Digital IC Design Lab

PART I

1) Use VDD=1.8V for 0.18um CMOS process, VDD=1.3V for 0.13um CMOS
Process and
VDD=1V for 0.09um CMOS Process.
Input Characteristics Analysis
a) Plot and analyse ID vs. VGS at different drain voltages for NMOS,
PMOS. Determine Vt
b) Plot log ID vs. VGS at particular drain voltage (high) for NMOS, PMOS
and determine IOFF and sub-threshold slope.
Output Characteristics Analysis
a) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and
determine Channel
Length modulation factor.
b) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and
calculate gm, gds, gm/gds, and unity gain frequency. Tabulate your result
according to technologies and comment on it.

1
Input Characteristics Analysis

1. VDD=1.8V for 0.18um NMOS

* NMOS characteristics
*TECHNOLOGY: SCN018
FEATURE SIZE: 0.18 microns

***************library file***************
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3661665
+K1 = 0.5857155 K2 = 2.994278E-3 K3 = 3.556898E-3
+K3B = 1.8784845 W0 = 1E-7 NLX = 1.80374E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.2506467 DVT1 = 0.3605386 DVT2 = 0.0408777
+U0 = 269.1687827 UA = -1.424122E-9 UB = 2.475132E-18
+UC = 7.558213E-11 VSAT = 1.070462E5 A0 = 1.9772757
+AGS = 0.45153 B0 = 2.56812E-7 B1 = 5E-6
+KETA = -0.0130762 A1 = 2.024625E-4 A2 = 0.8237527
+RDSW = 105 PRWG = 0.4945196 PRWB = -0.2
+WR =1 WINT = 1.880796E-9 LINT = 1.401095E-8
+XL =0 XW = -1E-8 DWG = -2.161747E-9
+DWB = 8.373845E-9 VOFF = -0.0936982 NFACTOR = 2.2128214
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.671776E-3 ETAB = 9.400138E-6
+DSUB = 0.0128511 PCLM = 0.7712839 PDIBLC1 = 0.1468288
+PDIBLC2 = 2.967266E-3 PDIBLCB = -0.1 DROUT = 0.6975638
+PSCBE1 = 4.088149E10 PSCBE2 = 2.354872E-9 PVAG = 0.0106191
+DELTA = 0.01 RSH = 6.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11

2
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 9.37E-10 CGSO = 9.37E-10 CGBO = 1E-14
+CJ = 9.555366E-4 PB = 0.8 MJ = 0.3827435
+CJSW = 2.69781E-10 PBSW = 0.8 MJSW = 0.145082
+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.145082
+CF =0 PVTH0 = 2.401607E-4 PRDSW = -3.1167685
+PK2 = 6.948372E-4 WKETA = -2.542534E-4 LKETA = -5.176493E-3
+PU0 = 7.5752863 PUA = 1.590549E-11 PUB = 3.528309E-24
+PVSAT = 1.522996E3 PETA0 = 1.003159E-4 PKETA = -3.041391E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3944719
+K1 = 0.5828995 K2 = 0.0266823 K3 =0
+K3B = 14.3383713 W0 = 1E-6 NLX = 1.373459E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.6336613 DVT1 = 0.2409053 DVT2 = 0.1
+U0 = 112.690631 UA = 1.417849E-9 UB = 1.12483E-21
+UC = -1E-10 VSAT = 1.850699E5 A0 = 1.7532818
+AGS = 0.375203 B0 = 3.569636E-7 B1 = 1.12458E-6
+KETA = 0.0205518 A1 = 0.4474986 A2 = 0.3631955
+RDSW = 243.82298 PRWG = 0.5 PRWB = 0.5
+WR =1 WINT = 0 LINT = 2.551606E-8
+XL =0 XW = -1E-8 DWG = -4.374325E-8
+DWB = 2.595671E-10 VOFF = -0.0937437 NFACTOR = 2

3
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1136843 ETAB = -0.0748821
+DSUB = 1.0613195 PCLM = 2.4303317 PDIBLC1 = 7.845168E-4
+PDIBLC2 = 0.0239307 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 3.207414E9 PSCBE2 = 9.282296E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.34E-10 CGSO = 6.34E-10 CGBO = 1E-14
+CJ = 1.148543E-3 PB = 0.8476511 MJ = 0.4067434
+CJSW = 2.382898E-10 PBSW = 0.8222976 MJSW = 0.3300124
+CJSWG = 4.22E-10 PBSWG = 0.8222976 MJSWG = 0.3300124
+CF =0 PVTH0 = 3.507137E-3 PRDSW = 17.811338
+PK2 = 3.610481E-3 WKETA = 0.0334716 LKETA = -3.202602E-3
+PU0 = -2.0541594 PUA = -8.93082E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1.003159E-4 PKETA = -1.696047E-3 )
*****************************************************

.PARAM
.OPTION POST
**** main ckt****************************************

M1 vdd ng 0 0 nmos W=360n L=180n

R1 in ng 50
Vdd vdd 0 1.8v

4
 Vin in 0 1.8v

*** SIMULATION Commands ***

.op
.dc Vin 0 1.8 0.05 Vdd 0 1.8 0.3
.probe dc i(m1)
.load current current

.end
*****************************

Waveform for ID vs VGS

Vt= 351.8578m

5
VDD=1.3V FOR 0.13um NMOS
 Add library files .

.PARAM
.OPTION POST
**** main ckt****************************************

M1 vdd ng 0 0 nmos W=360n L=130n

R1 in ng 50
Vdd vdd 0 1.3v
Vin in 0 1.3v

*** SIMULATION Commands ***

.op
.dc Vin 0 1.3 0.05 Vdd 0 1.3 0.3
.probe dc i(m1)
.load current current

.end

6
WAVEFORM for ID vs VGS
Vt=280.1352m

VDD=1V for 0.09un

 Add library file
.OPTION POST
.PARAM
*** NETLIST Description ***

M1 vdd ng 0 0 nmos W=360n L=90n

R1 in ng 50
Vdd vdd 0 1v
Vin in 0 0.5v
*** SIMULATION Commands ***
.op
.dc Vin 0 0.5 0.1 Vdd 0 1 0.05
.probe dc i(m1)
.end

7
WAVEFORM FOR ID vs VGS
Vt= 198.5274m

8
 PMOS VDD=1.8V for 0.18um
* PMOS Characteristics
.MODEL NMOS NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3661665
+K1 = 0.5857155 K2 = 2.994278E-3 K3 = 3.556898E-3
+K3B = 1.8784845 W0 = 1E-7 NLX = 1.80374E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.2506467 DVT1 = 0.3605386 DVT2 = 0.0408777
+U0 = 269.1687827 UA = -1.424122E-9 UB = 2.475132E-18
+UC = 7.558213E-11 VSAT = 1.070462E5 A0 = 1.9772757
+AGS = 0.45153 B0 = 2.56812E-7 B1 = 5E-6
+KETA = -0.0130762 A1 = 2.024625E-4 A2 = 0.8237527
+RDSW = 105 PRWG = 0.4945196 PRWB = -0.2
+WR =1 WINT = 1.880796E-9 LINT = 1.401095E-8
+XL =0 XW = -1E-8 DWG = -2.161747E-9
+DWB = 8.373845E-9 VOFF = -0.0936982 NFACTOR = 2.2128214
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.671776E-3 ETAB = 9.400138E-6
+DSUB = 0.0128511 PCLM = 0.7712839 PDIBLC1 = 0.1468288
+PDIBLC2 = 2.967266E-3 PDIBLCB = -0.1 DROUT = 0.6975638
+PSCBE1 = 4.088149E10 PSCBE2 = 2.354872E-9 PVAG = 0.0106191
+DELTA = 0.01 RSH = 6.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5

9
+CGDO = 9.37E-10 CGSO = 9.37E-10 CGBO = 1E-14
+CJ = 9.555366E-4 PB = 0.8 MJ = 0.3827435
+CJSW = 2.69781E-10 PBSW = 0.8 MJSW = 0.145082
+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.145082
+CF =0 PVTH0 = 2.401607E-4 PRDSW = -3.1167685
+PK2 = 6.948372E-4 WKETA = -2.542534E-4 LKETA = -5.176493E-3
+PU0 = 7.5752863 PUA = 1.590549E-11 PUB = 3.528309E-24
+PVSAT = 1.522996E3 PETA0 = 1.003159E-4 PKETA = -3.041391E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3944719
+K1 = 0.5828995 K2 = 0.0266823 K3 =0
+K3B = 14.3383713 W0 = 1E-6 NLX = 1.373459E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.6336613 DVT1 = 0.2409053 DVT2 = 0.1
+U0 = 112.690631 UA = 1.417849E-9 UB = 1.12483E-21
+UC = -1E-10 VSAT = 1.850699E5 A0 = 1.7532818
+AGS = 0.375203 B0 = 3.569636E-7 B1 = 1.12458E-6
+KETA = 0.0205518 A1 = 0.4474986 A2 = 0.3631955
+RDSW = 243.82298 PRWG = 0.5 PRWB = 0.5
+WR =1 WINT = 0 LINT = 2.551606E-8
+XL =0 XW = -1E-8 DWG = -4.374325E-8
+DWB = 2.595671E-10 VOFF = -0.0937437 NFACTOR = 2
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1136843 ETAB = -0.0748821
+DSUB = 1.0613195 PCLM = 2.4303317 PDIBLC1 = 7.845168E-4
+PDIBLC2 = 0.0239307 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 3.207414E9 PSCBE2 = 9.282296E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.5 MOBMOD = 1

10
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.34E-10 CGSO = 6.34E-10 CGBO = 1E-14
+CJ = 1.148543E-3 PB = 0.8476511 MJ = 0.4067434
+CJSW = 2.382898E-10 PBSW = 0.8222976 MJSW = 0.3300124
+CJSWG = 4.22E-10 PBSWG = 0.8222976 MJSWG = 0.3300124
+CF =0 PVTH0 = 3.507137E-3 PRDSW = 17.811338
+PK2 = 3.610481E-3 WKETA = 0.0334716 LKETA = -3.202602E-3
+PU0 = -2.0541594 PUA = -8.93082E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1.003159E-4 PKETA = -1.696047E-3 )
*
*Use VDD=1.8V for 0.18um
.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=360n L=180n
R1 in ng 50
Vdd vdd 0 1.8v
Vin in 0 1.8v
*** SIMULATION Commands ***
.op
.dc Vin -1.8 0 0.05 Vdd -1.8 0 0.3
.probe dc i(m1)

.end

11
WAVEFORM for ID vs VGS
Vt=-201.9340m

VDD=1.3V FOR 0.13um

 Add library files.

.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=360n L=130n
R1 in ng 50
Vdd vdd 0 1.3v
Vin in 0 1.3v

*** SIMULATION Commands ***

.op
.dc Vin -1.3 0 0.05 Vdd -1.3 0 0.3
.probe dc i(m1)

12
.end

WAVEFORM for ID vs VGS

Vt= -239.4144m

13
 VDD=1V for 0.09un
 Add library file
.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=180n L=90n
R1 in ng 50
Vdd vdd 0 1v
Vin in 0 1v
*** SIMULATION Commands ***
.op
.dc Vin -1 0 0.05 Vdd -1 0 0.3
.probe dc i(m1)
.end

14
WAVEFORM for ID vs VGS
Vt= -113.9333m

b) Plot log ID vs. VGS at particular drain voltage (high) for NMOS, PMOS and
determine IOFF and sub-threshold slope
for nmos 180n
 Add library file
M1 vdd ng 0 0 nmos W=360n L=180n
R1 in ng 50
Vdd vdd 0 1.8v
Vin in 0 1.8v
*** SIMULATION Commands ***.op
.dc Vin 0 1.8 0.05 Vdd 0 1.8 1.8
.probe dc i(m1)
.load current current
.end

15
WAVEFORM

IOFF=304.31p sub-threshold =503.22n

For nmos 130n

.OPTION POST
.PARA
*** NETLIST Description ***
M1 vdd ng 0 0 nmos W=260n L=130n
R1 in ng 50
Vdd vdd 0 1.3v
Vin in 0 1.3v
*** SIMULATION Commands ***
.op
.dc Vin 0 1.3 0.05 Vdd 0 1.3 1.3
.probe dc i(m1)
.load current current
.end

16
WAVEFORM
IOFF=208.02p sub-threshold =1.5678u

For nmos 90n

.OPTION POST
.PARA
*** NETLIST Description ***
M1 vdd ng 0 0 nmos W=180n L=90n
R1 in ng 50
Vdd vdd 0 1v
Vin in 0 1v
*** SIMULATION Commands ***
.op
.dc Vin 0 1 0.05 Vdd 0 1 1
.probe dc i(m1)
.load current current
.end

17
WAVEFORM
IOFF=819.32p sub-threshold =505.44n

18
Output Characteristics Analysis
VDD=1.8V for 0.18un
 Add library file
.OPTION POST
.PARAM
*** NETLIST Description ***
M1 vdd ng 0 0 nmos W=360n L=180n
R1 in ng 50
Vdd vdd 0 1.8v
Vin in 0 1.8v
*** SIMULATION Commands ***
.op
.dc Vdd 0 1.8 0.1 Vin 0 1.8 0.5
.probe dc i(m1)
.load current current

.end

19
WAVEFORM

Vgs= 1.8v , lamda=39.43u

Vgs= 1.5v ,lamda=30.89u
Vgs= 1.2v ,lamda=22.63u
Vgs= 0.5v ,lamda=7.89u
Vgs= 0.2v ,lamda=59.88n

20
VDD=1.3V for 0.13un
 Add library file

.OPTION POST
.PARA
*** NETLIST Description ***
M1 vdd ng 0 0 nmos W=260n L=130n
R1 in ng 50
Vdd vdd 0 1.3v
Vin in 0 1.3v
*** SIMULATION Commands ***
.op
.dc Vdd 0 1.3 0.01 Vin 0 1.3 0.5
.probe dc i(m1)
.load current current

.end

21
WAVEFORM

Vgs=1.3v, lamda=28.77u
Vgs=1v, lamda=12.58u
Vgs=0.5v, lamda=4.33u
Vgs=0.2v, lamda=48.26n

22
VDD=1V for 0.09un
 Add library file
.OPTION POST
.PARAM
*** NETLIST Description ***

M1 vdd ng 0 0 nmos W=180n L=90n

R1 in ng 50
Vdd vdd 0 1v
Vin in 0 1v

*** SIMULATION Commands ***

.op
.dc Vdd 0 1 0.01 Vin 0 1 0.5
.probe dc i(m1)
.load current current

.end

23
WAVEFORM

Vgs=1v, lamda=22.75u
Vgs=0.5v,lamda=13.185u
Vgs=0.1v,lamda=13.45n

24
PMOS ID VS VDS
VDD=1.8V for 0.18um
 Add library file

.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=360n L=180n
R1 in ng 50
Vdd vdd 0 1.8v
Vin in 0 1.8v
*** SIMULATION Commands ***
.op
.dc Vdd -1.8 0 0.1 Vin -1.8 0 0.3
.probe dc i(m1)

.end

25
WAVEFORM

Vgs=-1.8v, lamda=34.24u
Vgs=-1.5v, lamda=24.09u
Vgs=-1v, lamda=13.88u
Vgs=-0.5v, lamda=3.4u
Vgs=0.1v, lamda=9.56p

26
VDD=1.3V FOR 0.13um
 Add library files.

.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=260n L=130n
R1 in ng 50
Vdd vdd 0 1.3v
Vin in 0 1.3v

*** SIMULATION Commands ***

.op
.dc Vdd -1.3 0 0.1 Vin -1.3 0 0.3
.probe dc i(m1)
.end

27
WAVEFORM

Vgs=-1.3v,lamda=23.36u
Vgs=-1v,lamda=15.10u
Vgs=-0.1v,lamda=2.47n

28
VDD=1V for 0.09un
 Add library file
.PARAM
.OPTION POST
M1 vdd ng 0 0 pmos W=180n L=90n
R1 in ng 50
Vdd vdd 0 1v
Vin in 0 1v

*** SIMULATION Commands ***

.op
.dc Vdd -1 0 0.1 Vin -1 0 0.3
.probe dc i(m1)
.end

29
WAVEFORM

Vgs=-1v,lamda=16.16u
Vgs=-0.5v,lamda=4.63u
Vgs=-0.1v,lamda=9.07u

30
 b) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and
calculate gm, gds, gm/gds, and unity gain frequency. Tabulate your result
according to technologies and comment on it.

NOTING DOWN THE VALUES FROM EDITE LL

Technology 180n 130n 90n

MOSFET NMOS PMOS NMOS PMOS NMOS PMOS
gm 186.58u 72.76n 256.77u 57.22n 156.85u 217.16n
gds 30.67u 1.89n 17.86u 4.72n 16.93u 19.19n
gm\gds 6.08 38.49 14.37 12.12 9.26 11.31
unity gain frequency 309.6n 145.43M 475.04n 119.15M 540.02n 1.03n

31
2) Use VDD=1.8V for 0.18um CMOS process, VDD=1.2V for
0.13um CMOS Process and
VDD=1V for 0.09um CMOS Process.
a) Perform the following
i. Plot VTC curve for CMOS inverter and thereon plot dVout
vs. dVin and determine
Transition voltage and gain g. Calculate VIL, VIH, NMH,
NML for the inverter.
ii. Plot VTC for CMOS inverter with varying VDD.
iii. Plot VTC for CMOS inverter with varying device ratio.
b) Perform transient analysis of CMOS inverter with no load and
with load and determine
tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE =
2V, Cload = 50fF)

32
VDD=1.8V for 0.18um CMOS process

*TECHNOLOGY: SCN018
FEATURE SIZE: 0.18 microns

.MODEL NMOS NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3661665
+K1 = 0.5857155 K2 = 2.994278E-3 K3 = 3.556898E-3
+K3B = 1.8784845 W0 = 1E-7 NLX = 1.80374E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.2506467 DVT1 = 0.3605386 DVT2 = 0.0408777
+U0 = 269.1687827 UA = -1.424122E-9 UB = 2.475132E-18
+UC = 7.558213E-11 VSAT = 1.070462E5 A0 = 1.9772757
+AGS = 0.45153 B0 = 2.56812E-7 B1 = 5E-6
+KETA = -0.0130762 A1 = 2.024625E-4 A2 = 0.8237527
+RDSW = 105 PRWG = 0.4945196 PRWB = -0.2
+WR =1 WINT = 1.880796E-9 LINT = 1.401095E-8
+XL =0 XW = -1E-8 DWG = -2.161747E-9
+DWB = 8.373845E-9 VOFF = -0.0936982 NFACTOR = 2.2128214
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.671776E-3 ETAB = 9.400138E-6
+DSUB = 0.0128511 PCLM = 0.7712839 PDIBLC1 = 0.1468288
+PDIBLC2 = 2.967266E-3 PDIBLCB = -0.1 DROUT = 0.6975638
+PSCBE1 = 4.088149E10 PSCBE2 = 2.354872E-9 PVAG = 0.0106191
+DELTA = 0.01 RSH = 6.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4

33
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 9.37E-10 CGSO = 9.37E-10 CGBO = 1E-14
+CJ = 9.555366E-4 PB = 0.8 MJ = 0.3827435
+CJSW = 2.69781E-10 PBSW = 0.8 MJSW = 0.145082
+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.145082
+CF =0 PVTH0 = 2.401607E-4 PRDSW = -3.1167685
+PK2 = 6.948372E-4 WKETA = -2.542534E-4 LKETA = -5.176493E-3
+PU0 = 7.5752863 PUA = 1.590549E-11 PUB = 3.528309E-24
+PVSAT = 1.522996E3 PETA0 = 1.003159E-4 PKETA = -3.041391E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3944719
+K1 = 0.5828995 K2 = 0.0266823 K3 =0
+K3B = 14.3383713 W0 = 1E-6 NLX = 1.373459E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.6336613 DVT1 = 0.2409053 DVT2 = 0.1
+U0 = 112.690631 UA = 1.417849E-9 UB = 1.12483E-21
+UC = -1E-10 VSAT = 1.850699E5 A0 = 1.7532818
+AGS = 0.375203 B0 = 3.569636E-7 B1 = 1.12458E-6
+KETA = 0.0205518 A1 = 0.4474986 A2 = 0.3631955
+RDSW = 243.82298 PRWG = 0.5 PRWB = 0.5
+WR =1 WINT = 0 LINT = 2.551606E-8
+XL =0 XW = -1E-8 DWG = -4.374325E-8
+DWB = 2.595671E-10 VOFF = -0.0937437 NFACTOR = 2
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1136843 ETAB = -0.0748821

34
+DSUB = 1.0613195 PCLM = 2.4303317 PDIBLC1 = 7.845168E-4
+PDIBLC2 = 0.0239307 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 3.207414E9 PSCBE2 = 9.282296E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.34E-10 CGSO = 6.34E-10 CGBO = 1E-14
+CJ = 1.148543E-3 PB = 0.8476511 MJ = 0.4067434
+CJSW = 2.382898E-10 PBSW = 0.8222976 MJSW = 0.3300124
+CJSWG = 4.22E-10 PBSWG = 0.8222976 MJSWG = 0.3300124
+CF =0 PVTH0 = 3.507137E-3 PRDSW = 17.811338
+PK2 = 3.610481E-3 WKETA = 0.0334716 LKETA = -3.202602E-3
+PU0 = -2.0541594 PUA = -8.93082E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1.003159E-4 PKETA = -1.696047E-3 )
*

**Use VDD=1.8V for 0.18um

.PARAM
.OPTION POST

M1 3 1 0 0 nmos l=180n W=360n

M2 3 1 2 2 pmos l=180n W=720n

v1 2 0 1.8v

35
v2 1 0 PULSE(0V 1.8V 0NS 0NS 0NS 5NS 10NS)

*c1 3 0 50f
.TRAN 0.1NS 15NS
.Dc v2 0 1.8 0.001

*.print dv2(dv1)
.end

dVout vs. dVin

dvout\dvin=-6.279
similarly we can try it for 130n n 90n and we can compare.

36
To find NMH AND NML

From graph
VOH=1.695V, VIL=0.674V
VOL=0.114V, VIH=0.920V
NMH=VOH-VIH=0.775
NML=VIL-VOL=0.56

37
Transition voltage
From graph Vm=0.8125

VDD=1.2V for 0.13um

.PARAM
.OPTION POST

M1 3 1 0 0 nmos l=130n W=360n

M2 3 1 2 2 pmos l=130n W=720n

v1 2 0 1.2v
v2 1 0 PULSE(0V 1.2V 0NS 0NS 0NS 5NS 10NS)
*c1 3 0 50f
.TRAN 0.1NS 15NS
.Dc v2 0 1.2 0.001

*.print dv2(dv1)
.end

38
WAVEFORM

VOH=1.1641V
VIL=0.5067V
VOL=0.03100V
VIH=0.61928V
NMH=0.5448V
NML=0.4757V
VM=0.56V

39
VDD=1V for 0.09um
.PARAM
.OPTION POST

M1 3 1 0 0 nmos l=90n W=360n

M2 3 1 2 2 pmos l=90n W=720n

v1 2 0 1v
v2 1 0 PULSE(0V 1V 0NS 0NS 0NS 5NS 10NS)

*c1 3 0 50f
.TRAN 0.1NS 15NS
.Dc v2 0 1 0.001

*.print dv2(dv1)
.end

40
WAVEFORM

VOH=0.9424V
VOL=0.0733V
VIH=0.5604V
VIL=0.37402V
NMH=0.382V
NML=0.3007V
VM=0.47V

41
VTC for CMOS inverter with varying VDD
For 180nm technology
VDD=1.2V, 1V,0.9V, 0.1V

For 130nm technology

VDD= 0.8V,2V,1.2V

For 130nm technology

42
VDD= 0.8V,2V,1V

OBESRVATION OF VARING VDD

AS we change VDD , Vm also changes .

AT particular value of VDD CMOS INV lesser its functionality

Ex: 0.1V in 180nm

43
VTC for CMOS inverter with varying device ratio

IDEAL L=180 W=180

NMOS 180 180

PMOS (CASE1) 180 300

(CASE2) 180 750

FROM GRAPH
………… W=750
- - - - - -W=180
-----------W=300

44
CHANGING WIDTH OF NMOS
IDEAL L=180 W=180
NMOS(CASE1) 180 350
(CASE2) 180 800
PMOS 180 180

FROM GRAPH
………W=350
- - - - - -W=800
----------W=180
OBERVATION FOR DEVICE RATIO
 Device ratio is one of the important parameter while designing any digital
circuit, the driving capability is dependent on device ratio.
 If the device ratio of CMOS INV changes the corresponding ON and OFF timing
of PMOS and NMOS also changes in graph
 From the above graph it is observed that by changing the width of PMOS (W),
ON state and OFF state of PMOS and NMOS alter, i.e., if the w of PMOS is
increased the corresponding on state of PMOS increases and on state of NMOS
decreases
 Similarly we can do it for 130n and 90n and compere it

45
b) Perform transient analysis of CMOS inverter with no load and with load and
determine
tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload =
50fF)

.MODEL NMOS NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3661665
+K1 = 0.5857155 K2 = 2.994278E-3 K3 = 3.556898E-3
+K3B = 1.8784845 W0 = 1E-7 NLX = 1.80374E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.2506467 DVT1 = 0.3605386 DVT2 = 0.0408777
+U0 = 269.1687827 UA = -1.424122E-9 UB = 2.475132E-18
+UC = 7.558213E-11 VSAT = 1.070462E5 A0 = 1.9772757
+AGS = 0.45153 B0 = 2.56812E-7 B1 = 5E-6
+KETA = -0.0130762 A1 = 2.024625E-4 A2 = 0.8237527
+RDSW = 105 PRWG = 0.4945196 PRWB = -0.2
+WR =1 WINT = 1.880796E-9 LINT = 1.401095E-8
+XL =0 XW = -1E-8 DWG = -2.161747E-9
+DWB = 8.373845E-9 VOFF = -0.0936982 NFACTOR = 2.2128214
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.671776E-3 ETAB = 9.400138E-6
+DSUB = 0.0128511 PCLM = 0.7712839 PDIBLC1 = 0.1468288
+PDIBLC2 = 2.967266E-3 PDIBLCB = -0.1 DROUT = 0.6975638
+PSCBE1 = 4.088149E10 PSCBE2 = 2.354872E-9 PVAG = 0.0106191
+DELTA = 0.01 RSH = 6.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0

46
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 9.37E-10 CGSO = 9.37E-10 CGBO = 1E-14
+CJ = 9.555366E-4 PB = 0.8 MJ = 0.3827435
+CJSW = 2.69781E-10 PBSW = 0.8 MJSW = 0.145082
+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.145082
+CF =0 PVTH0 = 2.401607E-4 PRDSW = -3.1167685
+PK2 = 6.948372E-4 WKETA = -2.542534E-4 LKETA = -5.176493E-3
+PU0 = 7.5752863 PUA = 1.590549E-11 PUB = 3.528309E-24
+PVSAT = 1.522996E3 PETA0 = 1.003159E-4 PKETA = -3.041391E-3 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3944719
+K1 = 0.5828995 K2 = 0.0266823 K3 =0
+K3B = 14.3383713 W0 = 1E-6 NLX = 1.373459E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.6336613 DVT1 = 0.2409053 DVT2 = 0.1
+U0 = 112.690631 UA = 1.417849E-9 UB = 1.12483E-21
+UC = -1E-10 VSAT = 1.850699E5 A0 = 1.7532818
+AGS = 0.375203 B0 = 3.569636E-7 B1 = 1.12458E-6
+KETA = 0.0205518 A1 = 0.4474986 A2 = 0.3631955
+RDSW = 243.82298 PRWG = 0.5 PRWB = 0.5
+WR =1 WINT = 0 LINT = 2.551606E-8
+XL =0 XW = -1E-8 DWG = -4.374325E-8
+DWB = 2.595671E-10 VOFF = -0.0937437 NFACTOR = 2
+CIT =0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.1136843 ETAB = -0.0748821
+DSUB = 1.0613195 PCLM = 2.4303317 PDIBLC1 = 7.845168E-4

47
+PDIBLC2 = 0.0239307 PDIBLCB = -1E-3 DROUT = 0
+PSCBE1 = 3.207414E9 PSCBE2 = 9.282296E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.5 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 6.34E-10 CGSO = 6.34E-10 CGBO = 1E-14
+CJ = 1.148543E-3 PB = 0.8476511 MJ = 0.4067434
+CJSW = 2.382898E-10 PBSW = 0.8222976 MJSW = 0.3300124
+CJSWG = 4.22E-10 PBSWG = 0.8222976 MJSWG = 0.3300124
+CF =0 PVTH0 = 3.507137E-3 PRDSW = 17.811338
+PK2 = 3.610481E-3 WKETA = 0.0334716 LKETA = -3.202602E-3
+PU0 = -2.0541594 PUA = -8.93082E-11 PUB = 1E-21
+PVSAT = -50 PETA0 = 1.003159E-4 PKETA = -1.696047E-3 )
*
**Use VDD=1.8V for 0.18um
.PARAM
.OPTION POST

M1 3 1 0 0 nmos l=180n W=360n

M2 3 1 2 2 pmos l=180n W=720n

v1 2 0 2v
v2 1 0 PULSE(0V 2V 0NS 20NS 80NS 500NS 1000NS)

c1 3 0 50f

48
.TRAN 0.1NS 700NS
.meas tran delay_1 trig V(1) val='0.45' rise=1
+ targ v(3) val='0.45' fall=1
.end

Transient analysis of CMOS inverter with load FOR tpHL, tpLH, 20%-to-80%
tr

delay_1= 6.3889E-09 TPHL= 1.0889E-08 TPLH= 4.5000E-09

49
Transient analysis of CMOS inverter with load FOR tpHL, tpLH, 80%-to-20%
tr
 WRITING IN CODE: v2 1 0 PULSE (0V 2V 0NS 80NS 20NS 500NS
1000NS)

delay_1= 2.2004E-08 TPHL= 4.0004E-08 TPLH= 1.8000E-08

Transient analysis of CMOS inverter without load FOR tpHL, tpLH,

20%-to-80% tr
By removing: c1 3 0 50f in load code

50
delay_1= 5.4886E-09 TPHL= 9.9886E-09 TPLH= 4.5000E-09

Transient analysis of CMOS inverter without load FOR tpHL, tpLH,

80%-to-20% tr

delay_1= 2.0093E-08 TPHL= 3.8093E-08 TPLH= 1.8000E-08

 Similarly we can try it for 130n and 90n and compere it

51
c) Perform AC analysis of CMOS inverter with fanout 0 and fanout 1.
(Use Cin= 0.012pF,
Cload = 4pF, Rload = k)
For fanout0
 Add library files

.PARAM
.OPTION POST

M1 3 1 0 0 nmos l=180n W=360n

M2 3 1 2 2 pmos l=180n W=720n

v1 4 0 10 ac 1
v2 2 0 0v
cin1 1 4 0.012p
cout1 5 0 4p
rl1 3 5 1k
.op
.ac dec 10 1k 1meg
.print ac v(4) v(5) I(m1) I(m2)

.end

52
 WAVEFORM

For fanout1
 Add library files
.PARAM
.OPTION POST
M1 1 2 0 0 nmos l=180n W=360n
M2 1 2 3 3 pmos l=180n W=720n

M3 6 1 0 0 nmos l=180n W=360n

M4 6 1 3 3 pmos l=180n W=720n

cin1 2 5 0.012p
cout1 7 0 4p
rl1 6 7 1k
v1 5 0 10 ac 1

53
v2 3 0 0v
.op
.ac dec 10 1k 1meg
.print ac v(4) v(5) I(m1) I(m2)
.end

 Similarly we can try for 130n and 90n and compare it

54
3) Perform simulation to measure the power and delay for digital
circuits.
For NAND gate

 Add library files

.PARAM
.OPTION POST

m1 out in1 2 2 pmos l=180n w=720n

m2 out in2 2 2 pmos l=180n w=720n
m3 out in1 1 1 nmos l=180n w=360n
m4 1 in2 0 0 nmos l=180n w=360n
vdd 2 0 1.8v

vin1 in1 0 pulse(0v 1.8v 0ns 10ns 10ns 250ns 500ns)

vin2 in2 0 pulse(0v 1.8v 0ns 10ns 10ns 500ns 1000ns)

.tran 0.1ns 1000ns

.meas tran delay_1 trig v(in1) val='0.45' rise=1
+ targ v(out) val='0.45' fall=1

.meas tran avg_power avg power from=0.1n to=1000n

.op
.end

55
WAVEFORM

Total voltage source power dissipation= 15.1866p watts

delay_1= 4.2479E-09 targ= 6.7479E-09 trig= 2.5000E-09

avg_power= 1.4508E-06 from= 1.0000E-10 to= 1.0000E-06

56
PART II
Design, Write Verilog code for the circuits given below, Simulate, synthesize, view
report, Use EDA Tools like Cadence, Mentor Graphics, and Synopsis.
1) Adder
2) Magnitude Comparator
3) Parity Generator
4) D and T F/F
4) Universal Shift Register
5) Counter

Verilog commends in cadence

o Open terminal
o Csh
o Source cshrc2_new
o Mkdir _ program_name// to create new folder
o cd program_name
o gedit program_name.v
o ncvlog program_name.v –mess
o ncelab module name –access +wrc -mess
o ncsim module name –gui

57
1. ADDER

a. half adder

MODULE

module ha(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

assign carry=a&b; –This is same as and(carry,a,b)

assign sum=a^b; –This is same as xor(sum,a,b)

endmodule

58
TESTBENCH:
module halfaddert_b;

reg a;

reg b;

wire sum;

wire carry;

ha uut ( .a(a),.b(b),.sum(sum), .carry(carry));

initial begin

#10 a=1’b0;b=1’b0; –This is input a=0,b=0

#10 a=1’b0;b=1’b1; –This is input a=0,b=1

#10 a=1’b1;b=1’b0; –This is input a=1,b=0

#10 a=1’b1;b=1’b1; –This is input a=1,b=1

#10$stop;

End

59
OUTPUT WAVEFORM

60
b .FULL ADDER
MODULE
module full(a,b,cin,sum,carry);

input a,b,cin;

output sum,carry;

reg sum,carry;

always@(a,b,cin)

begin

sum=a^b^cin;

carry=(a&b)|(b&cin)|(cin&a);

end

endmodule

TESTBENCH
module tb;

reg a,b,cin;

wire sum,carry;

full dut(a,b,cin,sum,carry);

initial

begin

#10 a=1'b0;b=1'b0;cin=1'b0;

#10 a=1'b0;b=1'b0;cin=1'b1;

#10 a=1'b0;b=1'b1;cin=1'b0;

#10 a=1'b0;b=1'b1;cin=1'b1;

#10 a=1'b1;b=1'b0;cin=1'b0;

#10 a=1'b1;b=1'b0;cin=1'b1;

#10 a=1'b1;b=1'b1;cin=1'b0;

61
#10 a=1'b1;b=1'b1;cin=1'b1;

end

endmodule

OUTPUT WAVEFORM

62
2. MAGNITUDE COMPARATOR
MODULE
module comparator(a,b,eq,lt,gt);

input [3:0] a,b;

output reg eq,lt,gt;

always @(a,b)
begin
if (a==b)
begin
eq = 1'b1;
lt = 1'b0;
gt = 1'b0;
end
else if (a>b)
begin
eq = 1'b0;
lt = 1'b0;
gt = 1'b1;
end
else
begin
eq = 1'b0;
lt = 1'b1;
gt = 1'b0;
end
end
endmodule

TESTBENCH
module comparator_tst;
reg [3:0] a,b;
wire eq,lt,gt;

comparator DUT (a,b,eq,lt,gt);

initial
begin
a = 4'b1100;
b = 4'b1100;
#10;

63
 a = 4'b0100;
b = 4'b1100;
#10;

a = 4'b1111;
b = 4'b1100;
#10;

a = 4'b0000;
b = 4'b0000;
#10;
$stop;
end
endmodule

OUTPUT WAVEFORM

64
3. PARITY GENERATOR

MODULE

module parity(

input x,y,z,

output result);

xor (result,x,y,z); // SIMPLE XOR OPERATION : Gate Level Modeling

endmodule

TESTBENCH

module parity_tb;
reg x,y,z;
wire result;
parity dut(x,y,z,result);

initial begin

// Initialize Inputs

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

x = 0;

65
y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

66
#100;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

67
OUTPUT WAVEFORM

68
4. D FLIP FLOP
MODULE
module dflipflopmod(q, qb, d, clk);

output q;

output qb;

input d;

input clk;

reg q;

reg qb;

always @(posedge clk)

begin

q=d;

qb=~q;

end

endmodule

TESTBENCH

module d_tb;

reg d;

reg clk;

wire q;

wire qb;

dflipflopmod uut (.q(q),.qb(qb), .d(d), .clk(clk) );

initial begin

// Initialize Inputs

69
d = 0;

clk = 0;

end

always #3 clk=~clk;

always #5 d=~d;

initial #100 $stop;

endmodule

OUTPUT WAVEFORM

70
T FLIPFLOP
MODULE
module tffmod(q. qb, t, clk,);

input t;

input clk;

output reg q;

output reg qb;

initial q<=1’b0;

always @(posedge clk)

begin

q<=q^t;

qb<= ~q;

end

endmodule

TESTBECH
module tflipflopt_b;

reg t;

reg clk;

wire q, qb;

tffmod uut (q(q), .qb(qb), .t(t), .clk(clk));

initial begin

71
t = 0;

clk = 0;

#100;

end

always #3 clk=~clk;

always #5 t=~t;

initial #100 $stop;

endmodule

OUTPUT WAVEFORM

72
5 .UNIVERSAL SHIFT REGISTER

module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);

output reg [7:0] op;

input load;

input [1:0] sh_ro_lt_rt;

input [7:0] ip;

input clk, rst_a;

reg [7:0]temp;

always @(posedge clk or posedge rst_a)

begin

if (rst_a)

op = 0;

else

case(load)

1'b1:

begin //Load Input

temp = ip;

73
 // op = temp;

end

1'b0: //Operation

case (sh_ro_lt_rt)

2'b00: op = temp<<1; //Left Shift

2'b01: op = temp>>1; //Right Shift

2'b10: op = {temp[6:0],temp[7]}; //Rotate Left

2'b11: op = {temp[0], temp[7:1]}; //Rotate Right

default: $display("Invalid Shift Control Input");

endcase

default: $display("Invalid Load Control Input");

endcase

end

endmodule

74
TESTBENCH

module uni_shift_8b_tst;

reg [7:0] ip;

reg [1:0] sh_ro_lt_rt;

reg load,rst_a,clk;

wire [7:0] op;

uni_shift_8b u1 (.op(op), .ip(ip), .sh_ro_lt_rt(sh_ro_lt_rt), .load(load) , .rst_a(rst_a) ,

.clk(clk));

initial

begin

clk=1'b1;

forever #50 clk=~clk;

end

initial

begin

ip = 8'b11001100;

rst_a = 1'b1;

load = 1'b1;

75
sh_ro_lt_rt = 2'b00;

#100;

ip = 8'b10001100;

rst_a = 1'b0;

load = 1'b1;

sh_ro_lt_rt = 2'b01;

#100;

ip = 8'b11001100;

load = 1'b0;

sh_ro_lt_rt = 2'b01;

#100;

ip = 8'b10101101;

load = 1'b1;

76
sh_ro_lt_rt = 2'b01;

#100;

ip = 8'b11001101;

load = 1'b0;

sh_ro_lt_rt = 2'b01;

#100;

ip = 8'b11101100;

load = 1'b1;

sh_ro_lt_rt = 2'b10;

#100;

ip = 8'b11110000;

load = 1'b0;

sh_ro_lt_rt = 2'b10;

#100;

77
ip = 8'b11001100;

load = 1'b1;

sh_ro_lt_rt = 2'b11;

#100;

ip = 8'b11001101;

load = 1'b0;

sh_ro_lt_rt = 2'b11;

#100;

ip = 8'b11001000;

load = 1'b1;

sh_ro_lt_rt = 2'b11;

#100;

$stop;

end // initial begin

endmodule

78
OUTPUT WAVEFORM

79
6. COUNTER
module up_counter(input clk, reset, output[3:0] counter
);
reg [3:0] counter_up;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up <= 4'd0;
else
counter_up <= counter_up + 4'd1;
end
assign counter = counter_up;
endmodule

TESTBENCH
module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;

up_counter dut(clk, reset, counter);

initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule

80
OUTPUT WAVEFORM

81