Introduction To Nanoscience and Nanotechnology (Ece1006)

INTRODUCTION TO NANOSCIENCE AND
NANOTECHNOLOGY (ECE1006)
DA – 1
SLOT – A1
NAME – HARENSHYLAK M K
REG NO – 18BEC0681
TOPIC – NANOTECHNOLOGY AND ITS IMPACT ON CMOS
FACULTY NAME - MANGAIYARKARASI R

Complementary metal–oxide–semiconductor (CMOS) –
CMOS stands for Complementary Metal Oxide Semiconductor. A CMOS has a

unique design style, sometimes also called as complementary symmetric, as it
uses complementary and bilateral twain of p-type MOSFET and n-type MOSFET
the most important parameters of CMOS are high noise immunity and low static
power consumption. This happens due to the series combination draws significant
power only momentarily during switching between on and off states as Since one
transistor of the pair is always off, in result to this, CMOS devices produce less
amount of heat than any other logics. Unlike any other technology like transistor–
transistor logic (TTL) or NMOS logic, lesser amount of heat is wasted. When the
state of the device is not changed, still such types of logics have some standing
current. Due to CMOS technology a galactic denseness of logic can be enforced
on the very chip. This has been among the utmost reasons that CMOS became the
most used technology to be implemented in VLSI chips.
The DC power is not consumed due to the absence of a strictly resistive path to
ground. The symmetry of the device is maintained due to the pull-up and pull-
down resistances of the P- and N-channel transistors which are made equal. The
fabrication of CMOS is very difficult than the fabrication of a single NMOS
transistor as in CMOS there are two different types of transistors which are made
on the single substrate as shown in figure 1. shows a set of transient output
characteristics for a typical CMOS inverter are shown in Figure 2. In this example
the NMOS pull-down transistor has the marginal channel length and width of 3µ,
while the PMOS pull-up transistor has a channel width of almost double that of
NMOS. The output load for the inverter is another identical inverter, and the input
is a pulse with a 1 n.
Among the similar feature sizes the CMOS technology is said to be the cheapest.
There are many resources available in the CMOS technology. CMOS technology
can be further scaled down as per the technology. It draws a very little amount of
power at low frequency. CMOS technology can be used for mixed signals (digital
and analog) together as well, on a single chip. CMOS technology integrates large
number of transistors on the single chip. On the other hand, CMOS consumes a
lot of power at high frequency and the transconductance of CMOS are very low
than BJT. But on the other hand, the switch of a CMOS inverter is kept on for a
long time hence it can be damaged easily. There is a large propagation delay due
to the lump capacitance involved with it. The noise margin in CMOS are also
low.
III. CHALLENGES WITH NANOSCALE MOSFETs

Nanoscale MOSFET’s provides us with useful interpretation of the anomalies
that we might encounter in their SPICE simulations, these SPICE tools also let us
know the future trends and the limitations of the scaling of the device. In the next
section, we are going to put emphasis on these phenomena. We will start of with
the introduction to the overview of scaling trend of silicon-based planar bulk
MOSFETs and spot light the challenges to be solved. Ongoing approaches to
control all these small-geometry effects such as increased leakage currents,
threshold voltage variations, weakened gate controllability over the channel, and
increased in S/D resistances will be discussed.
IV. CARBON NANO TUBES FET

Carbon nanotubes (CNTs) were recognized in late nineties, CNT’s are allotropes
of carbon having a cylinder like structure. The length-to-diameter ratio of Nano
tubes is up to 132,000,000:1. There are certain unique properties about these
cylindrical carbon molecules, the thermal conductivities , mechanical and
electrical properties of CNT’s are quite extraordinary which make them very
important for nanotechnology, Carbon Nano tubes are used in various area’s like
electronics, optics and in number of fields of materials science and technology.
Carbon Nano tubes uses thick sheets of carbon called graphene, CNT belong to
the fullerene family and their name is inspired by their long and hollow structure.
These carbon nanotubes can be of metals or semiconductors depending upon the

method on which it is rolled. These sheets are rolled at specific and discrete
angles, which are called as chiral. And the combo rolling angle and radius decides
the nanotube properties. The way CNT’s are rolled is called its chirality. There is
an advantage with the nanotubes that their threshold voltage can be easily
controlled. The band gap of CNT and their diameter are inversely proportional to
each other so either can be controlled by varying the other. Band gap of CNT’s
are inversely proportional to their diameters.
The Carbon Nano tubes have great strength precisely due to the nature of bonds
they inherit. The chemical bonding of nanotubes is composed entirely of sp2
bonds, which is same as that found in graphite. These sp2 bonds are stronger than
the sp3 bonds which are generally found in alkanes and diamond. Due to the
qualities like have high thermal conductivity, current carrying capacity, and
excellent mechanical and thermal stability nanotubes can be used as interconnects
in the future. Now importantly these CNT’s are used in CNTFET (carbon
nanotube field-effect transistor), these transistors use CNT’s as the channel
material instead of silicon which is used in routine CMOS technology. CNTFET
have a single carbon nanotube or an array of carbon nanotubes as the channel
material.
Now the challenges come into existence when the technology goes to 22nm and
so. At this very channel length fabrication and device performance issues comes
into picture. When we talk about CMOS technology there are a number of
limitations that a device has to face as the technology shrunk, few of the, electron
tunnelling through short channels and thin insulator films, variations in device
structure and doping, leakage currents, passive power dissipation, short channel
effects etc. These secondary effects can be reduced by using CNT’s as channel
material, where one of the ways is to use CNTFET’s. one of the greatest features
in Carbon Nano tube is that there is no is no boundary scattering because of the
lack of boundaries in the perfect and hollow cylinder structure of CNTs. CNT’s
allow only forward and back ward scattering as the material they use is quasi-1D.
These properties make CNT a reliable material to be used in future. Due to the
strong covalent carbon–carbon bonding, with sp2 configuration, makes carbon
nanotubes chemically inert. Also, carbon nanotubes are able to transport large
amounts of electric current. Carbon nanotubes are also able to conduct heat nearly
as well as diamond or sapphire, and due to their miniaturized dimensions, the
CNTFET uses much less power than a silicon-based device and have high speeds.
CNT’s are inert in nature due to the bonding arrangement and nature of bonds
CNTFET’s are capable of bearing various fabrications and device challenges, few
of them are electron tunnelling through short channels and thin insulator films,
variations in the structure of device and doping, leakage currents, passive power
dissipation, short channel effects etc. because of inert nature of CNT material
used they have high thermal conductivity, current carrying capacity, and excellent
mechanical and thermal stability .
Nano processors: Scaling Beyond CMOS Limits Using Nanotechnology –
Introduction: Moore's Law

Moore's Law states that the density of transistors on a chip will increase
exponentially - doubling in performance every two years. The computing industry
has managed to adhere to this law since it was first proposed by Gordon Moore
in 1965. However, this prediction only considers silicon-based CMOS
(complementary metal-oxide semiconductor) technology.
This technology has limits which will must eventually break the exponential
trend. This article explores some of the ways in which the lifetime of CMOS
microprocessors can be extended, and some of the technologies which are being
suggested as replacements.
Limits to CMOS Scaling

There are three main limits to the continued down-scaling of CMOS feature size:
 Capabilities of the fabrication method

 Decreasing switching performance
 Increasing leakage (spontaneous switching of states, leading to errors and
data corruption)
There have been multiple points in the history of computing where CMOS
technology has been predicted to hit a limit.
Engineers in the microchip industry have an excellent track record for getting
around seemingly unbreakable performance limits. Because of this, CMOS
technology and Moore's Law will probably continue for much longer than many
commentators currently claim.
However, as quantum effects begin to have a much stronger effect on the

behaviour of the electronic components in microprocessors, silicon will become
unworkable, and new materials and designs must be employed to continue to meet
the demand for increasing performance in microelectronics.
Carbon Nanotubes and Graphene as Transistor Materials
A large part of the buzz surrounding nanostructured carbon materials like carbon
nanotubes (CNTs) and graphene in the last few years has been centred on their
potential for use as transistors.
These materials have unique electronic properties, because of the quantum effects
of their dimensional restrictions. They have been shown to possess very useful
qualities for use in nanoelectronics.
However, the precise physical structure of the materials can lead to a large range
of properties, particularly in CNTs. There are difficulties associated with
manufacturing CNTs with a particular structure on a large scale, as most existing
techniques tend to produce a mixture of forms.
Fabrication and separation processes are getting better all the time, however.
Graphene is likely to start appearing in computing applications relatively soon.
Molecular Electronics
Molecular electronics aims to make components like transistors and logic gates
from single molecules. Several potential candidates for molecular devices like
these have been proposed.
However, a fully integrated chip using solely molecular components has not yet
been achieved, and there are some serious manufacturing issues to overcome
before the technology can be considered for commercial applications.
The benefits of molecular electronics would be extraordinary, however. The

power consumption and data density which would become achievable once the
initial design and manufacturing challenges have been overcome are incredible.
Molecular electronics is potentially capable of providing a clear pathway to sub-
nanometre chip architectures.
Graphene could be the basis of the next generation of

transistors. Image credit: LBL.gov
In February 2010, an article in Science was published reporting on joint work by

IBM and DARPA which created a graphene processor with a 240nm gate length
capable of a clock speed of 100GHz, around four times faster than any previous
graphene-based transistors. Silicon-based processors with a similar scale of
architecture only capable of around a 40GHz clock speed.
Post-CMOS Nanoelectronics: Primetime for nanotechnology solutions
Computer chips are what make ‘smart technology' smart. And silicon-based
CMOS nanoelectronics comprise the neurons of those electronic brains. Arguably
the world's most transformative technology in terms of economic, cultural and
social impact, silicon CMOS continues to plunge to ever-smaller device
dimensions and ever-expanding levels of integration. And although technologists
have long predicted the end of the technological ‘run' of CMOS advancement -
often referred to as Moore's Law - the fundamental physics of energy dissipation
in nanoscale Si transistors and Cu wiring on today's most advanced chips may
well be a challenge that cannot be answered by Si nanoelectronics. Indeed, it is
not likely that any conventional charge-based switch - no matter what the material
- will dramatically alter the cost per function curve that drives today's integrated
circuit (IC) technology, since resistive and capacitive parasitics intrinsic to IC
topologies effectively dominate system performance.
To put it bluntly, it looks as if a new nanoelectronic switch will be needed.

Considering the tremendous cost required to retool an entire industry for such a
fundamental technology change, a new switch cannot simply be 30% or 50%
faster than - or consume half the power of - a Si FET. Its system performance and
extendibility must be measured in orders of magnitude. It is hardly a surprise,
then, that nanotechnology is providing some of the most provocative solutions to
address this challenge. The core of these solutions - being pursued by many of
the world's leading university/industry/government research consortia, such as
CNSE's Institute for Nanoelectronics Discovery and Exploration (INDEX) - is to
exploit nanotechnology to replace multiple CMOS switches with a single
nanoscale logic element, i.e. a multi-function nanoscale gate. Perhaps the best
example is the use of a single atomic monolayer of carbon - graphene - not as a
semiconductor, but as an electron waveguide which can focus and direct electrons
much like photons are directed in optical fibers and lenses. The so-called
Veselago lens effect (described in 2007 by Cheianov and co-workers) in graphene
has the potential to combine devices and interconnects in the same atomic
monolayer constituting an ultra-low power field-programmable gate array
(FPGA). In this scenario, a single graphene focusing switch + interconnect could
replace as many as 200 conventional transistors. Researchers at CNSE's INDEX
Center are at the forefront of this critical development.
A similar nanotechnology-enabled solution to the challenge facing conventional

Si CMOS technology may come not from manipulating the electron via its
charge, but via its intrinsic magnetic properties (so-called ‘spin'). Spin is an
intrinsically quantum mechanical property. The nanotechnology of spin and
magnetism is what allows us to store more than one trillion bits of information on
hard drives no larger than a person's wallet. And now, that same nanotechnology
may be able to enable the logic operations that process those 1 trillion bits as well.
A dynamically reprogrammable logic gate (proposed by Sham and co-workers in
2007) relies solely on spin-based information transmission (not electric charge).
In principle, this type of gate can be employed in a cascading architecture and
support the same design fabrics that have been developed for Si CMOS over the
last 20 years while, perhaps, avoiding challenges associated with conventional
CMOS power dissipation. The fundamental nanoscale science and engineering
breakthroughs necessary to explore this potential are also a focus of CNSE's
INDEX initiative, along with similar research consortia across the globe.
CONCLUSION -
So, while Si CMOS-based nanoelectronics is facing its share of technology

challenges, the ever-expanding knowledge base of nanotechnology has no
shortage of game-changing alternatives from which to respond. Should you trade
in your Si chip for one made of carbon or one processing electron spin instead of
electron charge? Not yet. No technology known to mankind has been as
successful as Si nanoelectronics and it will be around for a long while. But don't
be surprised if R&D on carbon or spin-based devices starts to become more ‘D'
than ‘R'.
REFERENCES –
G. E. Moore, Electronics, Vol. 38, No. 8, April 19, 1965.
https://www.azonano.com/article.aspx?ArticleID=3060
https://en.wikipedia.org/wiki/CMOS
http://www.ijcse.net/docs/IJCSE16-05-05-028.pdf
G. E. Moore, International Electron Devices Meeting. Technical Digest

(Washington, DC ,1975 Dec. 1-3, IEEE Group on Electron Devices)
THANK YOU

Introduction To Nanoscience and Nanotechnology (Ece1006)

Uploaded by

Copyright:

Available Formats

Introduction To Nanoscience and Nanotechnology (Ece1006)

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Introduction To Nanoscience and Nanotechnology (Ece1006)

Uploaded by

Copyright:

Available Formats

INTRODUCTION TO NANOSCIENCE AND

TOPIC – NANOTECHNOLOGY AND ITS IMPACT ON CMOS

FACULTY NAME - MANGAIYARKARASI R

CMOS stands for Complementary Metal Oxide Semiconductor. A CMOS has a

III. CHALLENGES WITH NANOSCALE MOSFETs

IV. CARBON NANO TUBES FET

These carbon nanotubes can be of metals or semiconductors depending upon the

Nano processors: Scaling Beyond CMOS Limits Using Nanotechnology –

Introduction: Moore's Law

Limits to CMOS Scaling

 Capabilities of the fabrication method

However, as quantum effects begin to have a much stronger effect on the

The benefits of molecular electronics would be extraordinary, however. The

Graphene could be the basis of the next generation of

In February 2010, an article in Science was published reporting on joint work by

Post-CMOS Nanoelectronics: Primetime for nanotechnology solutions

To put it bluntly, it looks as if a new nanoelectronic switch will be needed.

A similar nanotechnology-enabled solution to the challenge facing conventional

So, while Si CMOS-based nanoelectronics is facing its share of technology

G. E. Moore, Electronics, Vol. 38, No. 8, April 19, 1965.

G. E. Moore, International Electron Devices Meeting. Technical Digest

You might also like