kid_s

CSE211

Computer Organization and

Design

Lecture : 3 Tutorial: 1 Practical: 0 Credit: 4

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Unit 1 : Basics of Digital Electronics

Introduction
Logic Gates
Flip Flops
Decoder
Encoder
Multiplexers
Demultiplexer

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Integrated Circuits

An IC is a small silicon semiconductors crystal called chip containing the

electronic components for digital gates.
- Various gates are interconnected inside chip to form required circuit.
- Chip is mounted in ceramic/plastic container connected to external pin

Small scale Integration (SSI) : less than 10 gates

Medium Scale Integration(MSI) : between 10 to 200 gates

(decoders, adders, registers)

Large Scale Integration(LSI) : between 200 and few thousands gates

( Processors, Memory Chips)

Very Large Scale Integration (VLSI) : Thousands of gate within

single package ( Large Memory Arrays, Complex Microcomputer Chips)

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 CSE211

Computer Organization and

Design

Lecture : 3 Tutorial: 2 Practical: 0 Credit: 4

KIDS Labs 13
Unit 1 : Basics of Digital Electronics

Introduction
Logic Gates
Flip Flops
Decoder
Encoder
Multiplexers
Demultiplexer
Registers

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Octal to Binary Encoder
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1 D1 A0
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1 D2
0 0 0 1 0 0 0 0 1 0 0 A1
0 0 1 0 0 0 0 0 1 0 1 D3
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
D4
A2
A0 = D1 + D3 + D5 + D7 D5
D6
A1 = D2 + D3 + D6 + D7
D7
A2 = D4 + D5 + D6 + D7

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A Demultiplexer, sometimes abbreviated DMUX is a circuit that has
one input and more than one output. It is used when a circuit wishes
to send a signal to one of many devices

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 When the load input is 1 , the
data in the four inputs are
transferred into the register with
the next positive transition of a
clock pulse

When the load input is 0, the

data inputs are inhibited and the D-
output of flip flop are connected to
their inputs.

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 CSE211
Computer Organization and Design

Register Transfer Language

Register Transfer

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Register Transfer and Micro-operations

Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

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Register Transfer Language

 Combinational and sequential circuits can be used to create simple

digital systems.

 These are the low-level building blocks of a digital computer.

 Simple digital systems are frequently characterized in terms of

 the registers they contain, and
 the operations that are performed on data stored in them

 The operations executed on the data in registers are called micro-

operations e.g. shift, count, clear and load

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Register Transfer Language

Internal hardware organization of a digital computer :

Set of registers and their functions

 Sequence of microoperations performed on binary

information stored in registers

Control signals that initiate the sequence of micro-

operations (to perform the functions)

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Register Transfer Language

 Rather than specifying a digital system in words, a specific notation is
used, Register Transfer Language

 The symbolic notation used to describe the micro operation transfer

among register is called a register transfer language

 For any function of the computer, the register transfer language can be
used to describe the (sequence of) micro-operations

 Register transfer language

 A symbolic language
 A convenient tool for describing the internal organization of
digital computers in concise/precise manner.
 Can also be used to facilitate the design process of digital
systems.
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Register Transfer
 Registers are designated by capital letters, sometimes followed by
numbers (e.g., A, R13, IR)
 Often the names indicate function:
 MAR - memory address register
 PC - program counter
 IR - instruction register

 Registers and their contents can be viewed and represented in various

ways
 A register can be viewed as a single entity:

MAR

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Register Transfer

• Designation of a register

- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

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Register Transfer
• Copying the contents of one register to another is a register transfer

• A register transfer is indicated as

R2  R1

 In this case the contents of register R1 are copied (loaded) into

register R2
 A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
 Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2

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Register Transfer
• A register transfer such as

R3  R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination
register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

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Control Functions

 Often actions need to only occur if a certain condition is true

 This is similar to an “if” statement in a programming language
 In digital systems, this is often done via a control signal, called a control
function
 If the signal is 1, the action takes place
 This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2  R1)

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Hardware Implementation of Controlled Transfers

Implementation of controlled transfer
P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

 The same clock controls the circuits that generate the control function and the
destination register
 Registers are assumed to use positive-edge-triggered flip-flops

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Basic Symbols in Register Transfer

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& Numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2 R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A B, B A

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 CSE211
Computer Organization and Design

Bus and Memory Transfers

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Register Transfer and Micro-operations 38

Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

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Connecting Registers - Bus Transfer

 In a digital system with many registers, it is impractical to have data and
control lines to directly allow each register to be loaded with the contents
of every possible other registers

 To completely connect n registers  n(n-1) lines

 O(n2) cost
 This is not a realistic approach to use in a large digital system

 Instead, take a different approach

 Have one centralized set of circuits for data transfer – the bus

 BUS STRUCTURE CONSISTS OF SET OF COMMON LINES, ONE FOR EACH BIT
OF A REGISTER THROUGH WHICH BINARY INFORMATION IS TRANSFERRED
ONE AT A TIME

 Have control circuits to select which register is the source, and which is the
destination
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Connecting Registers - Bus Transfer

 One way of constructing common bus system is with multiplexers

 Multiplexer selects the source register whose binary information is
kept on the bus.

 Construction of bus system for 4 register (Next Fig)

 4 bit register X 4
 four 4X1 multiplexer
 Bus selection S0, S1
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Connecting Registers - Bus Transfer

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Connecting Registers - Bus Transfer

 For a bus system to multiplex k registers of n bits each

 No. of multiplexer = n

 Size of each multiplexer = k x 1

 Construction of bus system for 8 register with 16 bits

 16 bit register X 8
 Sixteen 8X1 multiplexer
 Bus selection S0, S1, S2

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Connecting Registers - Bus Transfer

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Connecting Registers - Bus Transfer

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Memory Transfer
Memory is usually accessed in computer systems by putting the desired
address in a special register, the Memory Address Register (MAR, or AR)

M
Memory Read
AR
unit Write

Data out Data in

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Memory Read

 To read a value from a location in memory and load it into a

register, the register transfer language notation looks like this:

R1  M[MAR]

 This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Read (= 1) gets sent to the memory unit
3. The contents of the specified address are put on the
memory’s output data lines
4. These get sent over the bus to be loaded into register R1

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Memory Write

 To write a value from a register to a location in memory looks like

this in register transfer language:

M[MAR]  R1

 This causes the following to occur

1. The contents of the MAR get sent to the memory address
lines
2. A Write (= 1) gets sent to the memory unit
3. The values in register R1 get sent over the bus to the data
input lines of the memory
4. The values get loaded into the specified address in the
memory

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SUMMARY OF R. TRANSFER MICROOPERATIONS

A B 1.Transfer content of reg. B into reg. A

AR DR(AD) 2.Transfer content of AD portion of reg. DR into reg. AR
A  constant 3.Transfer a binary constant into reg. A
ABUS R1, R2 ← ABUS 4.Transfer content of R1 into bus A and, at the same time,
transfer content of bus A into R2
AR 5.Address register
DR 6.Data register
M[R] 7.Memory word specified by reg. R
M 8.Equivalent to M[AR]
DR  M 9.Memory read operation: transfers content of
memory word specified by AR into DR
M  DR 10.Memory write operation: transfers content of
DR into memory word specified by AR

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 CSE211
Computer Organization and Design

Arithmetic Microoperations

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Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Arithmetic Micro-operations

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

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MICROOPERATIONS

Computer system microoperations are of four types:

 Register transfer microoperations

 Arithmetic microoperations
 Logic microoperations
 Shift microoperations

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Arithmetic MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement
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Binary Adder

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Binary Adder-Subtractor

Binary Adder-Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

 Mode input M controls the operation

 M=0 ---- adder
 M=1 ---- subtractor
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Binary Incrementer

Binary Incrementer

A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

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Arithmetic Circuits
Cin
S1
S0

A0 X0 C0

S1 D0
S0
Y0
FAC1
B0 0
1 4x1
2
3
MUX
A1 X1 C1

S1 D1
S0 FA
B1 0 Y1 C2
1 4x1
2
3
MUX
A2 X2 C2

S1 D2
S0 FA
B2 0 Y2 C3
1 4x1
2
3
MUX
A3 X3 C3

S1 D3
S0 FA
B3 0 Y3 C4
1 4x1
2
3
MUX Cout
0 1

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 CSE211
Computer Organization and Design

Logic Microoperations
Shift Microoperations
Arithmetic Logic Shift Unit

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Register Transfer and Micro-operations 58

Overview

 Register Transfer Language

 Register Transfer

 Bus and Memory Transfers

 Arithmetic Micro-operations

 Logic Micro-operations

 Shift Micro-operations

 Arithmetic Logic Shift Unit

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Logic Micro operations

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Logic Microoperations

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Hardware Implementation
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

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Applications of Logic Microoperations

 Logic microoperations can be used to manipulate individual bits or a
portions of a word in a register

 Consider the data in a register A. In another register, B, is bit data that

will be used to modify the contents of A

 Selective-set AA+B
 Selective-complement AAB
 Selective-clear A  A • B’
 Mask (Delete) AA•B
 Clear AAB
 Insert A  (A • B) + C
 Compare AAB

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Applications of Logic Microoperations

1. In a selective set operation, the bit pattern in B is used to set certain bits in A

1 1 0 0 At
1010 B
1 1 1 0 At+1 (A  A + B)

If a bit in B is set to 1, that same position in A gets set to 1, otherwise that

bit in A keeps its previous value
2. In a selective complement operation, the bit pattern in B is used to
complement certain bits in A
1 1 0 0 At
1010 B

0 1 1 0 At+1 (A  A  B)
If a bit in B is set to 1, that same position in A gets complemented from its
original value, otherwise it is unchanged
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Applications of Logic Microoperations

3. In a selective clear operation, the bit pattern in B is used to clear certain bits
in A
1 1 0 0 At
1010 B

0 1 0 0 At+1 (A  A  B’)
If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is
unchanged
4. In a mask operation, the bit pattern in B is used to clear certain bits in A
1 1 0 0 At
1010 B

1 0 0 0 At+1 (A  A  B)

If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is

unchanged
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Applications of Logic Microoperations

5. In a clear operation, if the bits in the same position in A and B are the same,
they are cleared in A, otherwise they are set in A
1 1 0 0 At
1010 B

0 1 1 0 At+1 (A  A  B)

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Applications of Logic Microoperations

6. An insert operation is used to introduce a specific bit pattern into A register,
leaving the other bit positions unchanged
This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired positions
– Example
• Suppose you wanted to introduce 1010 into the low order four bits of A:
• 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

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Shift Microoperations
• There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into the serial input

• A right shift operation

Serial
input

• A left shift operation

Serial
input

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Logical Shift
• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

– shl for a logical shift left
– shr for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
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Circular Shift
• In a circular shift the serial input is the bit that is shifted out of the other
end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
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Arithmetic Shift
• An arithmetic shift is meant for signed binary numbers (integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• Sign bit : 0 for positive and 1 for negative
• The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation: 0

sign
bit

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Arithmetic Shift
• An left arithmetic shift operation must be checked for the overflow

0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3

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Hardware Implementation of Shift Microoperation

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Arithmetic Logic and Shift Unit

S3
S2 C
i
S1
S0

D
Arithmetic i

Circuit
Select

0 4x1
C i+1 F
1 i
MUX S3 S2 S1 S0 Cin Operation
2 0 0 0 0 0 F=A
3 0 0 0 0 1 F=A+1
0 0 0 1 0 F=A+B
E 0 0 0 1 1 F=A+B+1
Logic i 0 0 1 0 0 F = A + B’
Bi 0 0 1 0 1 F = A + B’+ 1
Circuit 0 0 1 1 0 F=A-1
A 0 0 1 1 1 F=A
i
0 1 0 0 X F=AB
shr
A 0 1 0 1 X F = A B
i-1 0 1 1 0 X F=AB
shl
A 0 1 1 1 X F = A’
i+1
1 0 X X X F = shr A
1 1 X X X F = shl A
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Computer Organization and Design

Instruction Codes
Computer Registers

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Overview

 Instruction Codes

 Computer Registers

 Computer Instructions

 Timing and Control

 Instruction Cycle

 Memory Reference Instructions

 Input-Output and Interrupt

 Complete Computer Description

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Introduction

• Organization of computer is defined by its :

• Internal Registers
• Timing and Control Structure
• Set of instructions that it uses

• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start with a
simplified processor model
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Basic Computer

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095
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Instruction
 Program
 A sequence of (machine) instructions
 Instruction
 binary code that specifies a sequence of microoperations for a
computer.
 The instructions of a program, along with any needed data are stored in
memory
 The CPU reads the next instruction from memory
 It is placed in an Instruction Register (IR)
 Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it

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Instruction Format
 Instruction Codes
 A group of bits that tell the computer to perform a specific operation (a
sequence of micro-operation)
 A computer instruction is often divided into two parts
 An opcode (Operation Code) that specifies the operation for that instruction
 Sometimes called as Macrooperation
 An address that specifies the registers and/or locations in memory to use for
that operation

 In the Basic Computer, the memory contains 4096 (= 212) words, we needs 12 bit to
specify which memory address this instruction will use

 In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing)

 Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode
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Instruction Format
 Sometimes the address bit of instruction code represent various different
information, classified into different Instruction formats :
 Immediate Instruction : when second part of instruction specifies operand

 When second part of address specify address :

 Direct Addressing : second part of instruction specifies address of an
operand
 Indirect Addressing : second part of instruction designates an address of a
memory in which the address of the operand is found

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

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Addressing Mode
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the operand), or
– Indirect address: the address in memory of the address in memory of the data to use
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +

AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to access an operand for a
computation-type instruction, or as the target address for a branch-type instruction
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Processor Register
 A processor has many registers to hold instructions, addresses, data, etc
 The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction to be executed
Since the memory in the Basic Computer only has 4096 locations,
the PC only needs 12 bits
 In a direct or indirect addressing, the processor needs to keep track of
what locations in memory it is addressing: The Address Register (AR) is
used for this
The AR is a 12 bit register in the Basic Computer
 When an operand is found, using either direct or indirect addressing, it
is placed in the Data Register (DR). The processor then uses this value as
data for its operation
 The Basic Computer has a single general purpose register – the
Accumulator (AC)

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Processor Register
 The significance of a general purpose register is that it can be referred to in
instructions
e.g. load AC with the contents of a specific memory location; store the contents of AC
into a specified memory location
 Often a processor will need a scratch register to store intermediate results
or other temporary data; in the Basic Computer this is the Temporary
Register (TR)
 The Basic Computer uses a very simple model of input/output (I/O)
operations
Input devices are considered to send 8 bits of character data to the processor
The processor can send 8 bits of character data to output devices
 The Input Register (INPR) holds an 8 bit character gotten from an input
device
 The Output Register (OUTR) holds an 8 bit character to be send to an
output device

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Processor Register
Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
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Common Bus System

 Basic computer : 8 register, a memory unit and a control unit

 The registers in the Basic Computer are connected using a bus

 This gives a savings in circuitry over complete connections between

registers

 Output of 7 register and memory connected to input of bus

 Specific output that is selected for bus lines will be determined by

selection variables S2, S1, S0

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Common Bus System

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR
DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD

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Common Bus System

 Three control lines, S2, S1, and S0 control which register the bus
selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

 Either one of the registers will have its load signal activated, or the
memory will have its write signal activated
Will determine where the data from the bus gets loaded
 Memory places its 16 bit output on bus when read input is
activated and S2S1S0=111

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Common Bus System

 4 register DR, AC, IR, TR is 16 bit. The 12-bit registers, AR and PC,
have 0’s loaded onto the bus in the high order 4 bit positions

 When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus

 INPR – connected to provide information to bus

- receives character from input device and transfer to AC
 OUTR – can only receive information from bus
- receives a character from AC and delivers to Output device

 Three types of input to AC :

 from AC : complement AC, Shift AC
 from DR : arithmetic and logic microoperation
 from INPR
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Common Bus System

 Bus lines connected to inputs of 6 registers and memory

 Three types of input to AC :

 from AC : complement AC, Shift AC
 from DR : arithmetic and logic microoperation
 from INPR

 Input/output data connected to common bus but memory address

connected to AR

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Computer Organization and Design
Computer Instructions
Timing and Control
Instruction Cycles
Memory Reference Instructions
Input Output and Interrupts
Complete Computer Description

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Overview

Instruction Codes

 Computer Registers

 Computer Instructions

 Timing and Control

 Instruction Cycle

 Memory Reference Instructions

 Input-Output and Interrupt

 Complete Computer Description

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Basic Computer Instructions

Basic Computer Instruction Format

1. Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

2. Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

3. Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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Basic Computer Instructions

 Only 3 bits are used for operation code

 It may seem computer is restricted to eight different

operations

 however register reference and input output instructions use

remaining 12 bit as part of operation code

 so total number of instruction can exceed 8

Infact total no. of instructions chosen for basic computer is 25

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Basic Computer
Hex Code
Instructions
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
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Instruction Set Completeness

A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable.

The set of instructions are said to be complete if computer includes a

sufficient number of instruction in each of the following categories :
 Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CMA, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/output Instructions
- Input and output
- INP, OUT
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Control Unit
 Control unit (CU) of a processor translates from machine instructions
to the control signals for the microoperations that implement them

 Control units are implemented in one of two ways

Hardwired Control
CU is made up of sequential and combinational circuits to generate the control
signals
Advantage : optimized to provide fast mode of operations
Disadvantage : requires changes in wiring if design has been modified
Microprogrammed Control
A control memory on the processor contains microprograms that activate the
necessary control signals

 We will consider a hardwired implementation of the control unit for

the Basic Computer

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Timing and Control

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
signals
logic

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

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Timing Signals
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC
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Instruction Cycle

 In Basic Computer, a machine instruction is executed in the following

cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

 After an instruction is executed, the cycle starts again at step 1, for the
next instruction

Note: Every different processor has its own (different) instruction cycle

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Fetch and Decode

Initially PC loaded with address of first instruction and Sequence counter

cleared to 0, giving timing signal T0

T0: AR PC

T1: IR  M [AR], PC  PC + 1

T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

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Fetch and Decode

Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
unit 7
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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Fetch and Decode

 Figure shows how first two statements are implemented in bus system

 At T0 :
 1. Place the content of PC into bus by making S2S1S0=010
 Transfer the content of bus to AR by enabling the LD input of AR

 At T1 :
 1. Enable read input of memory
 2. Place content of bus by making S2S1S0=111
 3. Transfer content of bus to IR by enabling the LD input of IR
 4. Increment PC by enabling the INR input of PC

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Determine the Type of Instructions

Start
SC <-- 0

T0
AR <-- PC

T1
IR <-- M[AR], PC <-- PC + 1

T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0

Fig : Flow chart for Instruction Cycle

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Determining Type of Instruction

D'7IT3: AR M[AR]

D'7I'T3: Nothing

D7I'T3: Execute a register-reference instr.

D7IT3: Execute an input-output instr.

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Register Reference Instruction

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11 e.g. rB11=CLA
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
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Memory Reference Instructions

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4

AND to AC //performs AND logic with AC and memory word specified by EA

D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

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Memory Reference Instructions

ADD to AC // add content of memory word specified by EA to value of AC
sum is transferred to AC and Carry to E (Extended Accumulator)

D1T4: DR  M[AR] Read operand

D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

LDA: Load to AC // Transfers memory word specified by memory address to AC

D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

STA: Store AC // Stores the content of AC into memory specified by EA

D3T4: M[AR]  AC, SC  0

BUN: Branch Unconditionally // Transfer program to instruction specified by EA

D4T4: PC  AR, SC  0

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Memory Reference Instructions

BSA: Branch and Save Return Address // 1. stores address of next instruction in sequence (PC) into
address specified by EA 2. EA+1 transfer to PC serve as 1st inst. In subroutine
M[AR]  PC, PC  AR + 1

BSA:
D 5 T4 : M[AR]  PC, AR  AR + 1
D 5 T5 : PC  AR, SC  0

BSA: Example
M[135]  21, PC  135 + 1=136

Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

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Memory Reference Instructions

ISZ: Increment and Skip-if-Zero

// increments the word specified by effective address,
and if incremented value=0 , PC incremented by 1

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

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Flow Chart - Memory Reference Instructions

Memory-reference instruction

AND ADD LDA STA

D 0T 4 D 1T 4 D 2T 4 D 3T 4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC

SC  0

D 0T 5 D 1T 5 D 2T 5
AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D 4T 4 D 5T 4 D 6T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D 5T 5 D 6T 5

PC  AR DR  DR + 1
SC  0
D 6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
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Input/Output and Interrupt

A Terminal with a keyboard and a Printer
Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit
Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the communication interface serially and with
the AC in parallel.
- The flags are needed to synchronize the timing difference between I/O device and
the computer
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Determining Type of Instruction

 FGI =1 when new information available at input device,

and cleared to 0 when information accepted by
computer

 Initially FGI=0, new key pressed , 8 bit alphanumeric

shifted to INPR and FGI=1, Computer checks flag if 1
then transfer content to AC and clear FGI to 0.

 Initially FGO=1,
- computer checks flag bit if 1, then OUTR  AC and
clears FGO=0
- O/P device accepts information prints character and
finally sets FGO=1.

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Input/Output Instructions
I/O instructions are needed for transferring info to and from AC register, for
checking the flag bits and for controlling interrupt facility

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

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Program controlled Input/Output

• Program-controlled I/O

-Continuous CPU involvement

CPU keeps checking flag bit. If 1 then initiates transfer
I/O takes valuable CPU time

-Difference in information flow rate makes this type of

transfer inefficient

• Alternative approach is to let external device inform the computer when

it is ready for transfer, in meantime computer can be busy with other task

- Interrupt

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Interrupt Initiated Input/Output

- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- When cleared (IEN=0) the computer cannot be interrupted
- When set (IEN=1) the computer can be interrupted

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Flow Chart of Interrupt Cycle

R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

INPR Input register - 8 bits

Fetch and decode Store return address OUTR Output register - 8 bits
instructions in location 0
M[0]  PC FGI Input flag - 1 bit
FGO Output flag - 1 bit
=0 IEN Interrupt enable - 1 bit
Execute IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch and save return address operation.
- At the beginning of the next instruction cycle, the instruction that is read from memory is in
address 1.
- At memory address 1, the programmer must store a branch instruction that sends the control to
an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0"
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Register Transfer Operations in Interrupt Cycle

Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
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Complete Computer Description

start
SC  0, IEN  0, R  0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref) INPR Input register - 8 bits

D7 OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit
=1 (I/O) =0 (Register) =1(Indir) =0(Dir) IEN Interrupt enable - 1 bit
I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

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Complete Computer Design

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
R1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0

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Complete Computer Design

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
HLT rB0: S0

Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: If(FGI=1) then (PC  PC + 1)
SKO pB8: If(FGO=1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0

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Design of a Basic Computer(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
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Design of a Basic Computer(BC)

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Design of a Basic Computer(BC)

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