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Gujarat Technological University

This document appears to be an exam for a Digital Electronics course, consisting of 5 questions covering various topics: 1. Question 1 has parts on binary conversion, subtraction using complement representation, and De Morgan's theorems. 2. Question 2 covers proofs about AND/OR gates, universal gates and how to realize Ex-OR and Ex-NOR using NAND, and a short note on error detection codes or Gray code. 3. Question 3 includes Boolean expression reduction, characteristics of logic families, minimizing using K-maps and realizing with gates, and comparisons of minimization methods and counters/registers. 4. Question 4 distinguishes combinational and sequential circuits, explains a full subtractor, covers

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50 views2 pages

Gujarat Technological University

This document appears to be an exam for a Digital Electronics course, consisting of 5 questions covering various topics: 1. Question 1 has parts on binary conversion, subtraction using complement representation, and De Morgan's theorems. 2. Question 2 covers proofs about AND/OR gates, universal gates and how to realize Ex-OR and Ex-NOR using NAND, and a short note on error detection codes or Gray code. 3. Question 3 includes Boolean expression reduction, characteristics of logic families, minimizing using K-maps and realizing with gates, and comparisons of minimization methods and counters/registers. 4. Question 4 distinguishes combinational and sequential circuits, explains a full subtractor, covers

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mtbhoye
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Seat No.: ________ Enrolment No.

___________

GUJARAT TECHNOLOGICAL UNIVERSITY


BE - SEMESTER–IV (NEW) EXAMINATION – WINTER 2018
Subject Code:2140910 Date:28/11/2018
Subject Name:Digital Electronics
Time: 02:30 PM TO 05:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
MARKS

Q.1 (a) Convert (0.6875)10 to binary equivalent number CH-1 03


(b) Using 10’s complement ,subtract (i) (72532-3250)10 CH-1 04
(ii) (3250-72532)10
(c) State and Prove De-Morgan’s theorems with necessary truth table. CH-3 07

Q.2 (a) Prove that a positive-logic AND gate is a negative-logic OR gate. CH-2 03
(b) Why NAND gate and NOR gate are known as universal gates? CH-2 04
Obtain Ex-OR and Ex-NOR using NAND.
(c) Write short note on error detection codes. CH-1 07
OR
(c) Write short note on Gray code. CH-1 07
Q.3 (a) Reduce the expression f= (B+BC) (B+𝐵̅ 𝐶)(B+D) CH-3 03
(b) Define the following general characteristics of logic families. (i) 04
Propagation delay time (ii) Noise Margin (iii) Fan – out CH-2
(iv) Power dissipation
(c) Minimize the following Boolean expression using K- Map and CH-3 07
realize it using logic gates.
F(A,B,C,D)=∑m(0,1,5,9,13,14,15)+d(3,4,7,10,11)
OR
Q.3 (a) Compare K-map and tabular method of minimization. CH-3 03
(b) Compare Counters and Registers. CH-5 04
(c) Express the Boolean function F=A+𝐴C in a sum of min-terms. CH-3 07
Q.4 (a) Distinguish between combinational and sequential logic circuits. CH-5 03
(b) Explain full- subtractor in brief. CH-4 04
(c) Write short note on Multiplexers. CH-4 07
OR
Q.4 (a) State the basic difference between synchronous and asynchronous 03
counters. CH-5
(b) Explain operation of 4 bit left shift register with necessary diagrams. CH-5 04
(c) Differentiate between level triggering and edge triggering of flip- 07
flops. Explain Master-Slave J-K flip-flop configuration. CH-5
Q.5 (a) Define following specification of ADC (i) Resolution (ii) Conversion 03
time (iii) Quantization error CH-7
(b) Compare between various types of ROM. CH-6 04
(c) Explain internal organization of RAM , Draw and explain with 07
necessary block diagram the process of writing in memory and
reading from memory also. CH-6
OR

1
Q.5 (a) Define following specifications of DAC (i) Resolution (ii) Accuracy 03
(iii) Settling time (iv) Monotonicity. CH-7
(b) Compare various D/A Converters. CH-7 04
(c) Describe operation of D/A converter with binary weighted resistors. CH-7 07

*************

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