8086 & 8088 Microprocessors

VDD (5V)
• 8086 Microprocessor (1978)
EE2323:Microprocessors & – 16-bit microprocessor
Computer Architecture – 20-bit Address Bus 20-bit
16-bit/ Address
– 16-bit Data Bus 8-bit data
8086/ bus
Spring 2013 – 6-byte instruction queue. bus
8088 control
Separate Data & Segment Registers

•••
– signals
• 8088 Microprocessor (1979)
8086/8088 Microprocessors CLK
– 16-bit microprocessor
– 20-bit Address Bus
Lecture 5 – 8-bit Data Bus
GND

March 04, 2013 – 4-byte instruction queue.

– Separate Data & Segment Registers

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8086/8088 Processor Microarchitecture 8086/8088 Processor Microarchitecture

• Micro-architecture is internal architecture of a Segment Control

processor General pins
Registers
purpose
• 8086/8088 microprocessors have pipelined micro- Registers
IP
architecture that employ parallel processing
Multiplexed
• Micro-architecture of 8086/8088 microprocessors Bus
consist of two independent processing units Address Generation
And Bus Control
– Bus interface Unit (BIU)
+5 V
– Execution Unit (EU) Operands GND
• BIU & EU make fetch & execution of instructions
independent operations Instruction
Clock
ALU Queue
• Both units execute in parallel and result in
efficient use of system bus and higher
Control Flags
performance
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Bus Interface Unit (BIU) Execution Unit (EU)
• BIU is 8086/8088 interface to the outside world • Execution unit is responsible for decoding &
execution of program instructions
• BIU is responsible for performing all external bus
operations such as instruction fetching, • Execution unit is composed of general purpose
reading/writing of data to memory and address registers, ALU, control flags & temporary operand
registers
generation
• EU accesses instructions from instruction queue,
• BIU is composed of system bus, segment decodes them, reads operands from
registers, instruction pointer, address generation registers/memory and performs the operation
unit and instruction queue specified by instruction
• System bus include bidirectional data bus, 20 bit • ALU performs arithmetic, logic, shift operations and
address bus and control bus may update control flags
• Instruction queue is a FIFO queue where • EU may also request BIU to perform read/write
program instructions are prefetched in operations on memory or I/O devices
sequential order and fed into the execution unit • If instruction queue is empty, EU waits for the
instruction to be fetched
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Memory Address Space Byte Ordering (“Endianness”)

• Memory in an 8086 microprocessor is byte
Multiple byte data can be
addressable stored in memory in two
• With 20-bit address bus an 8086 µP can address formats
1M ( 220 ) distinct memory locations

Little Endian
• Memory space is organized as consecutive byte •Least significant byte goes to low
locations over the address range 00000H to memory location & most significant
byte goes to high memory location
FFFFFH
• 8086 microprocessor can access data in memory
Big Endian
•Most significant byte goes to low
as a byte (8-bits), word (16-bits) and double word memory location & least significant
(32-bits) byte goes to high memory location

• 16 bit & 32 data occupy multiple byte locations in

8086/8088 based processors
memory access memory in little endian
format
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Byte Ordering (Endianness) : Example Byte Ordering (Endianness) : Example

Example : Example :
Store 16-bit words 1234H and 5678H at Memory Addresses Store 8-bit data 12H, 39H, 85H, 48H at Memory Addresses
0x10000H & 0x10002H in Little Endian & Big Endian Format 0x10000H to 0x10003H in Little Endian & Big Endian Format

Endianness
does not
10003H 78H 10003H 56H 10003H 48H 10003H 48H
matter for
10002H 56H 10002H 78H 10002H 85H 10002H 85H 8-bit data

10001H 34H 10001H 12H 10001H 39H 10001H 39H

10000H 12H 10000H 34H 10000H 12H 10000H 12H

Big Endian Little Endian Big Endian Little Endian

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Memory Alignment Memory Alignment : Word Data

For storage of multi-byte data elements such as • Word data is composed
16-bit, 32-bit , 64-bit data memory address is of two bytes
either aligned or misaligned • For word size data an Misaligned
Word

An aligned address for an n-byte data element aligned memory address
is an address that is multiple of n should be a multiple of 2
– For 2 byte data, aligned address should be multiple of 2 • A word data stored at an
– For 4 byte data, aligned address should be multiple of 4 even address is said to be
– For 8 byte data, aligned address should be multiple of 8 aligned word Aligned
Word

If the address of an n-byte data in memory is not • A word data stored at an
multiple of n it is said to be misaligned/unaligned odd address is said to be

x86 processors can handle both aligned and a misaligned word
misaligned memory addresses

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Memory Alignment : Double Word
Memory Alignment of Data
Data
• Double word data is
Aligned
composed of four bytes DWord
• An aligned double word
is stored at a memory
address that is a
multiple of 4
• If a double word is
stored at an address
that is not a multiple of
4 it is said to be a
misaligned double word

Misaligned
DWord
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