1

CHAPTER 1
MICROPROCESSORS, MICROCONTROLLERS, AND ASSEMBLY LANGUAGE

A microprocessor is a programmable integrated device that has computing and decision-making

capabilities similar to that of the CPU of a computer.

A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device

that reads binary instructions from a storage device called memory, accepts binary data as input and
processes data according to those instructions, and provides results as output.

A microcomputer is a computer that uses a microprocessor as its CPU.

A microcontroller is a devices that has the functionalities of a microprocessor but also has on-chip
memory and i/o devices.

Microprocessors are typically used as CPUs of computers while microcontrollers are used in
embedded devices.

Each microprocessor has a fixed set of instructions in the form of binary patterns called a machine
language.

The binary instructions are given abbreviated names, called mnemonics, which form the assembly
language for a given microprocessor.

Each microprocessor recognizes and processes a group of bits called a word.

Microprocessors are classified according to their word length, viz. 8-bit microprocessors, 16-bit
microprocessors, 32-bit microprocessors, 64-bit microprocessors, etc.

Intel was developing a programmable calculator. The original design needed 12 different chips with
hardwired logic functions. Ted Hoff suggested a general-purpose chip that could perform various
logic functions which could be activated by providing patterns of 0s and 1s. Intel coined the term
microprocessor and in 1971 released the first microprocessor as the Intel 4004.

Gordon Moore, cofounder of Intel, proposed the Moore’s law.

The number of transistors per integrated circuit would double every 18 months.

Evolution: 4004
4040
8008
8080
8085
8086
8088
80186
80188
80286

80386
80486
Pentium

Intel 8080
Intel 8085, Motorola 6800, Zilog Z80

Intel 8085 and Zilog Z80 are upward software compatible with Intel 8080, i.e. their instruction sets
are supersets of the instruction set of Intel 8080.

[Section: 1.1]
 2

CHAPTER 4
8085 MICROPROCESSOR ARCHITECTURE AND MEMORY INTERFACING

Intel 8085 microprocessor –

- Technically 8085A
- 8-bit, general purpose microprocessor
- 8-bit ALU, 8-bit data bus, 16-bit address bus
- Capable of addressing 64 KB memory
- nMOS technology
- Dual in-line package (DIP), 40 pins
- Single +5 V power supply
- Operates at 3 MHz
- 246 instructions, 74 unique
- CISC processor

Intel 8085 pinout –

 3

Address bus –
- A15-A8
Multiplexed address/data bus –
- AD7-AD0
Control and status signals –
- ALE - Address latch enable. A positive going pulse emitted at the beginning of
each operation (machine cycle) denoting that AD7-AD0 are now behaving as
address lines.
- !RD
- !WR
- IO/!M
- S1 and S0 - Status signals.
Machine cycle IO/!M S1 S0
Opcode fetch 0 1 1
Memory read 0 1 0
Memory write 0 0 1
I/O read 1 1 0
I/O write 1 0 1
Interrupt acknowledge 1 1 1
Halt Z 0 0
 4

Power supply and clock frequency –

- VCC - +5 V power supply.
- VSS - Ground.
- X1 and X2 - A crystal or a RC or LC network is connected. The frequency is internally
divided by two.
- CLOCK (OUT) - System clock for other devices.
Externally initiated signals –
- INTR - Interrupt request. General-purpose interrupt.
- !INTA - Interrupt acknowledge.
- RST 5.5, RST 6.5 and RST 7.5 - Restart interrupts. Vectored interrupts that transfer the
program control to specific memory locations.
- TRAP - Non-maskable interrupt.
- HOLD - Denotes that a peripheral, like the DMA controller, is requesting for the data
and address buses.
- HLDA - Hold acknowledge.
- READY - Denotes that a peripheral is ready.
- !RESET IN - The microprocessor is reset with PC cleared to 0 and buses tri-stated.
- RESET OUT - Denotes that the microprocessor is being reset, other devices may follow.
Serial i/o ports –
- SID - Serial input data.
- SOD - Serial output data.

Intel 8085 block diagram –

 5

Flag register –
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
AC - If in an arithmetic operation a carry is generated by the bit D3 and passed onto the bit D4,
then the flag is set. The flag is used only internally for BCD operations and is not accessible
to the programmer.
P - If the result has even number of 1’s, then the flag is set.

Instruction cycle is defined as the time required to complete the execution of one instruction.
1 instruction cycle = 1 to 6 machine cycles.
Machine cycle is defined as the time required to complete one operation of accessing memory, i/o,
or acknowledging an external request.
1 machine cycle = 3 to 6 t-states.
T-state is defined as a subdivision of an operation performed in one clock period.
1 instruction = 4 to 18 t-states.

Exercise. Execution of the instruction MVI A, 32H stored in memory locations 2000-01H.
Solution. 2000H
3EH (opcode), 2001H
32H (operand).

M1: Opcode fetch.

T1: Signal that it is an opcode fetch cycle and place address on the address bus.
T2: Copy opcode from memory and place it on data bus.
T3: Copy opcode to the instruction register.
T4: Decode opcode.
M2: Memory read.
T1: Signal that it is a memory read cycle and place address on the address bus.
T2: Copy data from memory and place it on data bus.
T3: Copy data to the accumulator.
 6

Exercise. Execution of the instruction STA 2065H stored in memory locations 2010-12H.
Solution. 2010H
32H (opcode), 2011H
65H (low-order address), 2012H
20H (high-order
address).
M1: Opcode fetch.
M2: Memory read (low-order address).
M3: Memory read (high-order address).
M4: Memory write.
T1: Signal that it is a memory write cycle and place address on the address bus.
T2: Copy data from the accumulator and place it on data bus.
T3: Copy data to the memory.

To make programs short: minimize bytes.

To make programs fast: minimize t-states.
No correlation between the two.

Memory interfacing –

Use low-order address-lines to specify address.

Use high-order address-lines to generate !CS.
Combine IO/!M and !RD to generate !MEMR.
Combine IO/!M and !WR to generate !MEMW.
 7

[Section: 4.1 – 4.3]

 8

CHAPTER 5
INTERFACING I/O DEVICES

Exercise. Execution of the instruction OUT 01H stored in memory locations 2050-51H.
Solution. 2050H
D3H (opcode), 2051H
01H (operand).

Exercise. Execution of the instruction IN 84H stored in memory locations 2065-66H.

Solution. 2065H
DBH (opcode), 2066H
84H (operand).
 9

In memory-mapped i/o, the i/o devices are assigned and identified by 16-bit addresses.
To transfer data between the microprocessor and the i/o devices, memory-related instructions (LDA,
STA, MOV, etc.) and control signals (!MEMR and !MEMW) are used.
The microprocessor interacts with the i/o device as if it was one the memory locations.

[Section: 5.1 and 5.4]

 10

CHAPTER 6
INTRODUCTION TO 8085 INSTRUCTIONS

In Intel 8085, 1 word = 1 byte

Instructions can be classified as –
- 1-byte instructions e.g. - HLT
- 2-byte instructions e.g. - IN
- 3-byte instructions e.g. - JMP

Addressing modes –
- Implied e.g. - HLT, NOP, CMA
- Immediate e.g. - MVI, ADI, ANI
- Direct e.g. - LDA, STA
- Register e.g. - MOV, ADD, ANA
- Register indirect e.g. - LDAX, STAX, MOV, ADD

R, Rd, Rs: registers

Rp: register pair
M: memory location specified by the HL register pair

Data transfer (copy) instructions –

MOV Rd, Rs 1-byte
MVI R, 8-bit 2-byte
OUT 8-bit 2-byte
IN 8-bit 2-byte
HLT 1-byte The microprocessor stops executing and enters
wait state. The buses are tri-stated. Contents of
the registers are not affected.
NOP 1-byte
The data transfer instructions do not affect the flags.

Exercise. Write a program to send the content of the register B to the output device with port address
FFH and then store the data 10H in the same register.

Arithmetic instructions –
ADD R 1-byte
ADI 8-bit 2-byte
SUB R 1-byte
SUI 8-bit 2-byte
INR R 1-byte
DCR R 1-byte
The arithmetic instructions affect the flag registers. However, INR and DCR do not affect the CY flag.

Exercise. Write a program to add 10H and 20H, increment the value by one, and then decrement the
value by two.

Logic instructions –
ANA R 1-byte
ANI 8-bit 2-byte
ORA R 1-byte
 11

ORI 8-bit 2-byte

XRA R 1-byte
XRI 8-bit 2-byte
CMA 1-byte
The logic instructions actually work bit-wise.
The logic instructions clear the CY flag and affect the other flags. However, CMA does neither clear
the CY flag nor affect the other flags.

Exercise. What is the effect of the instructions XRA A?

Branch (jump) instructions –

JMP 16-bit 3-byte Jump unconditionally. The second byte specifies
the low-order and the third byte specifies the high-
order memory address.
JC 16-bit 3-byte Jump on carry.
JNC 16-bit 3-byte Jump on no carry.
JZ 16-bit 3-byte Jump on zero.
JNZ 16-bit 3-byte Jump on no zero.
JP 16-bit 3-byte Jump on plus.
JM 16-bit 3-byte Jump on minus.
JPE 16-bit 3-byte Jump on even parity (P = 1).
JPO 16-bit 3-byte Jump on odd parity (P = 0).

Exercise. Write a program to input a number using the device with port address FEH and output it
using the device with port address FFH only if the number is (a) equal to 10H and (b) greater than
10H.

[Sections: 6.1 – 6.4]

 12

CHAPTER 7
PROGRAMMING TECHNIQUES WITH ADDITIONAL INSTRUCTIONS

Additional data transfer and 16-bit arithmetic instructions –

LXI Rp, 16-bit 3-byte The second and the third bytes are loaded in the
low-order and the high-order register of the
register pair, respectively. Special case: LXI SP.
MOV R, M 1-byte
LDAX Rp 1-byte Cases: LDAX B and LDAX D.
LDA 16-bit 3-byte The second byte specifies the low-order and the
third byte specifies the high-order memory
address.
MOV M, R 1-byte The memory location is specified by the HL
register pair.
STAX Rp 1-byte Cases: STAX B and STAX D.
STA 16-bit 3-byte The second byte specifies the low-order and the
third byte specifies the high-order memory
address.
MVI M, 8-bit 2-byte
INX Rp 1-byte Special case: INX SP.
DCX Rp 1-byte Special case: DCX SP.

Arithmetic instructions related to memory –

ADD M 1-byte
SUB M 1-byte
INR M 1-byte All flags except the CY flag are affected.
DCR M 1-byte All flags except the CY flag are affected.

Logic instructions to rotate –

RLC 1-byte Rotate accumulator left.
RAL 1-byte Rotate accumulator left through carry.
RRC 1-byte Rotate accumulator right.
RAR 1-byte Rotate accumulator right through carry.
Only the CY flag is affected.

Logic instructions to compare –

CMP R/M 1-byte If A < R/M, then CY = 1 and Z = 0.
If A = R/M, then CY = 0 and Z = 1.
If A > R/M, then CY = 0 and Z = 0.
CPI 8-bit 2-byte
Contents are not affected but the other flags are affected.

Exercise. Find the maximum of three numbers.

Exercise. Calculate the sum of a list of numbers terminated by zero.

Exercise. List the first ten even numbers.

Exercise. Linear search.

 13

Exercise. Find the maximum and minimum in a list of ten numbers.

Exercise. Multiply two numbers by successive additions.

Exercise. Bubble sort.

Exercise. Insertion sort.

[Sections: 7.2 – 7.5]

 14

CHAPTER 8
COUNTERS AND TIME DELAYS

Exercise. Calculate the time delay inserted in a program by the following code.
MVI C, FFH
LOOP: DCR C
JNZ LOOP
Solution. Frequency = 3 MHz.
Instruction T-states Number of times executed Total clock periods
MVI 7 1 7
DCR 4 255 1020
JNZ (jump) 10 254 2540
JNZ (no jump) 7 1 7
Total 3574
Delay = 3574/(3x106) = 1.19 ms.

Exercise. Write a code fragment to insert a delay of 10 ms in a program.

[Section: 8.1]
 15

CHAPTER 9
STACK AND SUBROUTINES

The instruction LXI SP, 3000H will set SP = 3000H.

The data will be stored at the memory locations 2FFFH, 2FFEH, and so on.
PUSH Rp 1-byte The SP is decremented, the content of the high-
order register is pushed, the SP is decremented
again and the content of the low-order register is
pushed. Special case PUSH PSW which pushes the
contents of the accumulator and the flag register.
POP Rp 1-byte
CALL 16-bit 3-byte Saves the content of the PC on the stack.
RET 1-byte
CC 16-bit 3-byte
CNC 16-bit 3-byte
CZ 16-bit 3-byte
CNZ 16-bit 3-byte
CP 16-bit 3-byte
CM 16-bit 3-byte
CPE 16-bit 3-byte
CPO 16-bit 3-byte
RC 1-byte
RNC 1-byte
RZ 1-byte
RNZ 1-byte
RP 1-byte
RM 1-byte
RPE 1-byte
RPO 1-byte

The RST instructions are executed like call instructions. They are typically, but not always, used in
conjunction with interrupts.
RST0 1-byte Equivalent to CALL 0000H.
RST1 1-byte Equivalent to CALL 0008H.
RST2 1-byte Equivalent to CALL 0010H.
RST3 1-byte Equivalent to CALL 0018H.
RST4 1-byte Equivalent to CALL 0020H.
RST5 1-byte Equivalent to CALL 0028H.
RST6 1-byte Equivalent to CALL 0030H.
RST7 1-byte Equivalent to CALL 0038H.

Exercise. Write a subroutine to add three numbers and use it to write a program to add nine
numbers.

Exercise. Write a program to calculate the numbers of Fibonacci series less than hundred using
recursion.

[Sections: 9.1 – 9.3]

 16

CHAPTER 10
CODE CONVERSION, BCD ARITHMETIC, AND 16-BIT DATA OPERATIONS

DAA Decimal-adjust accumulator

1-byte
The content of A is changed from a binary value to two 4-bit BCD digits.
This is the only instruction that uses AC flag (internally).
All flags affected.
If A3-A0 is greater than 9 or if AC is set, then DAA adds 6 to A3-A0.
If A7-A4 is greater than 9 or if CY is set, then DAA adds 6 to A7-A4.
E.g. – 39BCD + 12BCD = 4B + 06 = 51BCD.

LHLD Load HL direct

3-byte
E.g. – LHLD 2000H

SHLD Store HL direct

3-byte
E.g. – SHLD 2000H

XCHG Exchange contents of HL and DE

1-byte

ADC R/M
ACI 8-bit Add with carry
Add operand and CY to A

SBB R/M
SBI 8-bit Subtract with carry
Subtract operand and CY from A

DAD Rp Double register add

Add register pair to HL
Sum in HL
1-byte
CY altered to reflect 16-bit addition, other flags unaffected.
E.g. – DAD B, DAD D, DAD H and DAD SP

XTHL Exchange top of stack with HL

L 
Stack[SP]
H 
Stack[SP+1]
1-byte

SPHL Copy HL into SP

1-byte

PCHL Copy HL into PC

1-byte
 17

CMC Complement carry flag

1-byte

STC Set carry flag

1-byte

Exercise. Write a program to copy a list stored in the memory locations 2001H through 200AH to
memory locations 2051H through 205AH using the XCHG instruction.

Exercise. Write a code fragment to jump to the address stored in the memory locations 2001-02H.

[Sections: 10.5 and 10.7]

 18

CHAPTER 12
INTERRUPTS

Three approaches of performing I/O –

- Polling
- Interrupt-based
- DMA

Interrupt-based I/O is a process of data transfer whereby an external device can inform the
processor that it is ready for communication and it requests attention.
The process is initiated by the external device.
The process is asynchronous, i.e. it can be initiated anytime without reference to the system clock.
The response to an interrupt is controlled by the microprocessor.

Intel 8085 interrupts –

4 maskable and 1 non-maskable
4 vectored and 1 non-vectored

The microprocessor can ignore or delay a maskable interrupt request if it is performing some critical
task.
However, it has to respond to a non-maskable interrupt immediately.

The starting address of the interrupt service routine is implicitly defined in case of a vectored
interrupt.
The starting address has to be provided by external hardware in case of a non-maskable interrupt.

Interrupt Maskable / Non- Vectored / Non- Call location Priority Trigger

maskable vectored
TRAP Non-maskable Vectored 0024H Max (but less Level- and
than HOLD) edge-sensitive
RST 7.5 Maskable Vectored 003CH ↓ Edge-sensitive
RST 6.5 Maskable Vectored 0034H ↓ Level-sensitive
RST 5.5 Maskable Vectored 002CH ↓ Level-sensitive
INTR Maskable Non-vectored Refer to RST 0 Min Level-sensitive
- RST 7
 19

The Intel 8085 interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to
the microprocessor and can be set or reset using software instructions.

If the Interrupt Enable flip-flop is enabled and the INTR pin (pin 10) goes high, then the
microprocessor is interrupted.
This is a maskable interrupt and can be disabled.

EI 1-byte Enable interrupt. Sets the Interrupt Enable flip-flop

and enables the interrupt process. System reset or
an interrupt disables the interrupt process.
DI 1-byte Disable interrupt. Resets the Interrupt Enable flip-
flop and disables the interrupt process. Used in a
program fragment where an interrupt cannot be
tolerated.
The microprocessor checks the INTR line during the execution of each instruction.
If the INTR line is high and the Interrupt Enable flip-flop is set, then the microprocessor completes
the current instruction, disables the flip-flop and send an !INTA signal.
The !INTA signal is used to insert an RST instruction through external hardware.
The service routine should include the EI instruction and end with a return instruction.

An RST instruction can be inserted by providing its opcode the low-order address bus.
For example, opcode of RST0 is C7H.

SIM 1-byte Set interrupt mask. Three functions:

- Set masks for RST 7.5, 6.5 and 5.5 interrupts. The
interrupts are enabled or disabled according to the
content of the accumulator.
- Reset RST 7.5 interrupt without servicing it.
- Perform serial output.

7 6 5 4 3 2 1 0
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
M7.5, M6.5 and M5.5: RST 7.5 mask, RST 6.5 mask and RST 5.5 mask. 0 = available and 1 = masked.
MSE: Mask set enable. 0 = bits 0-2 ignored and 1 = mask is set.
R7.5: Reset RST 7.5. 1 = ignore RST 7.5.
SDE: Serial data enable. 0 = ignore bit 7 and 1 = send bit 7 to serial output data latch.
SOD: Serial output data.

The interrupt process, except TRAP, can be disabled by resetting the Interrupt Enable flip-flop using
one of the follows.
- DI instruction
- System reset
- Recognition of an interrupt request

RST 7.5 is positive-edge sensitive and can be triggered with a short pulse.
The request is stored internally until the microprocessor responds to the request or until it is cleared
by reset or by bit 4 in SIM instruction.

RST 6.5 and 5.5 are level-sensitive.

The triggering levels should be maintained by external hardware until the microprocessor can
respond.
 20

Exercise. Enable all interrupts.

Solution.
EI
MVI A, 08H
SIM

Exercise. Reset the RST 7.5 interrupt.

Solution.
MVI A, 18H
SIM

When one interrupt is being served, other interrupt requests may occur and remain pending.
The RIM instruction is used to detect pending interrupts.

RIM 1-byte Read interrupt mask. Three functions:

- Load the status of the interrupt masks in the
accumulator.
- Identify pending requests.
- Perform serial input.

7 6 5 4 3 2 1 0
SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5
M7.5, M6.5 and M5.5: Interrupt masks. 0 = available and 1 = masked.
IE: Interrupt enable. 0 = disable and 1 = enable.
I7.5, I6.5 and I5.5: Pending interrupts. 0 = not pending and 1 = pending.
SID: Serial input data.

Exercise. The microprocessor is completing an RST 7.5 request. Check if RST 6.5 is pending. If yes, then
enable RST 6.5 else return to the main program.
Solution.
RIM
MOV B, A
ANI 20H ; check is RST 6.5 is pending
JNZ NEXT
EI
RET ; return to main program
NEXT: MOV A, B ; get bit pattern
ANI 0DH ; enables RST 6.5
ORI 08H ; enable mask
SIM
JMP SERV ; jump to RST 6.5 service routine

[Sections: 12.1 and 12.2]

 21

CHAPTER 14
PROGRAMMABLE INTERFACE DEVICES

Seven-segment display –
HP5082/7340

Fairchild 9370 hex decoder and common-anode seven-segment LED

Intel 8155 Multipurpose Programmable Device

Specifically designed to be used with Intel 8085.
40-pin DIP package.

Components –
- 256 bytes R/W static RAM
- I/O ports
- Two 8-bit parallel ports (Port A and Port B)
- One 6-bit parallel port (Port C)
- Timer
- 14-bit down-counter
 22

IO/!M: If high, then ports and timer selected, else memory is selected.

Addresses –
XXXXX000: Control/status register
XXXXX001: Port A
XXXXX010: Port B
XXXXX011: Port C
XXXXX100: Timer LSB
XXXXX101: Timer MSB

Control word –
D7 D6 D5 D4 D3 D2 D1 D0
D1, D0: Port B, Port A. 0 = input, 1 = output.
D3-D2: Port C. 00 = ALT1, 11 = ALT2, 01 = ALT3, 10 = ALT4.
D5, D4: Interrupt enable. Port B, Port A. 0 = disable, 1 = enable.
D7-D6: Timer command. 00 = no effect, 01 = stop, 10 = stop after terminal count, 11 = start.
PC5 PC4 PC3 PC2 PC1 PC0
ALT1 I I I I I I
ALT2 O O O O O O
ALT3 O O O !STBA BFA INTRA
ALT4 !STBB BFB INTRB !STBA BFA INTRA

Exercise. Display the number 1857H using four seven-segment displays connected to ports A and B.
Assume that Intel 8155 has an address 00100XXX.
Solution.
MVI A, 03H
OUT 20H
MVI A, 18H
OUT 21H
MVI A, 57H
 23

OUT 22H
HLT

Timer –
MSB
M2 M1 T13 T12 T11 T10 T9 T8
LSB
T7 T6 T5 T4 T3 T2 T1 T0
Mode 0: !TIMER OUT = 1 for first N/2, = 0 for last N/2.
Mode 1: Continuous version of Mode 0. (Square wave)
Mode 2: !TIMER OUT = 1 for first N-1, = 0 for last 1.
Mode 3: Continuous version of Mode 2.

Exercise. Design a square-wave generator with a pulse width of 100 µs.

Solution.
Pulse width = 100 µs
Wave period = 200 µs
Count = wave period / clock period = wave period x frequency = 200x10-6 x 3x106 = 600
MVI A, 58H
OUT 24H
MVI A, 42H
OUT 25H
MVI A, C3H
OUT 20H
HLT

I/o using handshaking –

!STB: Strobe (Input from peripheral)
BF: Buffer full (Output to peripheral)
INTR (Output to 8085)
Input
 24

Output

Status word –
X TI INTEB BFB INTRB INTEA BFA INTRA
TI: Set on reaching terminal count. Reset on reading status word and by hardware reset.

I/o using status checking –

Interrupts are not used

Intel 8279 Programmable Keyboard/Display Interface

40-pin DIP package.
 25

Keyboard section
Can be connected to 64-contact key matrix with an interrupt generated for each key press.
RL0-RL7: Return lines. Connected to eight columns of keyboard.
The keys are automatically debounced.
The keyboard can operate in two modes –
- Two-key lockout mode: If two keys are pressed in quick succession, then only the first is
recognized.
- N-key rollover mode: Codes of simultaneously pressed keys are stored in buffer; it can be
specified that no other key is recognized till one key remains pressed.
8 byte FIFO RAM: Store eight keyboard entries.

Scan section
SL0-SL3: Scan lines. Decoded in 16 lines using a 4-to-16 decoder.
Those lines can be connected to rows of keyboard or drivers of displays.

Display section
Can be connected to a 16-character display interface with devices like LEDs.
The display can be set up in either left-entry or right-entry format.
OUT A0 - OUT A3 and OUT B0 - OUT B3: Can be used as together or separately.
!BD: Blank display.
16 byte R/W RAM.

Interface section
A0 is low for data, high for control or status.
IRQ goes high when there is data in FIFO RAM.

Port addresses
XXXXXXX0: Data port
XXXXXXX1: Command/status port

Control word –
- Keyboard/display mode set: 000DDKKK
DD = 00 for 8 character display – left entry
KKK = 000 for encoded scan keyboard – 2-key lockout
- Program clock: 001PPPPP
The external clock signal is divided by PPPPP, 2 < PPPPP < 31.
- Read FIFO RAM: 010[AI]XAAA
AI = autoincrement mode, AAA = address.
- Read Display RAM: 011[AI]AAAA
- Write Display RAM: 100[AI]AAAA

[Sections: 14.2 and 14.3]

 26

CHAPTER 15
GENERAL PURPOSE PROGRAMMABLE PERIPHERAL DEVICES

Intel 8255A Programmable Peripheral Interface

Widely used, programmable, parallel i/o interface.
Supports different modes of i/o – simple to interrupt-driven.
40 pin DIP.
Three 8-bit ports – A, B and C.
Port C = Port CU + Port CL.

Modes –
- Bit Set/Reset (BSR) mode: set or reset bits in port C
- I/O mode –
- Mode 0: all ports function as simple i/o ports
- Mode 1: ports A and B use pits of port C for handshake
- Mode 2: port A is used as a bidirectional port using pits of port C and port B is used
in mode 0 or mode 1
 27

Port addresses –
A1A0 = 00: Port A
A1A0 = 01: Port B
A1A0 = 10: Port C
A1A0 = 11: Control register or status register

Mode 0 –
Control word: D7 D6 D5 D4 D3 D2 D1 D0
D7: 0 = BSR mode, 1 = I/O mode
D6D5: Port A. 00 = mode 0, 01 = mode 1, 1x = mode 2
D4: Port A. 0 = output, 1 = input
D3: Port CU. 0 = output, 1 = input
D2: Port B. 0 = mode 0, 1 – mode 1
D1: Port B. 0 = output, 1 = input
D0: Port CL. 0 = output, 1 = input

Exercise. Write a program to copy from ports B and CL to ports A and CU, respectively.
Solution.
MVI A, 83H
STA 8003H
LDA 8001H
STA 8000H
LDA 8002H
ANI 0FH
RLC
RLC
RLC
RLC
STA 8002H
HLT

BSR Mode –
Control word: D7 X X X D3 D 2 D1 D0
D7: 0 = BSR mode
D3D2D1: Port C. 000 = bit 0, 001 = bit 2, … 111 = bit 7
D0: 0 = reset, 1 = set

Exercise. Write a program to set bits 0 and 2 and reset bits 1 and 3 of Port C.

Mode 1 –
Input mode Output mode
PC4  !STBA PC7
!OBFA
PC5
IBFA PC6  ACKA
PC3
INTRA PC3
INTRA
PC2  !STBB PC1
!OBFB
PC1
IBFB PC2  ACKB
PC0
INTRB PC0
INTRB
PC6,7 
I/O PC4,5 
I/O
Status word: Status word:
X X IBFA INTEA INTRA IBFB INTEB INTRB !OBFA INTEA X X INTRA INTEB !OBFB INTRB
 28

Exercise. Write a program to accept inputs from a keyboard connected to port A and send outputs to
the printer connected to port B using handshaking.

Mode 2 –
Bidirectional data transfer.
PC3
INTRA
PC7
!OBFA
PC6  !ACKA
PC4  !STBA
PC5
IBFA
PC0-2 
I/O

Intel 8254 Programmable Interval Timer

Programmable interval timer/counter is functionally equivalent to software designed timers and
counters.
Applications: real-time clock, event counter, square wave generator, complex waveform generator,
etc.
Contains three independent 16-bit counters.
Count either in binary or in BCD.
Interrupt after counting or read value.
Can operate in six modes.
Upgraded version of Intel 8253.
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Port addresses –
A1A0 = 00: Counter 0
A1A0 = 01: Counter 1
A1A0 = 10: Counter 2
A1A0 = 11: Control register

Control word: SC1 SC0 RW1 RW0 M2 M1 M0 BCD

SC1SC0: Select counter. 00 = counter 0, 01 = counter 1, 10 = counter 2, 11 = read back command.
Read back: read count and status of counter.
RW1RW0: 00 = Latch on r/w, 01 = r/w lsb, 10 = r/w msb, 11 = r/w lsb and then msb.
M2M1M0: Mode. 000 = mode 0, 001 = mode 1, X10 = mode 2, X11 = mode 3, 100 = mode 4, 101 =
mode 5.
BCD: 0 = binary, 1 = BCD.

Mode 0: Interrupt on terminal count. Initially OUT is low. A count is loaded and decremented every
cycle. When count reaches 0, OUT goes high. OUT remains high till a new count or control
word is loaded. Counting can be suspended by disabling Gate and resumed on enabling it.
Mode 1: Hardware re-triggerable one-shot. OUT is initially high. When Gate is triggered, OUT goes
low. At the end of the count, OUT goes high.
Mode 2. Rate generator. Used to generate a pulse equal to the clock period at a given interval.
Then a count is loaded. OUT stays high till count reaches 1 and then goes low for one clock
period. The count is reloaded automatically and pulse is generated continuously. A count =
1 is illegal.
Mode 3. Square-wave generator. When a count is loaded, OUT goes high. Count is decremented by
2 in every clock cycle. When count reaches zero, OUT goes low. The count is reloaded
automatically. Frequency of square wave is equal to clock frequency divided by count. If
count is odd, pulse stays high for the extra clock cycle.
Mode 4. Software-triggered strobe. OUT is initially high. It goes low for one clock period at the end
of the count. The count has to be reloaded.
Mode 5. Hardware-triggered strobe. Same as mode 4 except triggered by rising pulse at gate.

Exercise. Write a subroutine to count 50000 supporting reading count on fly.

Solution.
MVI A, B0H
OUT 83H
MVI A, 50H
OUT 82H
MVI A, C3H
OUT 82H
LOOP: MVI A, 80H
OUT 83H
IN 82H
MOV B, A
IN 82H
ORA D
JNZ READ
RET

Exercise. Write code to generate a pulse every 50 µs. Assume frequency of 8254 be 2 MHz.
Solution. Count = 50 x 10-6 x 2 x 106 = 100 = 64H.
MVI A, 14H
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OUT 83H
MVI A, 64H
OUT 80H

Exercise. Write code to generate 1 KHz square-wave. Assume frequency of 8254 be 2 MHz.
Solution. Count = (2 x 106) / (1 x 103) = 2000 = 07D0H.
MVI A, 76H
OUT 83H
MVI A, D0H
OUT 81H
MVIA, 07H
OUT 81H

Intel 8259A Programmable Interrupt Controller

Works with Intel 8085, 8086 and 8088.
28-pin DIP.
Manages eight interrupts, i.e. equivalent to 8 INTR pins.
Vectors an interrupt anywhere in the memory.
However, distance between two such interrupt service routines should be either 4 or 8 bytes.
Uses eight priority levels to manage the interrupts.
The interrupts can be masked individually.
The status can be read for pending, in-service and masked interrupts.
Can be programmed to detect edge- and level-triggered interrupts.
Cascaded 8259As can be used to identify up to 64 interrupts.
 31

Two types of control words –

- Initialization Command Words – specify vector addresses
- Operational Command Words

Working –
The opcode of the CALL instruction is written on the lower-order data bus.
The microprocessor decodes the opcode and understands that it is a CALL instruction.
The address is then placed on the data bus.
The program control is transferred to the given address.

Intel 8237 Programmable DMA Controller

40-pin DIP.
Has four independent channels each capable of transferring 64KB.
Connected to a microprocessor and a peripheral device like a disk.
Channels are named CH0 – CH3.
Each channel has two associated 16-bit registers for storing the starting address and number of
bytes to be copied.

DREQ0-DREQ3: DMA request

DACK0-DACK3: DMA acknowledge
HRQ and HLDA: Hold request and Hold acknowledge
!IOR, !IOW, !MEMR, !MEMW
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The 8237 programmable DMA controller can operate in two modes –

- slave mode: treated as a peripheral by the microprocessor
- master mode: keeps checking for DMA requests and controls data transfer

[Sections: 15.1 and 15.4 – 15.6]

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CHAPTER 16
SERIAL I/O AND DATA COMMUNICATION

Intel 8085 serial i/o –

- Pins: SID (equivalent to an 1-bit input port) and SOD (equivalent to an 1-bit output port)
- Instructions: RIM (equivalent to 1-bit IN) and SIM (equivalent to 1-bit conditional OUT)

Exercise. Input an ASCII character through the serial input port. If the character is a lower case letter,
then convert it to higher case and send it to the serial output port. Enter a delay between reading or
writing two consecutive bits.

Intel 8251A USART

USART: Universal Synchronous/Asynchronous Receiver/Transmitter.
Acts as a serial i/o port to interface with slow peripherals.
28-pin DIP package.
 34

!CS: Chip select

C/!D: Control or data
!WR: Write
!RD: Read
RESET: Reset
CLK: System clock
D7-D0: Bidirectional data bus
TxD: Transmit data
RxD: Receive data

Control register (16-bit)

- mode word (8-bit) + command word (8-bit)
- use OUT instruction first for mode word and then for command word
Status register (8-bit)
Data buffer (8-bit)

!CS C/!D !RD !WR

0 1 1 0 Write instruction in control register
0 1 0 1 Read status from status register
0 0 1 0 Write data in data buffer
0 0 0 1 Read data from data buffer

Sample interfacing –
Intel 8085 Intel 8051
D0-D7 ↔ D0-D7
A0 ↔ C/!D
A1-A7 ↔ !CS
!IOW ↔ !WR
!IOR ↔ !RD
!IOW ↔ !WR
RESET OUT ↔ RESET
CLK (OUT) ↔ CLK

Port address of data buffer = FEH

Port address of control register and status register = FFH

Exercise. Write a program to transmit a message using Intel 8251. The number of bytes in the
message is stored in 2070H and the message is stored in memory locations starting at 2071H.
Solution.
LXI H, 2070H
MVI A, CAH ; initialize 8251
OUT FFH
MVI A, 11H
OUT FFH
LOOP: IN FFH ; check if transmitter ready
ANI 01H
JZ LOOP
INX H
MOV A, M
OUT FEH
DCR C
 35

JNZ LOOP
HLT

[Sections: 16.3 and 16.4]

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Level of details for interfacing chips:

Theory and programming: 8155, 8255, 8254.

Theory only and no programming: 8279, 8259, 8237, 8251.

[Full version]
[Last revised on 31 March 2016]