Ic PDF

24AA512/24LC512/24FC512
512K I2C™ Serial EEPROM

Device Selection Table Description:
Part VCC Max. Clock Temp. The Microchip Technology Inc. 24AA512/24LC512/
Number Range Frequency Ranges 24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
24AA512 1.7-5.5V 400 kHz(1) I Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
24LC512 2.5-5.5V 400 kHz I, E been developed for advanced, low-power applications
24FC512 1.7-5.5V 1 MHz(2) I such as personal communications and data acquisi-
Note 1: 100 kHz for VCC < 2.5V tion. This device also has a page write capability of up
2: 400 kHz for VCC < 2.5V to 128 bytes of data. This device is capable of both
random and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
Features: the same bus, for up to 4 Mbit address space. This
• Single Supply with Operation down to 1.7V for device is available in the standard 8-pin plastic DIP,
24AA512 and 24FC512 Devices, 2.5V for SOIJ, SOIC, TSSOP, DFN, and 14-lead TSSOP
24LC512 Devices packages. The 24AA512 is also available in the 8-lead
Chip Scale package.
• Low-Power CMOS Technology:
- Active current 400 uA, typical Block Diagram
- Standby current 100 nA, typical A0 A1 A2 WP HV Generator
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable for up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression I/O Memory EEPROM
• Output Slope Control to Eliminate Ground Bounce Control Control XDEC Array
Logic Logic
• 100 kHz and 400 kHz Clock Compatibility Page Latches
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle SCL
I/O
• 128-Byte Page Write Buffer YDEC
• Hardware Write-Protect
SDA
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles VCC
VSS Sense Amp.
• Data Retention > 200 years R/W Control
• Packages Include 8-lead PDIP, SOIJ, SOIC,
TSSOP, DFN, Chip Scale and 14-lead TSSOP
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E):-40C to +125C
Package Type
PDIP/SOIJ/SOIC/TSSOP TSSOP DFN CS (Chip Scale)(1)
A0 1 8 VCC A0 1 14 VCC VCC A1 A0

A0 1 8 VCC
A1 2 13 WP 1 2 3
24XX512
2
24XX512
A1 2 7 WP NC 3 12 NC A1 7 WP WP 4 5 A2
24XX512
NC 4 11 NC A2 3 6 SCL 6 7 8
A2 3 6 SCL
NC 5 10
NC SDA SCL VSS
6 9 VSS 4 5 SDA
VSS 4 5 SDA A2 SCL
VSS 7 8 SDA
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
Note 1: Available in I-temp, “AA” only.

* 24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices.
 2010 Microchip Technology Inc. DS21754M-page 1

24AA512/24LC512/24FC512
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics:
DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
Param.
Sym. Characteristic Min. Max. Units Conditions
No.
D1 — A0, A1, A2, SCL, SDA — — — —
and WP pins:
D2 VIH High-level input voltage 0.7 VCC — V —
D3 VIL Low-level input voltage — 0.3 VCC V VCC  2.5V
0.2 VCC V VCC < 2.5V
D4 VHYS Hysteresis of Schmitt 0.05 VCC — V VCC  2.5V (Note)
Trigger inputs
(SDA, SCL pins)
D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D6 ILI Input leakage current — ±1 A VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7 ILO Output leakage current — ±1 A VOUT = VSS or VCC
D8 CIN, Pin capacitance — 10 pF VCC = 5.0V (Note)
COUT (all inputs/outputs) TA = 25°C, FCLK = 1 MHz
D9 ICC Read Operating current — 400 A VCC = 5.5V, SCL = 400 kHz
ICC Write — 5 mA VCC = 5.5V
D10 ICCS Standby current — 1 A TA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
— 5 A TA = -40°C to +125°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
DS21754M-page 2  2010 Microchip Technology Inc.

24AA512/24LC512/24FC512
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No.
1 FCLK Clock frequency — 100 kHz 1.7V  VCC  2.5V
— 400 2.5V  VCC  5.5V
— 400 1.7V  VCC  2.5V 24FC512
— 1000 2.5V  VCC  5.5V 24FC512
2 THIGH Clock high time 4000 — ns 1.7V  VCC  2.5V
600 — 2.5V  VCC  5.5V
600 — 1.7V  VCC  2.5V 24FC512
500 — 2.5V  VCC  5.5V 24FC512
3 TLOW Clock low time 4700 — ns 1.7V  VCC  2.5V
1300 — 2.5V  VCC  5.5V
1300 — 1.7V  VCC  2.5V 24FC512
500 — 2.5V  VCC  5.5V 24FC512
4 TR SDA and SCL rise time (Note 1) — 1000 ns 1.7V  VCC< 2.5V
— 300 2.5V  VCC  5.5V
— 300 1.7V  VCC  5.5V 24FC512
5 TF SDA and SCL fall time (Note 1) — 300 ns All except, 24FC512
— 100 1.7V  VCC  5.5V 24FC512
6 THD:STA Start condition hold time 4000 — ns 1.7V  VCC  2.5V
600 — 2.5V  VCC  5.5V
600 — 1.7V  VCC  2.5V 24FC512
250 — 2.5V  VCC  5.5V 24FC512
7 TSU:STA Start condition setup time 4700 — ns 1.7V  VCC  2.5V
600 — 2.5V  VCC  5.5V
600 — 1.7V  VCC  2.5V 24FC512
250 — 2.5V  VCC  5.5V 24FC512
8 THD:DAT Data input hold time 0 — ns (Note 2)
9 TSU:DAT Data input setup time 250 — ns 1.7V  VCC  2.5V
100 — 2.5V  VCC  5.5V
100 — 1.7V  VCC  5.5V 24FC512
10 TSU:STO Stop condition setup time 4000 — ns 1.7V  VCC  2.5V
600 — 2.5V  VCC  5.5V
600 — 1.7V  VCC  2.5V 24FC512
250 — 2.5V  VCC  5.5V 24FC512
11 TSU:WP WP setup time 4000 — ns 1.7V  VCC  2.5V
600 — 2.5V  VCC  5.5V
600 — 1.7V  VCC  5.5V 24FC512
12 THD:WP WP hold time 4700 — ns 1.7V  VCC  2.5V
1300 — 2.5V  VCC  5.5V
1300 — 1.7V  VCC  5.5V 24FC512
13 TAA Output valid from clock (Note 2) — 3500 ns 1.7V  VCC  2.5V
— 900 2.5V  VCC  5.5V
— 900 1.7V  VCC  2.5V 24FC512
— 400 2.5V  VCC  5.5V 24FC512
14 TBUF Bus free time: Time the bus 4700 — ns 1.7V  VCC  2.5V
must be free before a new trans- 1300 — 2.5V  VCC  5.5V
mission can start 1300 — 1.7V  VCC  2.5V 24FC512
500 — 2.5V  VCC  5.5V 24FC512
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

24AA512/24LC512/24FC512
AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Param.
No.
16 TSP Input filter spike suppression — 50 ns All except, 24FC512 (Notes 1 and 3)
(SDA and SCL pins)
17 TWC Write cycle time (byte or page) — 5 ms —
18 — Endurance 1,000,000 — cycles Page Mode, 25°C, VCC = 5.5V
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

24AA512/24LC512/24FC512
FIGURE 1-1: BUS TIMING DATA
5 4
2 D4
SCL 7
3 8 9 10
SDA 6
IN
16
13 14
SDA
OUT
(protected)
WP 11 12
(unprotected)

24AA512/24LC512/24FC512
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE

14-lead
Name PDIP SOIC SOIJ TSSOP DFN CS Function
TSSOP
A0 1 1 1 1 1 1 3 User Configured Chip Select
(NC) — — — — 3, 4, 5 — — Not Connected
VSS 4 4 4 4 7 4 8 Ground
SDA 5 5 5 5 8 5 6 Serial Data
SCL 6 6 6 6 9 6 7 Serial Clock
(NC) — — — — 10, 11, 12 — — Not Connected
WP 7 7 7 7 13 7 4 Write-Protect Input
VCC 8 8 8 8 14 8 1 +1.7V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+1.7V to 5.5V (24FC512)
2.1 A0, A1 and A2 Chip Address 2.3 Serial Clock (SCL)

Inputs This input is used to synchronize the data transfer from
The A0, A1 and A2 inputs are used by the 24XX512 for and to the device.
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the 2.4 Write-Protect (WP)
slave address. The chip is selected if the compare is
true. This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
Up to eight devices may be connected to the same bus write operations are inhibited but read operations are
by using different Chip Select bit combinations. These not affected.
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1 3.0 FUNCTIONAL DESCRIPTION
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a The 24XX512 supports a bidirectional 2-wire bus and
microcontroller or other programmable logic device, data transmission protocol. A device that sends data
the chip address pins must be driven to logic ‘0’ or logic onto the bus is defined as a transmitter and a device
‘1’ before normal device operation can proceed. receiving data as a receiver. The bus must be
controlled by a master device which generates the
2.2 Serial Data (SDA) Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
This is a bidirectional pin used to transfer addresses 24XX512 works as a slave. Both master and slave
and data into and data out of the device. It is an open- can operate as a transmitter or receiver, but the
drain terminal, therefore, the SDA bus requires a pull- master device determines which mode is activated.
up resistor to VCC (typical 10 k for 100 kHz, 2 kfor
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

24AA512/24LC512/24FC512
4.0 BUS CHARACTERISTICS 4.5 Acknowledge
The following bus protocol has been defined: Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
• Data transfer may be initiated only when the bus
each byte. The master device must generate an extra
is not busy.
clock pulse which is associated with this Acknowledge
• During data transfer, the data line must remain bit. See Figure 4-2 for acknowledge timing.
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be Note: The 24XX512 does not generate any
interpreted as a Start or Stop condition. Acknowledge bits if an internal programming
cycle is in progress.
Accordingly, the following bus conditions have been
defined (Figure 4-1). A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
4.1 Bus Not Busy (A) that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
Both data and clock lines remain high. and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
4.2 Start Data Transfer (B) by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
A high-to-low transition of the SDA line while the clock slave (24XX512) will leave the data line high to enable
(SCL) is high determines a Start condition. All the master to generate the Stop condition.
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.

24AA512/24LC512/24FC512
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (C) (A)
SCL
SDA
Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change
FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
SDA Data from transmitter Data from transmitter
Transmitter must release the SDA line at this point Receiver must release the SDA line
allowing the Receiver to pull the SDA line low to at this point so the Transmitter can
acknowledge the previous eight bits of data. continue sending data.

24AA512/24LC512/24FC512
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE FORMAT
A control byte is the first byte received following the Read/Write Bit
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the Chip Select
24XX512 this is set as ‘1010’ binary for read and write Control Code Bits
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1 and A0). The Chip Select S 1 0 1 0 A2 A1 A0 R/W ACK
bits allow the use of up to eight 24XX512 devices on
the same bus and are used to select which device is
Slave Address
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2, Start Bit Acknowledge Bit
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address. 5.1 Contiguous Addressing Across
The last bit of the control byte defines the operation to Multiple Devices
be performed. When set to a one a read operation is
selected and when set to a zero a write operation is The Chip Select bits A2, A1 and A0 can be used to
selected. The next two bytes received define the expand the contiguous address space for up to 4 Mbit
address of the first data byte (Figure 5-2). Because all by adding up to eight 24XX512 devices on the same
A15…A0 are used, there are no upper address bits that bus. In this case, software can use A0 of the control
are “don’t care”. The upper address bits are transferred byte as address bit A16; A1 as address bit A17; and A2
first, followed by the Less Significant bits. as address bit A18. It is not possible to sequentially
read across device boundaries.
Following the Start condition, the 24XX512 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX512 will select a read or
write operation.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte Address High Byte Address Low Byte
A A A A A A A A A A A A A
1 0 1 0 1 0 R/W • • • • • •
2 15 14 13 12 11 10 9 8 7 0
Control Chip
Code Select
Bits

24AA512/24LC512/24FC512
6.0 WRITE OPERATIONS 6.2 Page Write
The write control byte, word address and the first data
6.1 Byte Write byte are transmitted to the 24XX512 in the same way
Following the Start condition from the master, the as in a byte write. But instead of generating a Stop
control code (four bits), the Chip Select (three bits) and condition, the master transmits up to 127 additional
the R/W bit (which is a logic low) are clocked onto the bytes, which are temporarily stored in the on-chip page
bus by the master transmitter. This indicates to the buffer and will be written into memory after the master
addressed slave receiver that the address high byte will has transmitted a Stop condition. After receipt of each
follow after it has generated an Acknowledge bit during word, the seven lower Address Pointer bits are inter-
the ninth clock cycle. Therefore, the next byte nally incremented by one. If the master should transmit
transmitted by the master is the high-order byte of the more than 128 bytes prior to generating the Stop con-
word address and will be written into the Address dition, the address counter will roll over and the previ-
Pointer of the 24XX512. The next byte is the Least ously received data will be overwritten. As with the byte
Significant Address Byte. After receiving another write operation, once the Stop condition is received, an
Acknowledge signal from the 24XX512, the master internal write cycle will begin (Figure 6-2). If an attempt
device will transmit the data word to be written into the is made to write to the array with the WP pin held high,
addressed memory location. The 24XX512 acknowl- the device will acknowledge the command, but no write
edges again and the master generates a Stop cycle will occur, no data will be written and the device
condition. This initiates the internal write cycle and will immediately accept a new command.
during this time, the 24XX512 will not generate
Acknowledge signals (Figure 6-1). If an attempt is 6.3 Write Protection
made to write to the array with the WP pin held high, the
The WP pin allows the user to write-protect the entire
device will acknowledge the command, but no write
array (0000-FFFF) when the pin is tied to VCC. If tied to
cycle will occur, no data will be written and the device
VSS the write protection is disabled. The WP pin is
will immediately accept a new command. After a byte
sampled at the Stop bit for every Write command
Write command, the internal address counter will point
(Figure 1-1). Toggling the WP pin after the Stop bit will
to the address location following the one that was just
have no effect on the execution of the write cycle.
written.
Note: When doing a write of less than 128 bytes Note: Page write operations are limited to writing
the data in the rest of the page is refreshed bytes within a single physical page,
along with the data bytes being written. regardless of the number of bytes
This will force the entire page to endure a actually being written. Physical page
write cycle, for this reason endurance is boundaries start at addresses that are
specified per page. integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

24AA512/24LC512/24FC512
FIGURE 6-1: BYTE WRITE
S
Bus Activity T S
Master Control Address Address
A T
R Byte High Byte Low Byte Data O
T P
SDA Line S1 01 0A AA
2 10 0 P
Bus Activity A A A A
C C C C
K K K K
FIGURE 6-2: PAGE WRITE

S
T S
Bus Activity A Control Address Address T
Master R Byte High Byte Low Byte Data Byte 0 Data Byte 127 O
T P
SDA Line AAA P
S101 02 1 00
A A A A A
Bus Activity C C C C C
K K K K K

24AA512/24LC512/24FC512
7.0 ACKNOWLEDGE POLLING FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write Send
command has been issued from the master, the device Write Command
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte Send Stop
for a Write command (R/W = 0). If the device is still Condition to
busy with the write cycle, then no ACK will be returned. Initiate Write Cycle
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See Send Start
Figure 7-1 for flow diagram.
Send Control Byte

with R/W = 0
Did Device No
Acknowledge
(ACK = 0)?
Yes
Next
Operation

24AA512/24LC512/24FC512
8.0 READ OPERATION 8.3 Sequential Read
Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a
operations with the exception that the R/W bit of the random read except that after the 24XX512 transmits
control byte is set to ‘1’. There are three basic types of the first data byte, the master issues an acknowledge
read operations: current address read, random read as opposed to the Stop condition used in a random
and sequential read. read. This acknowledge directs the 24XX512 to
transmit the next sequentially addressed 8-bit word
8.1 Current Address Read (Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
The 24XX512 contains an address counter that main- but will generate a Stop condition. To provide
tains the address of the last word accessed, internally sequential reads, the 24XX512 contains an internal
incremented by ‘1’. Therefore, if the previous read Address Pointer which is incremented by one at the
access was to address ‘n’ (n is any legal address), the completion of each operation. This Address Pointer
next current address read operation would access data allows the entire memory contents to be serially read
from address n + 1. during one operation. The internal Address Pointer will
Upon receipt of the control byte with R/W bit set to ‘1’, automatically roll over from address FFFF to address
the 24XX512 issues an acknowledge and transmits the 0000 if the master acknowledges the byte received
8-bit data word. The master will not acknowledge the from the array address FFFF.
transfer but does generate a Stop condition and the
24XX512 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS

READ
S
T S
Bus Activity A Control Data T
Master R Byte Byte O
T P
SDA Line S 1 0 1 0 A AA 1 P
2 1 0
A N
Bus Activity C O
K
A
C
K
8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX512 as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The 24XX512 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition which causes the 24XX512 to discontinue
transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.

24AA512/24LC512/24FC512
FIGURE 8-2: RANDOM READ
S S
Bus Activity T T S
Master A Control Address Address A Control Data T
R Byte High Byte Low Byte R Byte Byte O
T T P
SDA Line S1 01 0 AAA0 S 1 0 1 0 A A A1 P
2 1 0 2 1 0
A A A A N
Bus Activity C C C C O
K K K K A
x = “don’t care” bit C
K
FIGURE 8-3: SEQUENTIAL READ

Control S
Bus Activity T
Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x)
Master O
P
SDA Line P
A A A A N
C C C C O
Bus Activity K K K K A
C
K

24AA512/24LC512/24FC512
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
8-Lead PDIP (300 mil) Example:
XXXXXXXX 24AA512
T/XXXNNN I/P e3 017
YYWW 0510
8-Lead SOIJ (5.28 mm) Example:
XXXXXXXX 24LC512
T/XXXXXX I/SM e3
YYWWNNN 0510017
8-Lead DFN-S Example:
XXXXXXX 24LC512
T/XXXXX I/MF e3
YYWW 0510
NNN 017
Legend: XX...X Customer-specific information*

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
T Temperature
Blank Commercial
I Industrial
E Extended
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

24AA512/24LC512/24FC512
Package Marking Information (Continued)
8-Lead SOIC (3.90 mm) Example:
XXXXXXXT 24LC512I
XXXXYYWW SNMe3 0510
NNN 017
8-Lead TSSOP Example
XXXX 4LE
TYWW I510
NNN 017
14-Lead TSSOP Example
XXXXXXXT 4L512I
YYWW 0510
NNN 017
8-Lead Chip Scale Example:
XXXXXXX 24AA512
YYWWNNN 0810017
First Line Marking Codes
Part No. 8- Lead TSSOP Package Codes

24AA512 4AE
24LC512 4LE
24FC512 4FE

24AA512/24LC512/24FC512
/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
NOTE 1
E1
1 2 3
D
E
A A2
A1 L
c
e
b1 eB
b
8QLWV ,1&+(6
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
7RSWR6HDWLQJ3ODQH $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
%DVHWR6HDWLQJ3ODQH $ ± ±
6KRXOGHUWR6KRXOGHU:LGWK (
0ROGHG3DFNDJH:LGWK (
2YHUDOO/HQJWK '
7LSWR6HDWLQJ3ODQH /
/HDG7KLFNQHVV F
8SSHU/HDG:LGWK E
/RZHU/HDG:LGWK E
2YHUDOO5RZ6SDFLQJ H% ± ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKWKHKDWFKHGDUHD
6LJQLILFDQW&KDUDFWHULVWLF
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

24AA512/24LC512/24FC512
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
e
N
E1
NOTE 1
1 2 3
h α
b
h
c
A A2 φ
A1 L
L1 β
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $ ± ±
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK ( %6&
2YHUDOO/HQJWK ' %6&
&KDPIHURSWLRQDO K ±
)RRW/HQJWK / ±
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
0ROG'UDIW$QJOH7RS ±
0ROG'UDIW$QJOH%RWWRP ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

24AA512/24LC512/24FC512
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@

24AA512/24LC512/24FC512
/HDG3ODVWLF6PDOO2XWOLQH60±0HGLXPPP%RG\>62,-@
D
N
E1
1 2
e
b
c
A2 φ
A
β
A1 L
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ±
0ROGHG3DFNDJH7KLFNQHVV $ ±
6WDQGRII $ ±
2YHUDOO:LGWK ( ±
0ROGHG3DFNDJH:LGWK ( ±
2YHUDOO/HQJWK ' ±
)RRW/HQJWK / ±
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
0ROG'UDIW$QJOH7RS ± ±
0ROG'UDIW$QJOH%RWWRP ± ±
1RWHV
62,--(,7$(,$-6WDQGDUGIRUPHUO\FDOOHG62,&

24AA512/24LC512/24FC512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

24AA512/24LC512/24FC512
/HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67±PP%RG\>76623@
E1
NOTE 1
1 2
b
e
c
A A2 φ
A1 L1 L
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
1RWHV

24AA512/24LC512/24FC512
/HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67±PP%RG\>76623@
E
E1
NOTE 1
1 2
e
b
c φ
A A2
A1 L1 L
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
1RWHV

24AA512/24LC512/24FC512
/HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0)±[PP%RG\>')16@
D e
L
b
N N
E E2
EXPOSED PAD
NOTE 1 1 NOTE 1
1 2 2
D2
TOP VIEW BOTTOM VIEW
A3 A1
NOTE 2
8QLWV 0,//,0(7(56
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $
6WDQGRII $
&RQWDFW7KLFNQHVV $ 5()
2YHUDOO/HQJWK ' %6&
2YHUDOO:LGWK ( %6&
([SRVHG3DG/HQJWK '
([SRVHG3DG:LGWK (
&RQWDFW:LGWK E
&RQWDFW/HQJWK /
&RQWDFWWR([SRVHG3DG . ± ±
1RWHV
3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV
3DFNDJHLVVDZVLQJXODWHG

24AA512/24LC512/24FC512

24AA512/24LC512/24FC512

24AA512/24LC512/24FC512

24AA512/24LC512/24FC512

24AA512/24LC512/24FC512
APPENDIX A: REVISION HISTORY
Revision D
Correction to Section 1.0, Electrical Characteristics.
Revision E
Correction to Section 1.0., Ambient Temperature
Correction to Section 6.2, Page Write
Revision F
Add E3 (Pb-free) to marking examples.
Updated Marking Legend and On-line Support.
Revision G
Revised Sections 2.1, 2.4 and 6.3.
Revision H
Revised Features section; Revised 1.8V voltage to
1.7V; Replaced Package Drawings; Revised Product
ID System; Removed 14 Lead TSSOP.
Revision J
Revised Table 1-2, AC Characteristics; Updated
Packaging.
Revision K (06/2009)
Removed CMOS from title; Revised Table 1-2, Para.
18; Added SOIC and TSSOP packaging; Updated Pin
Descriptions; Updated Product ID.
Revision L (12/2009)
Added note to Section 6.1.
Revision M (03/2010)
Added 8-Lead Chip Scale package.

24AA512/24LC512/24FC512
NOTES:

24AA512/24LC512/24FC512
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
• General Technical Support – Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

24AA512/24LC512/24FC512
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: 24AA512/24LC512/24FC512 Literature Number: DS21754M
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?

24AA512/24LC512/24FC512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX Examples:

a) 24AA512-I/P: Industrial Temp.,
Device Temperature Package
1.7V, PDIP package.
Range
b) 24AA512T-I/SM: Tape and Reel,
Industrial Temp., 1.7V, SOIJ
Device: 24AA512: 512 Kbit 1.8V I2C Serial package.
EEPROM
c) 24AA512-I/MF: Industrial Temp.,
24AA512T: 512 Kbit 1.8V I2C Serial
1.7V, DFN package.
EEPROM (Tape and Reel)
24LC512: 512 Kbit 2.5V I2C Serial d) 24LC512-E/P: Extended Temp.,
EEPROM 2.5V, PDIP package.
24LC512T: 512 Kbit 2.5V I2C Serial e) 24LC512-I/SN: Industrial Temp.,
EEPROM (Tape and Reel) 2.5V, SOIC package.
24FC512: 512 Kbit 1 MHz I2C Serial f) 24LC512T-I/SM: Tape and Reel,
EEPROM Industrial Temp., 2.5V, SOIJ
24FC512T: 512 Kbit 1 MHz I2C Serial package.
EEPROM (Tape and Reel)
g) 24LC512-I/ST: Industrial Temp.,
2.5V, TSSOP package.
Temperature I = -40C to +85C h) 24FC512-I/P: Industrial Temp.,
Range: E = -40C to +125C 1.7V, High Speed, PDIP package.
i) 24FC512-I/SM: Industrial Temp.,
Package: P = Plastic DIP (300 mil body), 8-lead 1.7V, High Speed, SOIJ package.
SM = Plastic SOIJ (5.28 mm body), 8-lead j) 24FC512T-I/SN: Tape and Reel,
MF = Micro Lead Frame (6x5 mm body), Industrial Temp., 1.7V, High Speed,
8-lead SOIC package.
SN = Plastic SOIC (3.90 mm body), 8-lead
k) 24AA512T-I/CS17K: Industrial
ST = Plastic TSSOP (4.4 mm), 8-lead
Temp., 1.7V, CS package, Tape
ST14 = Plastic TSSOP (4.4 mm), 14-lead
and Reel
CS17K(1) = Chip Scale (CS), 8-lead (I-temp,
"AA", Tape and Reel only)
Note 1: "17K" indicates 160K technology.
 2010 Microchip Technology Inc. DS21754M-page33

24AA512/24LC512/24FC512
NOTES:
DS21754M-page34  2010 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PIC32 logo, rfPIC and UNI/O are registered trademarks of
MICROCHIP MAKES NO REPRESENTATIONS OR
Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control
QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip
FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-073-7
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

WORLDWIDE SALES AND SERVICE
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24AA512/24LC512/24FC512

512K I2C™ Serial EEPROM

A0 1 8 VCC A0 1 14 VCC VCC A1 A0

Note 1: Available in I-temp, “AA” only.

 2010 Microchip Technology Inc. DS21754M-page 1

TABLE 1-1: DC CHARACTERISTICS

DS21754M-page 2  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS21754M-page 3

DS21754M-page 4  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS21754M-page 5

TABLE 2-1: PIN FUNCTION TABLE

2.1 A0, A1 and A2 Chip Address 2.3 Serial Clock (SCL)

DS21754M-page 6  2010 Microchip Technology Inc.

4.3 Stop Data Transfer (C)

4.4 Data Valid (D)

 2010 Microchip Technology Inc. DS21754M-page 7

Start Address or Data Stop

FIGURE 4-2: ACKNOWLEDGE TIMING

SDA Data from transmitter Data from transmitter

DS21754M-page 8  2010 Microchip Technology Inc.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address High Byte Address Low Byte

 2010 Microchip Technology Inc. DS21754M-page 9

DS21754M-page 10  2010 Microchip Technology Inc.

FIGURE 6-2: PAGE WRITE

 2010 Microchip Technology Inc. DS21754M-page 11

Send Control Byte

DS21754M-page 12  2010 Microchip Technology Inc.

FIGURE 8-1: CURRENT ADDRESS

8.2 Random Read

 2010 Microchip Technology Inc. DS21754M-page 13

FIGURE 8-3: SEQUENTIAL READ

DS21754M-page 14  2010 Microchip Technology Inc.

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

8-Lead SOIJ (5.28 mm) Example:

8-Lead DFN-S Example:

Legend: XX...X Customer-specific information*

 2010 Microchip Technology Inc. DS21754M-page 15

8-Lead SOIC (3.90 mm) Example:

8-Lead TSSOP Example

14-Lead TSSOP Example

8-Lead Chip Scale Example:

First Line Marking Codes

Part No. 8- Lead TSSOP Package Codes

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 2010 Microchip Technology Inc. DS21754M-page 17

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

DS21754M-page 18  2010 Microchip Technology Inc.

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0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

DS21754M-page 20  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. DS21754M-page 21

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

DS21754M-page 22  2010 Microchip Technology Inc.

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DS21754M-page 24  2010 Microchip Technology Inc.

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0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

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