Scribd
Upload
1K views5 pages

Verilog Code For Floating Point 32-Bit Multiplication

This Verilog code defines a module to perform 32-bit floating point multiplication. It takes in two 32-bit floating point numbers (flp_a and flp_b) and outputs the sign, exponent, unbiased exponent, exponent sum, product, and final sum. It extracts the sign, exponent, and fraction from each input. It adds the biased exponents, removes the bias, multiplies the fractions, and postnormalizes the product. The final sum is formed by combining the sign, unbiased exponent, and product. A testbench is also defined which applies various input vectors and monitors the outputs.

Uploaded by

Vadlamudi Sree Harsha Chowdhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
1K views5 pages

Verilog Code For Floating Point 32-Bit Multiplication

This Verilog code defines a module to perform 32-bit floating point multiplication. It takes in two 32-bit floating point numbers (flp_a and flp_b) and outputs the sign, exponent, unbiased exponent, exponent sum, product, and final sum. It extracts the sign, exponent, and fraction from each input. It adds the biased exponents, removes the bias, multiplies the fractions, and postnormalizes the product. The final sum is formed by combining the sign, unbiased exponent, and product. A testbench is also defined which applies various input vectors and monitors the outputs.

Uploaded by

Vadlamudi Sree Harsha Chowdhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

Verilog code for floating point 32-bit multiplication: -

module mul (flp_a, flp_b, sign, exponent,exp_unbiased, exp_sum, prod,sum);


input [31:0] flp_a, flp_b;
output sign;output [7:0] exponent, exp_unbiased;
output [8:0] exp_sum;output [22:0] prod;
output [31:0] sum ;
//variables used in an always block are declared as registers
reg sign_a, sign_b;
reg [7:0] exp_a, exp_b;
reg [7:0] exp_a_bias, exp_b_bias;
reg [8:0] exp_sum;reg [22:0] fract_a, fract_b;
reg [45:0] prod_dbl;reg [22:0] prod;reg sign;
reg [31:0] sum ;reg [7:0] exponent, exp_unbiased;
//define sign, exponent, and fraction
always @ (flp_a or flp_b)
begin
sign_a = flp_a[31];
sign_b = flp_b[31];
exp_a = flp_a[30:23];
exp_b = flp_b[30:23];
fract_a = flp_a[22:0];
fract_b = flp_b[22:0];
//bias exponents
exp_a_bias = exp_a + 8'b0111_1111;
exp_b_bias = exp_b + 8'b0111_1111;
//add exponents
exp_sum = exp_a_bias + exp_b_bias;
//remove one bias
exponent = exp_sum - 8'b0111_1111;
exp_unbiased = exponent - 8'b0111_1111;
//multiply fractions
//if (flp_a != 0 || flp_b!=0) begin
prod_dbl = fract_a * fract_b;
prod = prod_dbl[45:23];
//postnormalize product
while (prod[22] == 0)
begin
prod = prod << 1;
exp_unbiased = exp_unbiased - 1;
end
sign = sign_a ^ sign_b;
if (prod ==0) begin
sum =32'b0;
end else sum ={sign, exp_unbiased, prod};
end //end
Endmodule
Testbench: -
module mul_tb;
reg [31:0] flp_a, flp_b;
wire sign;
wire [7:0] exponent, exp_unbiased;
wire [8:0] exp_sum;
wire [22:0] prod;
wire [31:0] sum ; //display variables
initial
$monitor ("sign = %b, exp_biased = %b, exp_unbiased = %b,prod = %b", sign, exp_sum,
exp_unbiased, prod); //apply input vectors
initial
begin
//+5 x +3 = +15
//s ----e---- --------------f-------------
#0 flp_a = 32'b0_0000_0011_1010_0000_0000_0000_0000_000;
flp_b = 32'b0_0000_0010_1100_0000_0000_0000_0000_000;
//+6 x +4 = +24
//s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0011_1100_0000_0000_0000_0000_000;
flp_b = 32'b0_0000_0011_1000_0000_0000_0000_0000_000;
//-5 x +5 = -25
//s ----e---- --------------f-------------
#10 flp_a = 32'b1_0000_0011_1010_0000_0000_0000_0000_000;
flp_b = 32'b0_0000_0011_1010_0000_0000_0000_0000_000;
//+7 x -5 = -35
//s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0011_1110_0000_0000_0000_0000_000;
flp_b = 32'b1_0000_0011_1010_0000_0000_0000_0000_000;
//+25 x +25 = +625
//+25 x +25 = +625
//s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0101_1100_1000_0000_0000_0000_000;
flp_b = 32'b0_0000_0101_1100_1000_0000_0000_0000_000;
//+76 x +55 = +4180
//s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_0111_1001_1000_0000_0000_0000_000;
flp_b = 32'b0_0000_0110_1101_1100_0000_0000_0000_000;
//-48 x -17 = +816
//s ----e---- --------------f-------------
#10 flp_a = 32'b0;
flp_b = 32'b1_0000_0101_1000_1000_0000_0000_0000_000;
//+3724 x +853 = +3,176,572
//s ----e---- --------------f-------------
#10 flp_a = 32'b0_0000_1100_1110_1000_1100_0000_0000_000;
flp_b = 32'b0_0000_1010_1101_0101_0100_0000_0000_000;
//s ----e---- --------------f-------------
#10 $stop;
end
//instantiate the module into the test bench
mul inst1 (.flp_a(flp_a),.flp_b(flp_b),.sign(sign),.exponent(exponent),.exp_unbiased(exp_unbiased),
.exp_sum(exp_sum),.sum(sum),.prod(prod));
Endmodule

You might also like