Digital Integrated

Circuits
A Design
Jan M. Rabaey
Perspective
Anantha Chandrakasan
Borivoje Nikolić

Logic Circuits
November 2002.

1
 Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

2
 Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

3
 Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

4
 NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

5
 PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

6
 Threshold Drops
VDD VDD
PUN
S D
VDD

D 0 Æ VDD S 0 Æ VDD - VTn

VGS
CL CL

PDN VDD Æ 0 VDD Æ |VTp|

VGS
D CL S CL
VDD

S D

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 Complementary CMOS Logic Style

8
 Example Gate: NAND

9
 Example Gate: NOR

10
 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

11
 Constructing a Complex Gate
VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

12
 Properties of Complementary CMOS Gates
Snapshot

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

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 CMOS Properties
• Full rail-to-rail swing; high noise margins
• Logic levels not dependent upon the relative
device sizes; ratioless
• Always a path to Vdd or Gnd in steady state; low
output impedance
• Extremely high input resistance; nearly zero
steady-state input current
• No direct path steady state between power and
ground; no static power dissipation
• Propagation delay function of load capacitance
and resistance of transistors

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 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

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 Input Pattern Effects on Delay
• Delay is dependent on the
Rp Rp pattern of inputs
A B • Low to high transition
– both inputs go low
Rn CL • delay is 0.69 Rp/2 CL
B – one input goes low
• delay is 0.69 Rp CL
Rn
Cint • High to low transition
A
– both inputs go high
• delay is 0.69 2Rn CL

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 Delay Dependence on Input Patterns

3
Input Data Delay
2.5
A=B=1Æ0
Pattern (psec)
2 A=B=0Æ1 67
A=1 Æ0, B=1
1.5 A=1, B=0Æ1 64
Voltage [V]

1
A=1, B=1Æ0 A= 0Æ1, B=1 61

0.5 A=B=1Æ0 45

0 A=1, B=1Æ0 80
0 100 200 300 400 A= 1Æ0, B=1 81
-0.5
time [ps] NMOS = 0.5mm/0.25 mm
PMOS = 0.75mm/0.25 mm
CL = 100 fF
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 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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 Transistor Sizing a Complex CMOS
Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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 Fan-In Considerations

A B C D

A CL Distributed RC model
(Elmore delay)
B C3
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C C2
Propagation delay deteriorates rapidly as a
D C1 function of fan-in – quadratically in the worst
case.

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 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a fan-in
750 greater than 4
should be avoided.
tp (psec)

tpHL tp
500

250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

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 tp as a Function of Fan-Out

All gates have the

same drive
tpNOR2 tpNAND2
current.

tpINV
tp (psec)

Slope is a function
of “driving
strength”

2 4 6 8 10 12 14 16
eff. fan-out

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 tp as a Function of Fan-In and Fan-Out

• Fan-in: quadratic due to increasing resistance

and capacitance
• Fan-out: each additional fan-out gate adds
two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

37
 Fast Complex Gates:
Design Technique 1
• Transistor sizing
– as long as fan-out capacitance dominates
• Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
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 Fast Complex Gates:
Design Technique 2
• Transistor ordering

critical path critical path

charged 0Æ1 charged

In3 1 In1 M3 CL
M3 CL
In2 1 M2 In2 1 M2 C2 discharged
C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0Æ1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

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 Fast Complex Gates:
Design Technique 3
• Alternative logic structures
F = ABCDEFGH

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 Fast Complex Gates:
Design Technique 4
• Isolating fan-in from fan-out using buffer
insertion

CL CL

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 Fast Complex Gates:
Design Technique 5
• Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

– linear reduction in delay

– also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on the receiving
end to restore the signal level (memory design)

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