The Effect of Electric Field On The Semiconductor Surface
The Effect of Electric Field On The Semiconductor Surface
Evac
= 2 1
1
2
E F1
EF
E F2
Fig. 33: Appearance of a contact potential at the interface of two dissimilar metals
Evac
Si M
M
Si
EC
E FM EF
E FSi
EV
Fig. 34: Appearance of a contact potential at the interface of a metal and intrinsic semiconductor
Of course, EFM is the Fermi level of the metal and M is the associated work function.
Likewise, EFSi is the Fermi level of the semiconductor and Si is its work function. Just
as in the case of two dissimilar metals, if one brings an intrinsic semiconductor and a
metal into close proximity, the metal tends to lose electrons to the semiconductor simply
because available energy states for electrons in the semiconductor are of lower energy,
i.e., because the Fermi level is lower in the semiconductor. Transient current flows until
equilibrium is established and the Fermi level becomes the same in both the metal and the
semiconductor. However, in contrast to the case of two metals, the transfer of electrons
to the semiconductor results in an electric field that penetrates the surface and causes the
band structure of the semiconductor to “bend”. If, as has been assumed, the metal work
function is smaller than the semiconductor work function, then the bands must bend
“downward”. This can be understood by observing that electrons transferred to the
semiconductor from the metal occupy states in the conduction band. (Of course, carrier
equilibrium implies that some electrons recombine with holes; however, this is only a
small fraction of electrons transferred.) Since these excess electrons are supplied from an
external source, holes do not appear in the valence band. Hence, the situation is very
similar to the case arising from shallow donor levels and the surface of the semiconductor
is no longer intrinsic, but becomes n-type. Accordingly, this implies that in proximity to
the surface, the Fermi level must lie above the intrinsic level. However, the condition of
equilibrium requires that the Fermi level is the same everywhere, thus, to satisfy this
condition the energy of the bands themselves must shift. Of course, the electrostatic field
arising from charge separation due to net electron transfer from the metal to the
semiconductor tends to confine excess electrons in the semiconductor in close proximity
to the surface. Therefore, at a distance sufficiently deep in the semiconductor bulk, the
semiconductor remains intrinsic. This implies, as is shown on the right side of the figure
that the bands bend smoothly in the region that the electric field penetrates into the
semiconductor.
One can further consider the effect of extrinsic doping. In the case of a p-type
semiconductor, the Fermi level in the bulk is shifted below the intrinsic level, Ei, by an
amount corresponding to the Fermi potential, F. Nevertheless, the effect of a metal
contact remains unchanged and the bands bend as illustrated for lightly and heavily
doped p-type substrates in the following figure:
EC
EC
Ei F
F Ei
EF EF
EV
EV
Depletion (p-type) Inversion (p-type)
Fig. 35: Depletion and inversion of p-type extrinsic semiconductor due to a metal contact
(In these diagrams and those that follow, F is to be understood as a measure of the
energy magnitude, |EF Ei |.) Again, when the metal and semiconductor initially come
into intimate contact, electrons are lost from the metal. Of course, in comparison to an
intrinsic semiconductor, the effective work function for a p-type semiconductor is larger
and downward band bending must be greater. However, in contrast to the intrinsic case,
instead of occupying empty conduction band states, electrons recombine with excess
holes in the valence band. If the net acceptor dopant concentration is sufficiently large
(i.e., heavy doping), an excess concentration of holes still remains at the surface once
equilibrium is established. However, near the surface, the distance between the valence
band edge and the Fermi level is increased, hence, the density of majority carriers (i.e.,
holes) is decreased and, thus, effective acceptor doping is reduced. This condition is
called depletion and corresponds to the left diagram in the preceding figure. Naturally,
there is still net charge separation due to electron transfer and a corresponding surface
electrostatic field.
Obviously, the intrinsic level bends along with the bands, therefore, in a doped
semiconductor the possibility exists that the bands may bend far enough so that the
intrinsic level and the Fermi level actually intersect. This typically happens if doping is
light and in the case of a p-type semiconductor majority carriers change from holes to
electrons such that at the surface the semiconductor changes from p-type to n-type. This
condition is called inversion and is illustrated by the right diagram in the preceding
figure. Inversion in a p-type semiconductor can be understood if one observes that upon
initial contact, as before, electrons from the metal recombine with holes in the valence
band. However, if acceptor doping is sufficiently low, all extrinsic holes are effectively
consumed, i.e., recombine, before equilibrium is established. At this point, the intrinsic
and Fermi levels are exactly equal and the semiconductor surface becomes effectively
intrinsic even though acceptor impurities are present. Consequently, additional electrons
transferred from the metal must occupy empty conduction band states and, thus, the
semiconductor surface becomes n-type. Of course, both depleted and inverted regions
are necessarily confined to a layer of semiconductor near the surface associated with
band bending.
In contrast to the case of a p-type semiconductor, in an n-type semiconductor the
Fermi level in the bulk is shifted above the intrinsic level, Ei, again, by an amount
corresponding to the Fermi potential, F. Therefore, in comparison to the intrinsic case,
the effective work function for an n-type semiconductor is smaller. This allows several
possibilities. First of all, if F is not too large, then the effective work function of the
semiconductor is still larger than for the metal and the bands still bend downward as in
the p-type case, but the degree of bending is necessarily less. Again, electrons are
transferred from the metal to the semiconductor; however, in this case rather than
recombining with holes in the valence band, electrons immediately occupy the
conduction band. Thus, the concentration of majority carriers (i.e., electrons) is increased
at the surface and effective doping is enhanced. This condition is called accumulation
and is illustrated by the left diagram in the following figure. Moreover, it can happen that
for a judicious choice of donor impurity concentration, the Fermi potential exactly offsets
the work function difference between the metal and semiconductor. In this case, no
charge transfer is required to establish equilibrium and the bands are not bent. This is
called the flat band condition and is illustrated by the right diagram in the following
figure:
EC EC
EF EF F
Ei Ei
F
EV EV
Accumulation (n-type) Flat Band (n-type)
Fig. 36: Flat band condition and accumulation of n-type extrinsic semiconductor due to a metal contact
However, if the Fermi potential for an n-type semiconductor is sufficiently large, the
effective semiconductor work function may actually be smaller than the metal work
function. In this case, electrons are transferred from the semiconductor to the metal
instead of from the metal to the semiconductor and bands are bent “upward” instead of
downward. Obviously, the majority carrier concentration is reduced at the semiconductor
surface; hence, this again corresponds to depletion. However, in this case depletion is a
consequence of the direct loss of electrons from the semiconductor to the metal rather
than recombination of excess electrons from the metal with holes in the semiconductor.
In both cases, a space charge region appears in the surface layer of the semiconductor due
to the presence of “uncovered” ionized impurity atoms. (Clearly, these charges are not
mobile since they are fixed in the silicon lattice.) Of course, depletion of n-type silicon
due to a metal contact is also represented by a band diagram, thus:
EC
EF
F
Ei
EV
Depletion (n-type)
All of these cases illustrate that penetration of the semiconductor surface by an electric
field alters effective doping at the surface from the net extrinsic doping of the bulk.
These are all examples of field effect. So far, these fields have been regarded as arising
from charge transfer induced by work function differences; however, it should be
apparent that field effects must arise any time an electric field penetrates a semiconductor
crystal irrespective of the source of the field.
The MOS Capacitor
EC EC
E FM E FSi
F
Ei Ei
F
E FM E FSi
EV EV
Depletion (p-type) Accumulation (n-type)
Here, the oxide layer is represented by the parallelogram separating metal and
semiconductor bands. (The width of the parallelogram corresponds to oxide thickness
and the slope of the top and bottom sides to internal electric field strength.) For p-type
silicon having a metal contact on the silicon dioxide layer, just as for a direct metal-
semiconductor contact, the bands generally bend downward and the semiconductor
becomes depleted or even inverted. Of course, the degree of depletion (or inversion) is
dependent on substrate doping, but the amount of band bending is not as great as in the
case of a metal-semiconductor contact since some of the electric field penetrates the
oxide layer, i.e., the potential due to the work function difference (contact potential) is
distributed over both the oxide layer and a surface layer in the semiconductor. The
situation remains similar for n-type silicon. Depending on the metal work function and
substrate doping, the bands may bend upward or downward (corresponding respectively
to accumulation or depletion and inversion), but again, not as much as in the case of a
direct metal contact.
Within this context, since thermal oxide is an excellent insulator, it becomes possible
to apply a much greater potential difference, i.e., bias voltage, between the metal and
semiconductor without an associated large current flow than is possible in the case of a
simple metal-semiconductor contact. In passing, it should be noted that application of an
external potential difference causes the Fermi levels in the metal and semiconductor in
both simple direct metal contacts and MOS structures to become offset. The magnitude
of the offset is, of course, exactly the energy gained by an electron “falling through” the
applied potential difference. Therefore, the sign of the Fermi level offset is opposite the
sign of the external potential difference since electrostatic potential is conventionally
defined with respect to positive rather than negative charge. Thus, a negative potential
difference between the metal and semiconductor causes a positive energy offset between
the metal and semiconductor Fermi levels. Conversely, a positive potential difference
between the metal and semiconductor causes a negative energy offset between the metal
and semiconductor Fermi levels. (This situation is also characteristic of contact
potentials in the absence of any external bias.)
Application of an external bias voltage to an MOS capacitor, allows the surface layer
of either n-type or p-type semiconductor to be accumulated, depleted, or inverted at will.
Moreover, in contrast to the case of an ideal parallel plate capacitor, which has a constant
capacitance for any value of applied voltage, the capacitance of an MOS structure
changes as a function of the condition of the semiconductor surface, i.e., the capacitance
is different depending on whether the semiconductor surface is accumulated, depleted, or
inverted. In addition, the capacitance-voltage (CV) response of an MOS capacitor
depends both on the characteristics of the oxide layer and the semiconductor substrate.
(As will become evident subsequently, the CV response of an MOS capacitor provides
very useful information regarding the behavior and quality of a Si/SiO2 interface.)
In practice, observation of CV response generally requires “sweeping” bias voltage
and simultaneously measuring capacitance. In the p-type case, accumulation occurs if the
applied bias is sufficiently negative. Clearly, this implies that a large concentration of
majority carriers (i.e., holes) is attracted to the semiconductor surface by the negative bias
voltage. Accordingly, if the bias voltage is made more positive, hole concentration at the
semiconductor surface must decrease. Moreover, a fixed bias can be found such that the
surface hole concentration becomes just equal to the hole concentration due to bulk
acceptor doping. In this case, the bands are flat (which formally specifies flat band
voltage). Therefore, any further increase in applied bias must cause the semiconductor
surface to become depleted. Obviously, increasing the bias voltage still further will cause
the surface to become first intrinsic and then inverted. At very high positive bias voltage,
the concentration of electrons in the inversion layer becomes large. Of course, the
behavior of n-type semiconductor can be expected to be inverted with respect to bias
voltage, but otherwise completely analogous. Naturally, accumulation for n-type
semiconductor will occur at sufficiently high positive bias voltage (instead of negative).
As bias is reduced, accumulation is followed by the flat band condition and then
depletion as the majority carrier concentration (i.e., electrons) falls below the bulk
electron concentration due to net donor doping. Further reduction of bias voltage to
negative values results first in an intrinsic surface and then in an inversion layer as holes
become majority carriers. These six applied bias conditions of an MOS capacitor are
illustrated in the following figure:
E FM
E FM
EC EC
E FSi
F
Ei Ei
F
E FS i
EV EV
Accumulation (p-type) Inversion (n-type)
EC
E FM EC
Ei E FSi
F F
E FS i Ei
E FM EV
EV
Depletion (p-type) Depletion (n-type)
EC
EC
F Ei E FS i
E FSi F
E FM Ei
EV
E FM EV
Fig. 39: Behavior of an MOS structure for both p and n-type substrates under various conditions of bias
Clearly, bias voltage increases from negative to more positive values as one sequentially
considers band diagrams from top to bottom and as expected, p and n-type
semiconductors exhibit complementary behavior.
Considering the case of an MOS capacitor fabricated on p-type silicon, if one initially
applies a negative voltage to the “gate” (i.e., the metal contact), it is clear that majority
carriers, i.e., holes, will be attracted to the surface forming an accumulation layer, i.e.,
the bands are strongly bent upward, increasing the effective doping of the surface relative
to the bulk. In this case, a sheet of negative charge will appear at the metal-oxide
interface and a sheet of positive charge will appear at the silicon-silicon oxide interface.
Clearly, this is similar to the simple case of a charged parallel plate capacitor. Thus, the
capacitance per unit area, called Cox, just corresponds to the elementary formula:
ox
Cox
xo
Here, ox is the dielectric constant of silicon dioxide (0.34 pF/cm) and xo is nominal oxide
thickness. If the magnitude of the negative voltage is reduced, i.e., bias voltage is
increased toward zero, then curvature of the bands decreases and, likewise, the degree of
accumulation decreases. Clearly, at some point, the bands will not be bent and the
surface will not be accumulated (or depleted), i.e., the silicon is neutral everywhere. This
is, of course, merely the flat band condition, which for this case occurs at a small
negative bias since work functions for metals, e.g., aluminum, typically are smaller than
for p-type silicon. Under this condition, the external potential exactly compensates the
intrinsic potential arising from the work function difference. As voltage is further
increased through zero to positive values, the bands bend the opposite direction, i.e.,
downward. (Clearly, it has already been established that the bands are bent downward at
zero bias.) In the case of a positive bias, but not too positive, one can easily visualize that
majority carriers will be repelled from the surface, thus, creating a region devoid of
mobile carriers. This is called the depletion region. Consequently, to satisfy charge
conservation requirements of the system, the depletion region must have a net negative
space charge. Of course, this space charge is provided by uncovered ionized dopant
atoms, i.e., in this case most likely negatively charged boron atoms. Since these negative
charges are not mobile, the conductivity of the depletion region is much lower than the
bulk semiconductor. It follows then that the capacitance per unit area of an MOS
structure in depletion, is the series combination of the oxide capacitance per unit area as
defined previously and a depletion layer capacitance per unit area, Cd:
s
Cd
xd
Here, s is the semiconductor dielectric constant (1.04 pF/cm for Si) and xd, is defined as
depletion width. Clearly, xd is not a physical thickness of a thin film in the same sense as
xo, but is an electrical equivalent thickness. (This will be treated in more detail
subsequently.) Naturally, if positive bias is increased still further, the bands continue to
bend downward until the intrinsic level and the Fermi level are just equal at the surface.
This defines the onset of inversion since as positive bias is increased further electrons
accumulate at the semiconductor surface to form an inversion layer. Thus, as asserted
previously, the semiconductor surface becomes effectively n-type. An additional
increase of bias voltage results in greater accumulation of electrons in the inversion layer
without substantial depletion of the underlying semiconductor. Therefore, once an
inversion layer is fully formed, the semiconductor does not deplete any further and xd
reaches a maximum value, x dmax . Obviously, maximum depletion capacitance per unit
area, Cs, is defined as follows:
s
Cs
xdmax
Within this context, the electrostatic potential and field within a semiconductor
surface layer can be readily analyzed quantitatively. For simplicity, the semiconductor
will be considered as a uniformly doped, semi-infinite silicon crystal in thermal
equilibrium. Accordingly, the semiconductor surface is defined by a plane located at
x 0 perpendicular to the x axis. Hence, the bulk of the semiconductor is characterized
by positive values of x. Naturally, an electrostatic surface potential, , is defined directly
from Poisson’s equation:
d 2 ( x)
dx 2
s
Here, (x) is net charge density. Clearly, (x) can be written as just the sum of
contributions from mobile carriers and ionized dopant atoms:
( x) q( p( x) n( x) N D N A )
Hence, one makes use of carrier equilibrium to construct expressions for carrier
concentrations as a function of x:
p ( x) n( x)
kT ln Ei ( x) EF ; kT ln Ei ( x) EF
ni ni
E Ei ( x) E ( x) EF
p( x) ni exp F ; n( x) ni exp i
kT kT
Clearly, hole concentration appears on the left and electron concentration on the right. Of
course, the intrinsic level is also a function of depth, x, since it bends with the bands. As
usual, for light to moderate doping these expressions can be regarded as explicitly of
Maxwellian form. Obviously, it follows that:
E ( x) EF
p( x) n( x) 2ni sinh i
kT
Naturally, deep within the bulk, i.e., in the limit that x , the condition of charge
neutrality must be satisfied, hence:
E EF
p() n() ( N D N A ) 2ni sinh i
kT
Here, Ei denotes the intrinsic level in the bulk, i.e., beyond the region of band bending.
Thus, these results can be readily combined to give an explicit expression for the charge
density:
E ( x ) EF Ei EF
( x) 2ni q sinh i sinh
kT kT
Of course, it follows from the Maxwellian forms that the electrostatic surface potential,
, is fundamentally related to the intrinsic level as follows:
EF Ei ( x)
q
Naturally, the “zero” of the potential may be always chosen arbitrarily. Clearly, the
preceding expression implies that vanishes if the intrinsic level and the Fermi level are
exactly equal; hence, Poisson’s equation takes the form:
d 2 2ni q q q
sinh sinh
dx 2
s kT kT
Here, is obviously identified as (EF Ei )/q. For convenience, dimensionless thermal
potentials, and are defined as q/kT and q/kT, respectively:
d 2 2q 2 ni
(sinh sinh )
dx 2 s kT
Upon inspection, a characteristic length, i, called the intrinsic Debye length can be
identified with the following combination of constants:
s kT
i
2q 2 ni
d d d d 2
2
2
dx dx dx dx 2
d d sinh sinh d
2
dx dx 2i dx
If one defines s and ds /dx, respectively, as and d/dx characteristic of the
semiconductor surface, i.e., x 0, then this expression can be cast into definite integral
form as follows:
d d sinh sinh
0 2
dx
d
d s dx
2i
s
Here, integration is taken from the surface into the bulk of the semiconductor.
Obviously, d/dx must be proportional to the electric field, hence:
d qE
dx kT
The integrals can be simplified by substitution of elementary forms, therefore one obtains
the result:
2
s 2 (cosh cosh s ( s ) sinh )
qE 2
kT i
Accordingly, at the surface of the semiconductor the electric field is determined in terms
of the dimensionless potential at the surface and in the bulk:
kT
Es sgn( s ) 2(( s ) sinh cosh cosh s )
q i
Here, “sgn” denotes the signum function, which merely specifies the sign as positive
(bands bend downward) or negative (bands bend upward). Accordingly, total charge per
unit area, Qs, is easily obtained using Gauss’ Law
s kT
Qs s Es sgn( s ) 2(( s ) sinh cosh cosh s )
q i
Surface charge density versus bias voltage for both p and n-type semiconductor is shown
in the following figure. (In practice, bias voltage can be regarded as surface potential, s,
plus some constant offset.)
10000000 10000000
100000 100000
Surface Charge Density
Surface Charge Density
10000 10000
1000 1000
depletion depletion
100 100
10 accumulation 10 accumulation
1 1
-30 -20 -10 0 10 20 30 -30 -20 -10 0 10 20 30
Bias Voltage Bias Voltage
p-type n-type
Fig. 40: Surface potential versus bias voltage (red indicates negative charge, blue positive charge)
If one identifies s as the the potential difference between the surface and the bulk,
s , one finds that for a p-type substrate Qs declines rapidly as s, i.e., potential bias,
is increased from accumulation to the flat band condition (at which point, by definition Qs
vanishes). As s is increased beyond the flat band condition, i.e., to positive values, the
magnitude of Qs increases slowly as the semiconductor surface is depleted. Obviously,
inversion must begin when s is equal to F, the Fermi potential in the bulk. (One notes
that F is equal to for a p-type substrate.) Furthermore, this implies that intrinsic and
actual Fermi levels are exactly equal at the surface. However, one finds that the
magnitude of Qs still increases only slowly until s is approximately twice the bulk Fermi
potential. This defines the condition of weak inversion. For values of s more positive
than 2F, the magnitude of Qs increases rapidly, thus, defining strong inversion. Clearly,
strong inversion in a p-type semiconductor occurs if the Fermi level is as far above the
intrinsic level at the surface as it is below the intrinsic level in the bulk. (Of course, an n-
type substrate exhibits analogous behavior with corresponding sign senses reversed.)
d 2 q
( N D ( x) N A ( x))
dx 2
s
Moreover, since carrier concentrations are ignored, the assumption of uniform doping can
be suspended and doping densities treated as general functions of x. Within this context,
it is useful to define the potential at the depletion region edge as, d , and the potential
difference across the depletion region, , as d . Thus, Poisson’s equation is easily
recast in terms of as follows:
d 2 q
( N D ( x) N A ( x))
dx 2
s
One readily integrates this expression from the depletion edge toward the semiconductor
surface:
E ( x)
d q d
x
0
d dx( N D ( x) N A ( x))
dx s x
Of course, the electric field, E(x), vanishes at the edge of the depletion region.
Furthermore, E(x) is just the negative of the potential gradient; hence, one can integrate a
second time as follows:
x x x
q d d
If the order of the integrals over x and x is formally inverted, then the integral over x is
readily simplified to give:
x x x
q d q d
s x x s x
( x) dx dx( N D ( x) N A ( x)) dx( x x)( N D ( x) N A ( x))
Obviously, this expression can be simplified no further without explicit knowledge of the
net impurity distribution.
If, for simplicity, one again assumes uniform doping, the previous expression can
easily be recast as follows:
d x
q q
( x) ( N D N A ) dx( x x) ( N A N D )( xd x) 2
s x
2 s
Thus, within this approximation, band bending has a parabolic shape as a function of
distance from the surface of the semiconductor. Furthermore, s is obtained by formally
setting x equal to zero:
q
s ( N A N D ) xd2
2 s
One can construct an approximate expression for the corresponding electric field by
directly differentiating:
q
E ( x) ( N A N D )( xd x)
s
Of course, the field at the surface is, again, obtained if x is set equal to zero:
q
Es ( N A N D ) xd
s
Likewise, the total charge per unit area in the depletion region is determined from Gauss’
Law:
Qs s Es q( N A N D ) xd
Alternatively, this expression follows just from elementary consideration of net impurity
concentration. Furthermore, one finds that capacitance per unit area of the depletion
region is just Qs /s as might be expected. For completeness, it is useful to observe that
within the depletion approximation the magnitude of Qs as a function of s is of simple
square root form:
| Qs | 2 s s q( N A N D )
Of course, for n-type and p-type semiconductors Qs is negative and positive, respectively.
Within this context, this formula is plotted in the previous figure and corresponds to the
“parabolic” curve coinciding with depletion. Clearly, as might be expected, the depletion
approximation is no longer applicable upon the onset of inversion.
The maximum depletion width expected under equilibrium conditions for a p-type
substrate can be determined by inverting the previous approximate expression for s and
replacing s by 2F, i.e., corresponding to the onset of strong inversion:
s F
xdmax 2
q( N A N D )
Naturally, this formula can be generalized to both n and p-type substrates by the simple
expedient of replacing NA ND with absolute value:
s F
xdmax 2
q N A ND
N ND
kT ln A Ei EF
ni
kT N A N D
F ln
q ni
One substitutes this formula into the expression for the maximum depletion width, x dmax ,
to obtain the desired result:
4 s kT N ND
xdmax ln A
q N A ND
2
ni
q s | N A ND |
Cs
2 kT ln(| N A N D | / ni )
In practice, both Cox and Cs are measured experimentally. These values can then be used
to determine oxide thickness and substrate doping. However, these quantities are better
measured by different methods and this is not the primary use of CV analysis, which is
characterization of the electrical quality of an oxide film and the Si/SiO2 interface.