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Explain Control Path in Pipeline or Pipelined Control?

The document discusses control in a pipelined processor. It explains that control signals are associated with specific pipeline stages and components. The control lines are divided into five groups according to the pipeline stage: instruction fetch, instruction decode/register file read, execution/address calculation, memory access, and write-back. Control is implemented by setting the appropriate control lines in each stage for each instruction based on the instruction type, similar to a single-cycle implementation. The control information is created during instruction decode and then used in later stages as the instruction moves through the pipeline.

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Loganathan Rm
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87 views

Explain Control Path in Pipeline or Pipelined Control?

The document discusses control in a pipelined processor. It explains that control signals are associated with specific pipeline stages and components. The control lines are divided into five groups according to the pipeline stage: instruction fetch, instruction decode/register file read, execution/address calculation, memory access, and write-back. Control is implemented by setting the appropriate control lines in each stage for each instruction based on the instruction type, similar to a single-cycle implementation. The control information is created during instruction decode and then used in later stages as the instruction moves through the pipeline.

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Loganathan Rm
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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3. Explain control path in pipeline or pipelined control?

Now in this section we add control to the pipelined data path. The PC is written on each
clock cycle, so there is no separate write signal for the PC. There are no separate write signals
for the pipeline registers (IF/ID, ID/EX, EX/MEM, and MEM/WB), since the pipeline registers
are also written during each clock cycle.
Each control line is associated with a component, that is active in only a single pipeline
stage. we can divide the control lines into five groups according to the pipeline stage.
1. Instruction fetch: The control signals to read instruction memory and to write the PC are
always asserted, so there is nothing special to control in this pipeline stage.

2. Instruction decode/register file read: As in the previous stage, the same thing happens at
every clock cycle, so there are no optional control lines to set.

3. Execution/address calculation: The signals to be set are RegDst, ALUOp, and ALUSrc .
The signals select the Result register, the ALU operation, and either Read data 2 or a sign-
extended immediate for the ALU.

4. Memory access: The control lines set in this stage are Branch, MemRead, and MemWrite.
The branch equal, load, and store instructions set these signals, respectively. Recall that PCSrc
in the figure selects the next sequential address unless control asserts Branch and the ALU
result was 0.

5. Write-back: The two control lines are MemtoReg, which decides between sending the ALU
result or the memory value to the register file, and Reg-Write, which writes the chosen value.
 Control signals derived from instruction as in single-cycle implementation, which
shows the signals of different instructions that are active during its respective stages
(refer table 4.49).
 Implementing control means setting the nine control lines to these values in each stage
for each instruction. The simplest way to do this is to extend the pipeline registers to
include control information.
 Since the control lines start with the EX stage, we can create the control information
during instruction decode. The figure 4.50 shows that these control signals are then
used in the appropriate pipeline stage as the instruction moves down the pipeline, just
as the destination register number for loads moves down the pipeline.

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