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1.whatismips, Mipsinstruction, Mipsimplementation: Mips R2000 Isa

The document discusses MIPS architecture and its implementation. It defines MIPS as a RISC instruction set and describes its key characteristics like fixed instruction width, load-store design, and three instruction formats. It then explains the basic implementation of a MIPS processor using functional units like ALU, registers, and memory interconnected via a datapath. The datapath is further broken down into five stages - fetch, decode, execute, memory, and writeback - to implement instruction pipelining for improved performance.

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Loganathan Rm
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59 views6 pages

1.whatismips, Mipsinstruction, Mipsimplementation: Mips R2000 Isa

The document discusses MIPS architecture and its implementation. It defines MIPS as a RISC instruction set and describes its key characteristics like fixed instruction width, load-store design, and three instruction formats. It then explains the basic implementation of a MIPS processor using functional units like ALU, registers, and memory interconnected via a datapath. The datapath is further broken down into five stages - fetch, decode, execute, memory, and writeback - to implement instruction pipelining for improved performance.

Uploaded by

Loganathan Rm
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1.

WhatisMIPS,MIPSInstruction, MIPSImplementation
MIPS is implementation of a RISC architecture

MIPS R2000 ISA

 Designed for use with high-level programming languages


o small set of instructions and addressing modes, easy for compilers
 Minimize/balance amount of work(computation and dataflow) per instruction
o Allows for parallel execution
 Load-store machine
o large register set, minimize main memory access
 fixed instruction width (32-bits),small set of uniform instruction encodings
o minimize control complexity, allow for more registers

MIPS Instructions

 MIPS instructions fall into 5 classes:


o Arithmetic/logical/shift/comparison
o Control instructions(branch and jump)
o Load/store
o Other (exception, register movement to/from GP registers, etc.)

Three instruction encoding formats


R-type (6-bit opcode, 5-bit rs, 5-bit rt, 5-bit rd, 5-bitshamt,6-bitfunctioncode)

I-type (6-bit opcode, 5-bit rs, 5-bit rt, 16-bitimmediate)

J-type(6-bitopcode, 26-bit pseudo-direct address)


Basic MIPS Implementation

For allinstructions,thefirsttwostepsarecommon:

 Settheprogramcounter(PC)tothememorylocationthatcontainsthecodeandfetchtheinstructionfr
omthatmemorylocation.
 Read oneortworegisters,usingthefieldsoftheinstruction.

Fig:Anabstractviewofthe implementationofthe MIPSsubset showing the


majorfunctionalunits and themajorconnectionsbetweenthem.

 Afterthesetwosteps,theactionsrequiredtocompletetheinstructiondependsontheinstruct
ionclass.

Threecommonlyused instruction classes are


1. MemoryReference
2. ArithmeticLogical
3. Branches

Foreachofthethreeinstructionclassestheactionsareexactlythesame,independentofthe
exactopcode.
 Across instructionstherearesome similarities.
o Forexample,allinstructionclasses,exceptjump,usethearithmetic-
logicalunit(ALU)afterreadingtheregisters.
o Thememory-referenceinstructionsusethe ALU
foranaddresscalculation,thearithmetic-
logicalinstructionsfortheoperationexecution,andbranchesforcomparison.
 AfterusingtheALU,theactionsrequiredtocompletevariousinstructionclassesdiffer.

 A memory-reference instruction will needto access thememoryeitherto read data


foraload orwrite datafora store. An arithmetic-logical or loadinstruction must write
thedatafrom the ALUor memoryback into a register.
 Lastly,forabranchinstruction,wemayneedtochangethenextinstructionaddressbasedonthe
comparison;otherwise,thePCshouldbeincrementedby4togettheaddress of the next
instruction.
 FigureAshowsthehigh-
levelviewofaMIPSimplementation,focusingonthevariousfunctional units and
theirinterconnection.
 The programcounter provides the addressof thenext instruction to be fetched.
 Afterthe instruction is fetched, the register operandsarefetched.
 Oncetheregisteroperandshavebeenfetched,theycanbeoperatedontocomputeamemoryadd
ress(foraloadorstore),tocomputeanarithmeticresult(foranintegerarithmetic-logical
instruction), or acompare (for a branch).
 Iftheinstructionisanarithmetic-logicalinstruction,theresultfromtheALUmustbewritten to
a register.
 Iftheoperationisaloadorstore,theALUresultisusedasanaddresstoeitherstoreavaluefrom
the registers or load a valuefrom memoryinto the registers.

Fig B:Thebasic implementationofthe MIPSsubset,including the


necessarymultiplexors and control lines
 Theresultfrom theALUor memoryis writtenback into the register file.
 Branches requirethe useof theALU output to determinethe next instruction address.
 Thethicklinesinterconnectingthefunctionalunitsrepresentbuses,whichconsistofmultiple
signals.
 FigureBshowsthedatapathofFigureAwiththethreerequiredmultiplexorsadded,aswellasco
ntrol lines for themajor functional units.
 Acontrolunit,usestheinstructionsasaninput,todeterminehowtosetthecontrollines forthe
functional unitsand two ofthe multiplexors.
 TheregularityandsimplicityoftheMIPSinstructionsetmeansthatasimpledecodingprocess
can be used to determinehow to set thecontrol lines.
 Thetopmultiplexor(“Mux”)controlswhatvaluereplacesthePC(PC+4orthebranchdestinati
onaddress);themultiplexoriscontrolledbythegatethat“ANDs”togethertheZerooutputofthe
ALUandacontrolsignalusedtoindicateiftheinstructionisabranch.
 Themiddlemultiplexor,whoseoutputreturnstotheregisterfile,isusedtosteertheoutput of
the ALU(in the case ofanarithmetic-logicalinstruction)or theoutput of thedata
memory(in thecaseof aload)for writinginto the registerfile.
 Finally,thebottommostmultiplexorisusedtodeterminewhetherthesecondALUinputisfrom
theregisters(foranarithmetic-logicalinstructionorabranch)orfromtheoffsetfield of the
instruction.
 TheaddedcontrollinesarestraightforwardanddeterminetheoperationperformedattheALU,
whetherthedatamemoryshouldreadorwrite,andwhethertheregistersshould perform
awrite operation.
2.ExplainDatapathin pipelineorpipelineddatapath?
Thedatapathisseparatedintofivepieces,witheachpiecenamedcorrespondingtoastageof
instructionexecution:
1. IF:Instruction fetch
2. ID:Instruction decodeandregisterfi le read
3. EX: Execution or addresscalculation
4. MEM: Data memoryaccess
5. WB: Write back

ReferAbovediagram,instructionsanddatamovegenerallyfromlefttorightthroughthefive
stagesastheycompleteexecution.
Thereare, however, twoexceptions to this left-to-right flow ofinstructions:
o Thewrite-back stage, which places theresultbackinto the registerfilein
themiddle ofthe datapath.
o Theselection ofthe next valueof thePC, choosingbetween the
incrementedPC and the branch address from theMEM stage.
Dataflowingfromrighttoleftdoesnotaffectthecurrentinstruction;thesereversedatamoveme
ntsinfluence onlylater instructions in the pipeline.
o The firstright-to-left flow ofdatacanlead todata hazards
o Thesecondright-to-left leads to controlhazards.
Toretainthevalueofanindividualinstructionfor
itsotherfourstages,thevaluereadfrominstructionmemorymustbesavedinaregister.Similarar
gumentsapplytoeverypipelinestage,sowemustplaceregisterswherevertherearedividingline
sbetweenstages.

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