TA84007PQ, TA84007SG, TA84007FG: Preliminary
TA84007PQ, TA84007SG, TA84007FG: Preliminary
TA84007PQ, TA84007SG, TA84007FG: Preliminary
TA84007PQ,TA84007SG,TA84007FG
DC Motor Full Bridge Driver ICs (Forward/reverse switching driver ICs)
Features
• Operation power supply voltage range:
VCC (opr.) = 4.5 to 27 V
VS (opr.) = 4.5 to 27 V
Vref (opr.) = 4.5 to 27 V
Usage Note:
Design your application so that Vref ≤ VS
TA84007FG
• Output current: PQ: 1.0 A (AVE.), 2.0 A (PEAK)
SG and FG: 0.4 A (AVE.), 1.2 A (PEAK)
• Built-in thermal shutdown and overcurrent protection
• Built-in back EMF suppression diode
• Built-in input hysteresis
• Built-in standby
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TA84007PQ/SG/FG
Block Diagram
VCC Vref
7/2/11 4/8/5
8/6/15 VS
REG OUT1
2/7/4
M
Protector
(thermal 10/3/13
shutdown) OUT2
Pin Functions
Pin No.
Symbol Description
PQ SG FG
VCC 7 2 11 Logic side power supply pin
VS 8 6 15 Output side power supply pin
Vref 4 8 5 Control power supply pin
GND 1 5 1 Ground
IN1 5 9 7 Input pin
IN2 6 1 9 Input pin
OUT1 2 7 4 Output pin
OUT2 10 3 13 Output pin
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TA84007PQ/SG/FG
Function
Input Output
Mode
IN1 IN2 OUT1 OUT2
0 0 ∞ ∞ Stop
1 0 H L CW/CCW
0 1 L H CCW/CW
1 1 L L Brake
∞: High impedance
VCC 30
Logic side power supply voltage V
VCC (opr.) 27
VS 30
Output side power supply voltage V
VS (opr.) 27
Vref 30
Control power supply voltage V
Vref (opr.) 27
PQ 2.0
PEAK IO (PEAK)
SG and FG 1.2
Power current A
PQ 1.0
AVE. IO (AVE.)
SG and FG 0.4
PQ 12.5 (Note 1)
Power dissipation SG PD 0.95 (Note 2) W
FG 1.4 (Note 3)
Operating temperature Topr −30 to 75 °C
Storage temperature Tstg −55 to 150 °C
Note 1: Tc = 25°C
Note 2: Standalone IC
Note 3: PCB mounting condition (PCB area 60 × 30 × 1.6 mm, occupies copper area of 50% or greater)
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TA84007PQ/SG/FG
Test Circuit 1.
ICC1, ICC2, ICC3
VS = 24 V
VS
7/2/11 4/8/5 8/6/15 A
VIN1
SW1 5/9/7 TA84007PQ/SG/AFG 2/7/4
VCC
5V
VIN2
SW2 6/1/9 10/3/13
3.5 V
VIN (H)
1/5/1
GND
Test Circuit 2.
VIN1, VIN 2, IIN, Iref
10 V
VS
Vref
SW3
VCC
5V
VS = 24 V
SW1
OUT1
5/9/7 TA84007PQ/SG/FG 2/7/4
VIN1
VIN2
6/1/9 10/3/13
A OUT2
SW2 1/5/1
VIN
5 V (max) GND
0 V (min)
TA84007PQ/SG/FG
TA84007FG’s fin is shorted to GND
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TA84007PQ/SG/FG
Test Circuit 3.
VSAT U-1, 2, 3 VSAT L-1, 2, 3 VSAT U-1’, 2’, 3’, 4’
SW4
VCC
5V
10 V
V
Vref VS
RL (Note)
7/2/11 4/8/5 8/6/15
OUT1
VS = 24 V
VIN1
SW1 5/9/7 TA84007PQ/SG/FG 2/7/4
VS
6/1/9 10/3/13 SW3
VIN2
SW2 OUT2
1/5/1 V
VIN (H)
3.5 V
GND
Test Circuit 4.
ILU, L
VS
VL = 30 V
A
7/2/11 4/8/5 8/6/15
VL
OUT1
5/9/7 2/7/4
TA84007PQ/SG/FG
6/1/9 10/3/13
OUT2
VL = 30 V
1/5/1 A
VL
TA84007PQ/SG/FG
TA84007FG’s fin is shorted to GND
Test Circuit 5.
VF U-1, 2 VF L-1, 2
VS
VU
IU
V
7/2/11 4/8/5 8/6/15
OUT1 SW1
5/9/7 2/7/4
TA84007PQ/SG/FG
6/1/9 10/3/13
OUT2 SW2
1/5/1
VU
IL
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TA84007PQ/SG/FG
TA84007PQ TA84007PQ
PD – Ta t – Rth
15
(1) Infinite heat sink (1) Infinite heat sink Input pulse
(1) (2) 80 cm2 × 2 mm Al (2) 80 cm2 × 2 mm Al heat sink PW
(W)
Rth (°C/W)
(θHS = 20°C/W)
(2)
(4) No heat sink 100 (4)
θj-a = 65°C/W 50
30
5 (2) (3)
(3)
10
(1)
(4) 5
3
0 1
0 50 100 150 200 10−2 10−1 1 10 102 103
TA84007SG TA84007SG
PD – Ta t – Rth
2.0 1000
Standalone
Standalone θj-a = 130°C/W 500
300
1.6
(W)
100
Rth (°C/W)
1.2
50
30
Input pulse
0.8
10
PW
5
0.4
3
t (s)
0 1
0 25 50 75 100 125 150 175 0.1 1 10 100 1000
TA84007FG TA84007FG
PD – Ta t – Rth
2.0
(1) PCB mounting condition (1) Standalone Input pulse
PCB area 60 × 30 × 1.6 mm (2) PCB mounting condition PW
1.6 occupies copper area of PCB area 60 × 30 × 1.6 mm
(W)
1.2 (1)
100
(2)
0.8 (2)
50
30
0.4
0 10
0 25 50 75 100 125 150 175 1 10 100 1000
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TA84007PQ TA84007PQ
VCE (SAT) – IOUT (upper side) VCE (SAT) – IOUT (lower side)
3.2 3.2
2.4 2.4
(V)
(V)
VCE (SAT)
VCE (SAT)
1.6 1.6
0.8 0.8
0 0
0 0.4 0.8 1.2 1.6 2.0 0 0.4 0.8 1.2 1.6 2.0
VCC
5V
5V
VS
7/2/11 8/6/15 Open 7/2/11 8/6/15 Open
VCC VS VCC VS
5/9/7 2/7/4 5/9/7 2/7/4
IN1 OUT1 IN1 OUT1
IN2 V IN2 V
6/1/9 6/1/9
G Vref G Vref
10 Ω
40 Ω
10 Ω
40 Ω
1/5/1 4/8/5 1/5/1 4/8/5
8V
Output open
Output open
10
9
40 Ω load
8
(V)
(V)
40 Ω load
10 Ω load
10 Ω load
VOUT (H)
VOUT (H)
6 8
0 6
0 2 4 6 8 10 12 8 9 10 11 12
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TA84007PQ/SG/FG
Usage Precautions
Power Input
When turning on the power, first apply power to VCC and then apply power to VS. (NOTE: It is also okay to
apply power to both at the same time.) When turning off the power, first turn off VS and then turn off VCC.
(NOTE: It is also okay to turn off both at the same time.)
1.3 kΩ
10 kΩ
VIN
apply the defined VIN (L) amount of voltage (or VIN 1 kΩ
5/9/7
lower) the corresponding pin will be grounded and
4.5 kΩ
logic will go low.
In addition, when logic is high, input current IIN or
will be inputted so be careful of the prior stage’s 6/1/9
output impedance. 5 kΩ
10 kΩ
Input hysteresis is 0.7 V (typ.)
When turning on the power (VCC), keep input
(both IN1 and IN2) low.
1/5/1
TA84007PQ/SG/FG
Output Circuitry
Output “H” Voltage
• Vref Voltage Operation 8/6/15
The voltage applied to Vref is filtered through the
Vref circuit and the resulting 2VBE (small signal) Q1
Q2
high voltage is applied to Q2 (Pw Tr)’s base-A. The A or 10/3/13
resulting VBE (Q2) low voltage is output as VOUT (H). VOUT
2/7/4
VOUT = Vref + 2VBE − VBE (Q2) @ Vref + 0.7 V Vref
4/8/5 Vref
circuit
• About the Vref Pin
When you aren’t using the Vref pin, don’t leave it
open but rather connect it to the VS pin using
protective resistance (of 3 kΩ or higher).
Also, design your application so that Vref ≤ VS. 1/5/1
TA84007PQ/SG/FG
Protector Function
Overcurrent Protection
If the current flowing to the upper power transistor is detected as being over the configured current threshold
(about 2.5 A), the overcurrent protector turns off all output. However, this doesn’t protect against all potential
overcurrent scenarios. For example, it is possible to destroy the IC due to an output short-circuit or grounding
fault prior to the overcurrent protector even being activated. Please connect a resistor or fuse to the power (VS)
line as protection against such overcurrent scenarios. (Refer to the application example on the next page.)
Thermal Shutdown
If the chip’s temperature is detected as being over the configured temperature threshold (about 170°C), the
thermal shutdown circuit turns off all output.
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TA84007PQ/SG/FG
Application Example
R1 (Note 2)
VS
VCC
(Note 1)
R2 (Note 3)
10 µF
7/2/11 8/6/15 4/8/5
TA84007PQ/SG/FG
Note 1: Experiment to determine the optimum capacity value (22 µF or greater) for the capacitor. Position the
capacitor near the pin (within 20 mm).
Note 3: If you wish to use the IC with VS = Vref, use a resistor to protect against Vref pin surge
Note 4: Utmost care is necessary in the design of the output, VCC, VM, and GND lines since the IC may be destroyed
by short-circuiting between outputs, air contamination faults, or faults due to improper grounding, or by
short-circuiting between contiguous pins.
Application Precautions
• Insert a stop (of about 100 µs) during switching (forward U reverse, forward/reverse U brake) to prevent against
in-rush current flow.
• IC functionality is not guaranteed when the IC is being powered on and off. Please confirm that there will be no
problems in your application in this regard.
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TA84007PQ/SG/FG
Package Dimensions
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Package Dimensions
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Package Dimensions
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TA84007PQ/SG/FG
Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified
for explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for
explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough
evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
case of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow and the
breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of
breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are
required.
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power
OFF. IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable,
the protection function may not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
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TA84007PQ/SG/FG
(4) Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s
power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the
device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid
this problem, take the effect of back-EMF into consideration in system design.
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