Introduction to Verilog HDL

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design

 Introduction
Verilog HDL: used to model a digital system at many levels of
abstraction (the algorithmic, gate-level and switch-level). Introdcution To Verilog cc

Complexity of the digital system: being modeled (a simple gate to a

complete electronic digital system)
Digital system can be described: hierarchically and timing can be
explicitly modeled within the same description.
Modeling Style:
• Describes the behavioral nature of a design,
• Describes the dataflow nature of a design,
• Describes a design’s structural composition,
• Mixed type of modeling.

Introduction to Verilog EC6203 Reconfigurable System Design

 History of Verilog
• 1983 - First developed by Gateway Design Automation to model
language for their simulator product. (proprietary language)
Introdcution To Verilog cc
• 1986- Extension version was Verilog-XL.
• 1990- Verilog was placed in the public domain In an effort to increase
the popularity of the language.
• 1992-Open Verilog International (OVI) was formed to promote Verilog.
• 1995- Verilog became an IEEE standard (IEEE Std 1364-1995).
• 2002- IEEE released a version IEEE 1364-2001.
• 2003- IEEE released a revised version 1364-2001 Revision C.

*Gateway Design Automation –Owner- Dr. Prabhu Goel (Acquired by

Cadence in 1989).
*Verilog HDL was designed by Phil Moorby.
*source: http://www.verilog.com/ ; https://en.wikipedia.org

Introduction to Verilog EC6203 Reconfigurable System Design

 Capabilities
Capabilities:
• Built-in Primitive logic gates, such as “and”, “or” and “nand”. Introdcution To Verilog cc
• Flexibility of creating a user-defined primitive (UDP). (Combinational and
sequential logic primitive)
• Switch-level modeling primitive gates, such as “pmos, nmos and cmos”.
• Specifying pin-to pin delays, path delays and timing checks of a design
• Data type- net data type and register data type.
• Hierarchical designs can be described, up to any level, (module instantiation
construct).
• A design can be of arbitrary size.
• Exchange language between tools and designers.
• PLI: allows functions to access information within a Verilog module and
allows for designer interaction with the simulator.
• Modeled hardware in a wide range of levels.
• Response monitoring and verification.
• Behavioral-level: Describes the architectural-level, its algorithmic-level and
RTL-level behavior.
• Model C type Constructs: If-else, case and loops etc.

Introduction to Verilog EC6203 Reconfigurable System Design

 Verilog: A Tutorial
• The basic unit of description in Verilog is the module. module module_name ( port_list );
• A module describes: functionality or structure of a design Declarations :
:describes the ports through which it communicates reg , wire , parameter ,
externally with other modules. input , output , inout ,
function, task,.
• The structure of a design is described using switch-level primitives, Statements :
gate-level primitives and user defined primitives; Initial statement
• Dataflow behavior of a design is described using continuous Always statement
assignments; Module instantiation
Gate instantiation
• Sequential behavior is described using procedural constructs. UDP instantiation
• A module can also be instantiated inside another module. Continuous assignment
endmodule

Module Name
IO Ports
Structure/
Functionality

Introduction to Verilog EC6203 Reconfigurable System Design

 Verilog: A Tutorial
Example:
2 continuous assignment statements with event trigger.
`timescale 1ns / 100ps //Time units-1ns, precision 0.1 ns

Introduction to Verilog EC6203 Reconfigurable System Design

 Data Flow Modelling
• In continuous assignment, a value is assigned to a net. (concurrent)
Syntax: assign [delay] LHS_net = RHS_expression;
Example: 2 to 4 decoder
`timescale 1ns / 1ns

Introduction to Verilog EC6203 Reconfigurable System Design

 Data Flow Modelling
Example: 2 to 4 decoder-(Simulation Results)

No delay value is specified, the default is zero delay

Introduction to Verilog EC6203 Reconfigurable System Design

 Behavioral Modelling
The behavior of a design is described using procedural constructs.
• Initial statement: This statement executes only once.
• Always statement: This statement always executes repeatedly.
• A register is used as data type to assign a value.
Example- 1-bit Full Adder

Introduction to Verilog EC6203 Reconfigurable System Design

 Behavioral Modelling
• A procedural assignment may optionally have a delay.
• Delays can be specified in two different forms:
• Inter-statement delay: This is the delay by which a statement’s
execution is delayed.
Sum = A ^B^Cin;
#4 T!= A & Cin;

• Intra-statement delay: This is the delay between computing the

value of the right-hand side expression and its assignment to the
left-hand side.
sum = #3 (A^B)^Cin;

• “reg” data type retains its value until a new value is assigned.
• All initial and always statements begin execution at time 0 concurrently.
• No delay= assignment occurs instantaneously

Introduction to Verilog EC6203 Reconfigurable System Design

 Behavioral Modelling
Example- initial statements.
'timescale 1ns / 1ns
module Test (P1, P2) ;
output P1, P2 ;
reg P1, P2 ;
initial
begin
P1 =0; // Stmt 1
P2 =0; // stmt 2
P1 = #5 1; // Stmt 3
P2 = #3 1; // Stmt 4
P1 = #6 0; // Stmt 5
P2 = #2 0; // Stmt 6
end
endmodule

Introduction to Verilog EC6203 Reconfigurable System Design

 Structural Modelling
Structures are described in Verilog by using:
• Built-in gate primitives (at the gate-level)
• Switch-level primitives (at the transistor-level)
• User-defined primitives (at the gate-level)
• Module instances (to create hierarchy)
Interconnections are specified by using nets.
Built-in gate primitives: (at the gate-level) :
• Verilog has in built primitive gates such as “and, or, xor, not” etc.
• This allows to call this gates and do the interconnection according
to our gate diagram
Syntax:
Gate_type label (output ports, input ports);

Eg: for a 3-input xor gate with Y output and A,B,C as input the syntax will
be :

xor x1 (Y, A, B, C); xor x1 (Y, A, B, C),

xor x2 (Y1, X, Y, Z); x2 (Y1, X, Y, Z);

Introduction to Verilog EC6203 Reconfigurable System Design

 Structural Modelling
Example- 1-bit Full Adder using primitive gates.

Introduction to Verilog EC6203 Reconfigurable System Design

 Structural Modelling
• Module Instantiation: 4-bit full-adder can be described by instantiating four 1-bit full-adder modules.

Introduction to Verilog EC6203 Reconfigurable System Design

 Mixed-design Modelling
A module can contain a mixture of gate instantiations, module instantiations,
continuous assignments, and always and initial statements. Gate Dataflow
Example- 1-bit Full Adder:

Behavioral

Introduction to Verilog EC6203 Reconfigurable System Design

 Simulating a Design
Test bench
Clock Gen
Unit
Reset Logic Under
Test
(UUT)
Test Gen at Inputs

Response Monitor Example- 1-bit Full Adder

Components of Test bench:

1. Module name(without I/Os)
2. wire and reg declaration,
3. UUT instantiation
4. Clock generator
5. Rest logic generator
6. Stimulus generator at inputs.

Introduction to Verilog EC6203 Reconfigurable System Design

 Simulating a Design
Example- 1-bit Full Adder:

Introduction to Verilog EC6203 Reconfigurable System Design

 Simulation Results
Example- 1-bit Full Adder:

Introduction to Verilog EC6203 Reconfigurable System Design

 Simulation Results
Example- 1-bit Full Adder:

time= 0::A=0, B=0, Cin=0, Sum=0, Cout =0

time= 10000::A=1, B=0, Cin=0, Sum=1, Cout =0
time= 20000::A=1, B=1, Cin=0, Sum=0, Cout =1
time= 40000::A=0, B=1, Cin=0, Sum=1, Cout =0

Introduction to Verilog EC6203 Reconfigurable System Design

References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com