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M
PIC16F87XA
Data Sheet
28/40-pin Enhanced FLASH
Microcontrollers

 2001 Microchip Technology Inc. Advance Information DS39582A

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PIC16F87XA
Pin Diagram

PDIP (40 pin)

MCLR/VPP 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5
RA2/AN2/VREF-/CVREF 4 37 RB4
RA3/AN3/VREF+ 5 36 RB3/PGM
RA4/T0CKI/C1OUT 6 35 RB2

PIC16F87A7/874A
RA5/AN4/SS/C2OUT 7 34 RB1
RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6

RA2/AN2/VREF-/CVREF
OSC1/CLKIN 13 28 RD5/PSP5
OSC2/CLKOUT 14 27 RD4/PSP4

RA3/AN3/VREF+
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK

MCLR/VPP
RC2/CCP1 17 24 RC5/SDO

RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 RD3/PSP3

RB5
RB4
19 22

NC

NC
RD1/PSP1 20 21 RD2/PSP2
PLCC

6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI/C1OUT 39 RB3/PGM
7
RA5/AN4/SS/C2OUT 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F877A 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F874A 33 RD7/PSP7
OSC1/CLKIN 14 32 RD6/PSP6
OSC2/CLKOUT 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
RC1/T1OSI/CCP2

18
19
20
21
22
23
24
25
26
27
282
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK

RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO

NC
RC4/SDI/SDA

RC6/TX/CK
RC2/CCP1

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC1/T1OSI/CCP2

RC3/SCK/SCL

RC5/SDO
NC

QFP
44
43
42
41
40
39
38
37
36
35
34

RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
RD6/PSP6 4 30 OSC1/CLKIN
RD7/PSP7 5 PIC16F877A 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F874A 27 RE2/AN7/CS
RB0/INT 8 26 RE1/AN6/WR
RB1 9 25 RE0/AN5/RD
RB2 10 24 RA5/AN4/SS/C2OUT
RB3/PGM 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22 RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RB4
RB5

RA0/AN0
RA1/AN1
NC
NC

RB6/PGC
RB7/PGD
MCLR/VPP

 2001 Microchip Technology Inc. Advance Information DS39582A-page 3

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PIC16F87XA
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
13 Data Bus 8 PORTA
Program Counter
RA0/AN0
FLASH
RA1/AN1
Program RA2/AN2/VREF-/CVREF
RAM RA3/AN3/VREF+
Memory 8 Level Stack
File RA4/T0CKI/C1OUT
(13-bit)
Registers RA5/AN4/SS/C2OUT
Program 14
RAM Addr(1) PORTB
Bus 9
RB0/INT
Addr MUX RB1
Instruction reg
RB2
Direct Addr 7 Indirect
8 Addr RB3/PGM
RB4
FSR reg RB5
RB6/PGC
STATUS reg RB7/PGD
8
PORTC
RC0/T1OSO/T1CKI
3 MUX RC1/T1OSI/CCP2
Power-up
Timer RC2/CCP1
RC3/SCK/SCL
Instruction Oscillator RC4/SDI/SDA
Decode & Start-up Timer ALU
Control RC5/SDO
Power-on RC6/TX/CK
Reset 8
RC7/RX/DT
Timing Watchdog
Generation W reg
Timer PORTD
OSC1/CLKIN Brown-out RD0/PSP0
OSC2/CLKOUT Reset RD1/PSP1
In-Circuit RD2/PSP2
Debugger RD3/PSP3
Low-Voltage RD4/PSP4
Programming RD5/PSP5
RD6/PSP6
RD7/PSP7

PORTE

MCLR VDD, VSS RE0/AN5/RD

RE1/AN6/WR
RE2/AN7/CS

Timer0 Timer1 Timer2 10-bit A/D Parallel Slave Port

Synchronous Voltage
Data EEPROM CCP1,2 USART Comparator Reference
Serial Port

Device Program FLASH Data Memory Data EEPROM

PIC16F874A 4K words 192 Bytes 128 Bytes

PIC16F877A 8K words 368 Bytes 256 Bytes

Note 1: Higher order bits are from the STATUS register.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 7

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PIC16F87XA
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
DIP PLCC QFP I/O/P Buffer
Pin Name Description
Pin# Pin# Pin# Type Type
PORTB is a bi-directional I/O port. PORTB can be soft-
ware programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 TTL/ST(1)
RB0 I/O Digital I/O.
INT I External interrupt.
RB1 34 37 9 I/O TTL Digital I/O.
RB2 35 38 10 I/O TTL Digital I/O.
RB3/PGM 36 39 11 TTL
RB3 I/O Digital I/O.
PGM I/O Low voltage ICSP programming enable pin.
RB4 37 41 14 I/O TTL Digital I/O.
RB5 38 42 15 I/O TTL Digital I/O.
RB6/PGC 39 43 16 TTL/ST(2)
RB6 I/O Digital I/O.
PGC I/O In-Circuit Debugger and ICSP programming clock.
RB7/PGD 40 44 17 TTL/ST(2)
RB7 I/O Digital I/O.
PGD I/O In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32 ST
RC0 I/O Digital I/O.
T1OSO O Timer1 oscillator output.
T1CKI I Timer1 external clock input.
RC1/T1OSI/CCP2 16 18 35 ST
RC1 I/O Digital I/O.
T1OSI I Timer1 oscillator input.
CCP2 I/O Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1 17 19 36 ST
RC2 I/O Digital I/O.
CCP1 I/O Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL 18 20 37 ST
RC3 I/O Digital I/O.
SCK I/O Synchronous serial clock input/output for SPI mode.
SCL I/O Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA 23 25 42 ST
RC4 I/O Digital I/O.
SDI I SPI data in.
SDA I/O I2C data I/O.
RC5/SDO 24 26 43 ST
RC5 I/O Digital I/O.
SDO O SPI data out.
RC6/TX/CK 25 27 44 ST
RC6 I/O Digital I/O.
TX O USART asynchronous transmit.
CK I/O USART 1 synchronous clock.
RC7/RX/DT 26 29 1 ST
RC7 I/O Digital I/O.
RX I USART asynchronous receive.
DT I/O USART synchronous data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 11

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PIC16F87XA
FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP

File File File File

Address Address Address Address

Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
PORTD(1) 08h TRISD(1) 88h 108h 188h
PORTE(1) 09h TRISE(1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh
TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h 95h 115h 195h
CCPR1H 16h 96h 116h 196h
CCP1CON 17h 97h General 117h General 197h
Purpose Purpose
RCSTA 18h TXSTA 98h Register 118h Register 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah 9Ah 11Ah 19Ah
CCPR2L 1Bh 9Bh 11Bh 19Bh
CCPR2H 1Ch CMCON 9Ch 11Ch 19Ch
CCP2CON 1Dh CVRCON 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h

General General General General

Purpose Purpose Purpose Purpose
Register Register Register Register
80 Bytes 80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
F0h 170h accesses 1F0h
accesses accesses
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ’0’.

* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876A.
2: These registers are reserved, maintain these registers clear.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 15

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PIC16F87XA
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Details
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on
POR, BOR
page:
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory 0000 0000 29, 148
(not a physical register)
101h TMR0 Timer0 Module Register xxxx xxxx 53, 148
102h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 28, 148
(3)
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 20, 148
104h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 29, 148
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 43, 148
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28, 148
10Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 22, 148
10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 37, 149
10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 37, 149
10Eh EEDATH — — EEPROM Data Register High Byte --xx xxxx 37, 149
(5)
10Fh EEADRH — — — — EEPROM Address Register High Byte ---- xxxx 37, 149
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory
0000 0000 29, 148
(not a physical register)
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 21, 148
(3)
182h PCL Program Counter (PC) Least Significant Byte 0000 0000 28, 148
183h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 20, 148
184h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 29, 148
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 43, 148
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28, 148
18Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 22, 148
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 32, 149
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 37, 149
18Eh — Reserved maintain clear 0000 0000 —
18Fh — Reserved maintain clear 0000 0000 —
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 19

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PIC16F87XA
2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 register contains the individual enable bits for enable any peripheral interrupt.
the peripheral interrupts.

REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc. Advance Information DS39582A-page 23

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PIC16F87XA
2.2.2.8 PCON Register Note: BOR is unknown on Power-on Reset. It
The Power Control (PCON) Register contains flag bits must be set by the user and checked on
to allow differentiation between a Power-on Reset subsequent RESETS to see if BOR is
(POR), a Brown-out Reset (BOR), a Watchdog Reset clear, indicating a brown-out has occurred.
(WDT), and an external MCLR Reset. The BOR status bit is a “don’t care” and is
not predictable if the brown-out circuit is
disabled (by clearing the BODEN bit in the
configuration word).

REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2001 Microchip Technology Inc. Advance Information DS39582A-page 27

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PIC16F87XA
3.0 DATA EEPROM AND 3.1 EEADR and EEADRH
FLASH PROGRAM MEMORY The EEADRH:EEADR register pair can address up to
The Data EEPROM and FLASH Program memory is a maximum of 256 bytes of data EEPROM or up to a
readable and writable during normal operation (over maximum of 8K words of program EEPROM. When
the full VDD range). This memory is not directly mapped selecting a data address value, only the LSByte of the
in the register file space. Instead, it is indirectly address is written to the EEADR register. When select-
addressed through the Special Function Registers. ing a program address value, the MSByte of the
There are six SFRs used to read and write this address is written to the EEADRH register and the
memory: LSByte is written to the EEADR register.

• EECON1 If the device contains less memory than the full address
reach of the address register pair, the Most Significant
• EECON2
bits of the registers are not implemented. For example,
• EEDATA if the device has 128 bytes of data EEPROM, the Most
• EEDATH Significant bit of EEADR is not implemented on access
• EEADR to data EEPROM.
• EEADRH
3.2 EECON1 and EECON2 Registers
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds EECON1 is the control register for memory accesses.
the address of the EEPROM location being accessed. Control bit EEPGD determines if the access will be a
These devices have 128 or 256 bytes of data EEPROM program or data memory access. When clear, as it is
(depending on the device), with an address range from when reset, any subsequent operations will operate on
00h to FFh. On devices with 128 bytes, addresses from the data memory. When set, any subsequent opera-
80h to FFh are unimplemented and will wrap around to tions will operate on the program memory.
the beginning of data EEPROM memory. When writing
to unimplemented locations, the on-chip charge pump Control bits RD and WR initiate read and write or erase,
will be turned off. respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
When interfacing the program memory block, the of the read or write operation. The inability to clear the
EEDATA and EEDATH registers form a two-byte word WR bit in software prevents the accidental, premature
that holds the 14-bit data for read/write, and the termination of a write operation.
EEADR and EEADRH registers form a two-byte word
that holds the 13-bit address of the program memory The WREN bit, when set, will allow a write or erase
location being accessed. These devices have 4 or 8K operation. On power-up, the WREN bit is clear. The
words of program FLASH with an address range from WRERR bit is set when a write (or erase) operation is
0000h to 0FFFh for the PIC16F873A/874A, and 0000h interrupted by a MCLR or a WDT Time-out Reset dur-
to 1FFFh for the PIC16F876A/877A. Addresses above ing normal operation. In these situations, following
the range of the respective device will wrap around to RESET, the user can check the WRERR bit and rewrite
the beginning of program memory. the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
The EEPROM data memory allows single byte read
and write. The FLASH program memory allows single Interrupt flag bit EEIF in the PIR2 register is set when
word reads and four-word block writes. Program mem- write is complete. It must be cleared in software.
ory write operations automatically perform an erase- EECON2 is not a physical register. Reading EECON2
before-write on blocks of four words. A byte write in will read all '0's. The EECON2 register is used
data EEPROM memory automatically erases the loca- exclusively in the EEPROM write sequence.
tion and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
Note: The self-programming mechanism for
write/erase voltages are generated by an on chip
FLASH program memory has been
charge pump, rated to operate over the voltage range
changed. On previous PIC16F87X
of the device for byte or word operations.
devices, FLASH programming was done in
When the device is code protected, the CPU may single word erase/write cycles. The newer
continue to read and write the data EEPROM memory. PIC16F87XA devices use a four-word
Depending on the settings of the write protect bits, the erase/write cycle. See Section 3.6 for
device may or may not be able to write certain blocks more information.
of the program memory; however, reads of the program
memory are allowed. When code protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 31

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PIC16F87XA
3.6 Writing to FLASH Program To transfer data from the buffer registers to the program
Memory memory, the EEADR and EEADRH must point to the
last location in the four-word block (EEADR<1:0> =
FLASH program memory may only be written to if the ‘11’). Then the following sequence of events must be
destination address is in a segment of memory that is executed:
not write protected, as defined in bits WRT1:WRT0 of
1. Set the EEPGD control bit (EECON1<7>)
the device configuration word (Register 14-1). FLASH
program memory must be written in four-word blocks. 2. Write 55h, then AAh, to EECON2 (FLASH pro-
A block consists of four words with sequential gramming sequence)
addresses, with a lower boundary defined by an 3. Set control bit WR (EECON1<1>) to begin the
address, where EEADR<1:0> = ‘00’. At the same time, write operation
all block writes to program memory are done as erase- The user must follow the same specific sequence to ini-
and-write operations. The write operation is edge- tiate the write for each word in the program block, writ-
aligned, and cannot occur across boundaries. ing each program word in sequence (00,01,10,11).
To write program data, it must first be loaded into the When the write is performed on the last word
buffer registers (see Figure 3-1). This is accomplished (EEADR<1:0> = ‘11’), the block of four words are
by first writing the destination address to EEADR and automatically erased, and the contents of the buffer
EEADRH, and then writing the data to EEDATA and registers are written into the program memory.
EEDATH. After the address and data have been set up, After the “BSF EECON1,WR“ instruction, the processor
then the following sequence of events must be exe- requires two cycles to set up the erase/write operation.
cuted: The user must place two NOP instructions after the WR
1. Set the EEPGD control bit (EECON1<7>) bit is set. Since data is being written to buffer registers,
2. Write 55h, then AAh, to EECON2 (FLASH pro- the writing of the first three words of the block appears
gramming sequence) to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
3. Set the WR control bit (EECON1<1>)
which the erase takes place (i.e., the last word of the
All four buffer register locations MUST be written to with four-word block). This is not SLEEP mode, as the
correct data. If only one, two, or three words are being clocks and peripherals will continue to run. After the
written to in the block of four words, then a read from write cycle, the processor will resume operation with
the program memory location(s) not being written to the third instruction after the EECON1 write instruction.
must be performed. This takes the data from the pro- If the sequence is performed to any other location, the
gram location(s) not being written and loads it into the action is ignored.
EEDATA and EEDATH registers. Then the sequence of
events to transfer data to the buffer registers must be
executed.

FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY

7 5 0 7 0
EEDATH EEDATA Four words of FLASH
are erased, then
all buffers are
6 8 transferred
to FLASH
automatically
First word of block after this word
to be written is written

14 14 14 14

EEADR<1:0> EEADR<1:0> EEADR<1:0> EEADR<1:0>

= ‘00’ = ‘01’ = ‘10’ = ‘11’
Buffer Register Buffer Register Buffer Register Buffer Register

Program Memory

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PIC16F87XA
4.0 I/O PORTS EXAMPLE 4-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
Some pins for these I/O ports are multiplexed with an BCF STATUS, RP1 ; Bank0
alternate function for the peripheral features on the CLRF PORTA ; Initialize PORTA by
device. In general, when a peripheral is enabled, that ; clearing output
pin may not be used as a general purpose I/O pin. ; data latches
Additional information on I/O ports may be found in the BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
PICmicro™ Mid-Range Reference Manual (DS33023).
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
4.1 PORTA and the TRISA Register ; initialize data
PORTA is a 6-bit wide, bi-directional port. The corre- ; direction
MOVWF TRISA ; Set RA<3:0> as inputs
sponding data direction register is TRISA. Setting a
; RA<5:4> as outputs
TRISA bit (= 1) will make the corresponding PORTA pin ; TRISA<7:6>are always
an input (i.e., put the corresponding output driver in a ; read as ’0’.
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin). FIGURE 4-1: BLOCK DIAGRAM OF
Reading the PORTA register reads the status of the RA3:RA0 PINS
pins, whereas writing to it will write to the port latch. All Data Latch
Data
write operations are read-modify-write operations. Bus
Therefore, a write to a port implies that the port pins are D Q
read, the value is modified and then written to the port VDD
WR
data latch. PORTA
CK Q
Pin RA4 is multiplexed with the Timer0 module clock P I/O pin(1)
input to become the RA4/T0CKI pin. The RA4/T0CKI TRIS Latch
pin is a Schmitt Trigger input and an open drain output. N
All other PORTA pins have TTL input levels and full D Q

CMOS output drivers. WR

Other PORTA pins are multiplexed with analog inputs TRISA VSS
CK Q
and the analog VREF input for both the A/D converters Analog
Input
and the comparators. The operation of each pin is Mode
selected by clearing/setting the appropriate control bits
in the ADCON1 and/or CMCON registers. RD
TRISA TTL
Note: On a Power-on Reset, these pins are con-
Input
figured as analog inputs and read as '0'. Buffer
The comparators are in the Off (digital) Q D
state.
The TRISA register controls the direction of the port
EN
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs. RD PORTA

To A/D Converter or Comparator

Note 1: I/O pins have protection diodes to VDD and VSS.

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PIC16F87XA
TABLE 4-3: PORTB FUNCTIONS

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input.

Internal software programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
(3)
RB3/PGM bit3 TTL Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or In-Circuit Debugger.
3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.

TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

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PIC16F87XA
4.5 PORTE and TRISE Register FIGURE 4-9: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Note: PORTE and TRISE are not implemented
on the 28-pin devices. Data Data Latch I/O pin(1)
Bus D Q
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6,
and RE2/CS/AN7), which are individually configurable WR
Port
as inputs or outputs. These pins have Schmitt Trigger CK
input buffers.
TRIS Latch
The PORTE pins become the I/O control inputs for the D Q
microprocessor port when bit PSPMODE (TRISE<4>) is WR
set. In this mode, the user must make certain that the TRIS
CK Schmitt
TRISE<2:0> bits are set, and that the pins are configured Trigger
Input
as digital inputs. Also ensure that ADCON1 is configured Buffer
for digital I/O. In this mode, the input buffers are TTL.
RD
Register 4-1 shows the TRISE register, which also con- TRIS
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When Q D
selected for analog input, these pins will read as ’0’s.
TRISE controls the direction of the RE pins, even when ENEN
they are being used as analog inputs. The user must RD Port
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs, and read as ‘0’.

TABLE 4-9: PORTE FUNCTIONS

Name Bit# Buffer Type Function

I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
RE0/RD/AN5 bit0 ST/TTL(1) 1 = Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected).
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
RE1/WR/AN6 bit1 ST/TTL(1) 1 = Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected).
I/O port pin or chip select control input in Parallel Slave Port mode or analog input:
CS
RE2/CS/AN7 bit2 ST/TTL(1)
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

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PIC16F87XA
5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
The Timer0 module timer/counter has the following increment either on every rising, or falling edge of pin
features: RA4/T0CKI. The incrementing edge is determined by
• 8-bit timer/counter the Timer0 Source Edge Select bit, T0SE
• Readable and writable (OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
• 8-bit software programmable prescaler
discussed in detail in Section 5.2.
• Internal or external clock select
The prescaler is mutually exclusively shared between
• Interrupt on overflow from FFh to 00h
the Timer0 module and the Watchdog Timer. The pres-
• Edge select for external clock caler is not readable or writable. Section 5.3 details the
Figure 5-1 is a block diagram of the Timer0 module and operation of the prescaler.
the prescaler shared with the WDT.
5.1 Timer0 Interrupt
Additional information on the Timer0 module is
available in the PICmicro™ Mid-Range MCU Family The TMR0 interrupt is generated when the TMR0 reg-
Reference Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit
Timer mode is selected by clearing bit T0CS TMR0IF (INTCON<2>). The interrupt can be masked
(OPTION_REG<5>). In Timer mode, the Timer0 mod- by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
ule will increment every instruction cycle (without pres- must be cleared in software by the Timer0 module
caler). If the TMR0 register is written, the increment is Interrupt Service Routine before re-enabling this inter-
inhibited for the following two instruction cycles. The rupt. The TMR0 interrupt cannot awaken the processor
user can work around this by writing an adjusted value from SLEEP, since the timer is shut-off during SLEEP.
to the TMR0 register.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (= FOSC/4) Data Bus

8
M 1
0
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 Reg
1 0
X Cycles

T0SE
T0CS
PSA Set Flag Bit TMR0IF
on Overflow
PRESCALER

0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer

8 - to - 1MUX PS2:PS0
PSA

0 1
WDT Enable bit
MUX PSA

WDT
Time-out

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

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PIC16F87XA
6.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input.
of two 8-bit registers (TMR1H and TMR1L), which are
Timer1 can be enabled/disabled by setting/clearing
readable and writable. The TMR1 Register pair
control bit, TMR1ON (T1CON<0>).
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled, Timer1 also has an internal “RESET input”. This
is generated on overflow, which is latched in interrupt RESET can be generated by either of the two CCP
flag bit, TMR1IF (PIR1<0>). This interrupt can be modules (Section 8.0). Register 6-1 shows the Timer1
enabled/disabled by setting/clearing TMR1 interrupt control register.
enable bit, TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is
Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
• As a Timer
ignored, and these pins read as ‘0’.
• As a Counter
Additional information on timer modules is available in
The operating mode is determined by the clock select the PICmicro™ Mid-Range MCU Family Reference
bit, TMR1CS (T1CON<1>). Manual (DS33023).

REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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PIC16F87XA
7.0 TIMER2 MODULE Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
Timer2 is an 8-bit timer with a prescaler and a
the PICmicro™ Mid-Range MCU Family Reference
postscaler. It can be used as the PWM time-base for
Manual (DS33023).
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET. FIGURE 7-1: TIMER2 BLOCK DIAGRAM
The input clock (FOSC/4) has a prescale option of Sets Flag
TMR2
bit TMR2IF Output(1)
1:1, 1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
RESET Prescaler
The Timer2 module has an 8-bit period register, PR2. TMR2 Reg FOSC/4
1:1, 1:4, 1:16
Timer2 increments from 00h until it matches PR2 and
Postscaler
then resets to 00h on the next increment cycle. PR2 is Comparator 2
1:1 to 1:16 EQ
a readable and writable register. The PR2 register is T2CKPS1:
initialized to FFh upon RESET. 4 PR2 Reg T2CKPS0

The match output of TMR2 goes through a 4-bit T2OUTPS3:

T2OUTPS0
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit Note 1: TMR2 register output can be software selected by the
TMR2IF, (PIR1<1>)). SSP module as a baud clock.

Timer2 can be shut-off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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PIC16F87XA
8.1 Capture Mode 8.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode, or Synchro-
16-bit value of the TMR1 register when an event occurs nized Counter mode, for the CCP module to use the
on pin RC2/CCP1. An event is defined as one of the capture feature. In Asynchronous Counter mode, the
following: capture operation may not work.
• Every falling edge
8.1.3 SOFTWARE INTERRUPT
• Every rising edge
• Every 4th rising edge When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
• Every 16th rising edge
CCP1IE (PIE1<2>) clear to avoid false interrupts and
The type of event is configured by control bits should clear the flag bit, CCP1IF, following any such
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap- change in operating mode.
ture is made, the interrupt request flag bit, CCP1IF
(PIR1<2>) is set. The interrupt flag must be cleared in 8.1.4 CCP PRESCALER
software. If another capture occurs before the value in
There are four prescaler settings, specified by bits
register CCPR1 is read, the old captured value is over-
CCP1M3:CCP1M0. Whenever the CCP module is
written by the new value.
turned off, or the CCP module is not in Capture mode,
8.1.1 CCP PIN CONFIGURATION the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
In Capture mode, the RC2/CCP1 pin should be config-
Switching from one capture prescaler to another may
ured as an input by setting the TRISC<2> bit.
generate an interrupt. Also, the prescaler counter will
Note: If the RC2/CCP1 pin is configured as an not be cleared, therefore, the first capture may be from
output, a write to the port can cause a a non-zero prescaler. Example 8-1 shows the recom-
capture condition. mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
RC2/CCP1 Set Flag bit CCP1IF
pin (PIR1<2>) CLRF CCP1CON ; Turn CCP module off
Prescaler
MOVLW NEW_CAPT_PS ; Load the W reg with
÷ 1, 4, 16
; the new prescaler
CCPR1H CCPR1L ; move value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with this
and Capture ; value
edge detect Enable

TMR1H TMR1L
CCP1CON<3:0>
Qs

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PIC16F87XA
TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS

0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh, 18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.

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PIC16F87XA
REGISTER 9-2: SSPCON: MSSP CONTROL REGISTER1 (SPI MODE) (ADDRESS 14h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSPBUF register is written while it is still transmitting the previous word.
(Must be cleared in software.)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must
read the SSPBUF, even if only transmitting data, to avoid setting overflow.
(Must be cleared in software.)
0 = No overflow
Note: In Master mode, the overflow bit is not set, since each new reception (and transmis-
sion) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = IDLE state for clock is a high level
0 = IDLE state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C
mode only.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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PIC16F87XA
9.3.6 SLAVE MODE the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
In Slave mode, the data is transmitted and received as output. External pull-up/pull-down resistors may be
the external clock pulses appear on SCK. When the desirable, depending on the application.
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave Mode with SS
While in Slave mode, the external clock is supplied by
pin control enabled (SSPCON<3:0> =
the external clock source on the SCK pin. This external
0100), the SPI module will reset if the SS
clock must meet the minimum high and low times, as
pin is set to VDD.
specified in the electrical specifications.
2: If the SPI is used in Slave Mode with CKE
While in SLEEP mode, the slave can transmit/receive
set, then the SS pin control must be
data. When a byte is received, the device will wake-up
enabled.
from SLEEP.
When the SPI module resets, the bit counter is forced
9.3.7 SLAVE SELECT to 0. This can be done by either forcing the SS pin to a
SYNCHRONIZATION high level or clearing the SSPEN bit.

The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can
SPI must be in Slave mode with SS pin control be connected to the SDI pin. When the SPI needs to
enabled (SSPCON<3:0> = 04h). The pin must not operate as a receiver, the SDO pin can be configured
be driven low for the SS pin to function as an input. as an input. This disables transmissions from the SDO.
The Data Latch must be high. When the SS pin is The SDI can always be left as an input (SDI function)
low, transmission and reception are enabled and since it cannot create a bus conflict.
the SDO pin is driven. When the SS pin goes high,

FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK
(CKP = 0
CKE = 0)

SCK
(CKP = 1
CKE = 0)

Write to
SSPBUF

SDO bit7 bit6 bit7 bit0

SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF

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PIC16F87XA
REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P S R/W UA BF
bit 7 bit 0

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: STOP bit
1 = Indicates that a STOP bit has been detected last
0 = STOP bit was not detected last
Note: This bit is cleared on RESET and when SSPEN is cleared.
bit 3 S: START bit
1 = Indicates that a START bit has been detected last
0 = START bit was not detected last
Note: This bit is cleared on RESET and when SSPEN is cleared.
bit 2 R/W: Read/Write bit information (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next START bit, STOP bit, or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is
in IDLE mode.
bit 1 UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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9.4.3.2 Reception 9.4.3.3 Transmission
When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set
address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the
register is cleared. The received address is loaded into SSPSTAT register is set. The received address is
the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will
(ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held
When the address byte overflow condition exists, then low, regardless of SEN (see “Clock Stretching”,
the No Acknowledge (ACK) pulse is given. An overflow Section 9.4.4, for more detail). By stretching the clock,
condition is defined as either bit BF (SSPSTAT<0>) is the master will be unable to assert another clock pulse
set or bit SSPOV (SSPCON<6>) is set. until the slave is done preparing the transmit data.The
transmit data must be loaded into the SSPBUF register,
An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then pin RC3/
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- SCK/SCL should be enabled by setting bit CKP
ware. The SSPSTAT register is used to determine the (SSPCON<4>). The eight data bits are shifted out on
status of the byte. the falling edge of the SCL input. This ensures that the
If SEN is enabled (SSPCON<0>=1), RC3/SCK/SCL SDA signal is valid during the SCL high time
will be held low (clock stretch) following each data (Figure 9-9).
transfer. The clock must be released by setting bit CKP The ACK pulse from the master-receiver is latched on
(SSPCON<4>). See Section 9.4.4 (“Clock Stretching”) the rising edge of the ninth SCL input pulse. If the SDA
for more detail. line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.

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FIGURE 9-11:

Bus Master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until

 2001 Microchip Technology Inc.

taken place taken place CKP is set to ‘1’
R/W = 0
Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W=1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P

SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software

BF (SSPSTAT<0>)

SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF

contents of SSPSR to clear BF flag BF flag is clear Write of SSPBUF Completion of
to clear BF flag initiates transmit data transmission
at the end of the
UA (SSPSTAT<1>) third address sequence clears BF flag

Advance Information
UA is set indicating that Cleared by hardware when Cleared by hardware when
the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address. byte of address.

UA is set indicating that

SSPADD needs to be
updated
CKP (SSPCON<4>)

CKP is set in software

I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

CKP is automatically cleared in hardware holding SCL low

DS39582A-page 87
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FIGURE 9-14:

Clock is held low until Clock is held low until

update of SSPADD has update of SSPADD has Clock is not held low
Clock is held low until
taken place taken place because ACK = 1
CKP is set to ‘1’
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
ACK ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

 2001 Microchip Technology Inc.

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P

SSPIF
Bus Master
(PIR1<3>) terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software

BF (SSPSTAT<0>)

SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF

contents of SSPSR to clear BF flag to clear BF flag
SSPOV (SSPCON<6>)

SSPOV is set
because SSPBUF is
still full. ACK is not sent.

UA (SSPSTAT<1>)

Advance Information
UA is set indicating that Cleared by hardware when Cleared by hardware when
the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address after falling edge byte of address after falling edge
of ninth clock. of ninth clock.

UA is set indicating that

SSPADD needs to be
updated
CKP
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will CKP written to ‘1’
have no effect on UA, and in software
UA will remain set.
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

Note: An update of the SSPADD

register before the falling
edge of the ninth clock will
have no effect on UA, and
UA will remain set.

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9.4.7 BAUD RATE GENERATOR Once the given operation is complete, (i.e. transmis-
sion of the last data bit is followed by ACK), the internal
In I2C Master mode, the baud rate generator (BRG) clock will automatically stop counting and the SCL pin
reload value is placed in the lower 7 bits of the will remain in its last state.
SSPADD register (Figure 9-17). When a write occurs to
SSPBUF, the baud rate generator will automatically Table 15-3 demonstrates clock rates based on instruc-
begin counting. The BRG counts down to 0 and stops tion cycles and the BRG value loaded into SSPADD.
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.

FIGURE 9-17: BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0 SSPADD<6:0>

SSPM3:SSPM0 Reload Reload

SCL Control

CLKOUT BRG Down Counter FOSC/4

TABLE 9-3: I2C CLOCK RATE W/BRG

FSCL
FCY FCY*2 BRG VALUE
(2 rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C
interface does not conform to the 400 kHz I2Cspecification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.

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9.4.10 I2C MASTER MODE 9.4.10.3 ACKSTAT Status Flag
TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge
other half of a 10-bit address is accomplished by simply (ACK = 0), and is set when the slave does Not
writing a value to the SSPBUF register. This action will Acknowledge (ACK = 1). A slave sends an Acknowl-
set the buffer full flag bit, BF, and allow the baud rate edge when it has recognized its address (including a
generator to begin counting and start the next transmis- general call), or when the slave has properly received
sion. Each bit of address/data will be shifted out onto its data.
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter #106). SCL 9.4.11 I2C MASTER MODE RECEPTION
is held low for one baud rate generator rollover count Master mode reception is enabled by programming the
(TBRG). Data should be valid before SCL is released receive enable bit, RCEN (SSPCON2<3>).
high (see Data setup time specification parameter
#107). When the SCL pin is released high, it is held that Note: The MSSP Module must be in an IDLE
way for TBRG. The data on the SDA pin must remain state before the RCEN bit is set, or the
stable for that duration and some hold time after the RCEN bit will be disregarded.
next falling edge of SCL. After the eighth bit is shifted The baud rate generator begins counting, and on each
out (the falling edge of the eighth clock), the BF flag is rollover, the state of the SCL pin changes (high to low/
cleared and the master releases SDA. This allows the low to high) and data is shifted into the SSPSR. After
slave device being addressed to respond with an ACK the falling edge of the eighth clock, the receive enable
bit during the ninth bit time, if an address match flag is automatically cleared, the contents of the
occurred or if data was received properly. The status SSPSR are loaded into the SSPBUF, the BF flag bit is
of ACK is written into the ACKDT bit on the falling edge set, the SSPIF flag bit is set and the baud rate genera-
of the ninth clock. If the master receives an Acknowl- tor is suspended from counting, holding SCL low. The
edge, the Acknowledge status bit, ACKSTAT, is MSSP is now in IDLE state, awaiting the next com-
cleared. If not, the bit is set. After the ninth clock, the mand. When the buffer is read by the CPU, the BF flag
SSPIF bit is set and the master clock (baud rate gener- bit is automatically cleared. The user can then send an
ator) is suspended until the next data byte is loaded Acknowledge bit at the end of reception, by setting the
into the SSPBUF, leaving SCL low and SDA Acknowledge sequence enable bit, ACKEN
unchanged (Figure 9-21). (SSPCON2<4>).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven 9.4.11.1 BF Status Flag
address bits and the R/W bit are completed. On the fall- In receive operation, the BF bit is set when an address
ing edge of the eighth clock, the master will de-assert or data byte is loaded into SSPBUF from SSPSR. It is
the SDA pin, allowing the slave to respond with an cleared when the SSPBUF register is read.
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address 9.4.11.2 SSPOV Status Flag
was recognized by a slave. The status of the ACK bit is In receive operation, the SSPOV bit is set when 8 bits
loaded into the ACKSTAT status bit (SSPCON2<6>). are received into the SSPSR and the BF flag bit is
Following the falling edge of the ninth clock transmis- already set from a previous reception.
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until 9.4.11.3 WCOL Status Flag
another write to the SSPBUF takes place, holding SCL
If the user writes the SSPBUF when a receive is
low and allowing SDA to float.
already in progress (i.e., SSPSR is still shifting in a data
9.4.10.1 BF Status Flag byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.

9.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress, (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.

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9.4.14 SLEEP OPERATION 9.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
While in SLEEP mode, the I2C
module can receive
addresses or data, and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from SLEEP (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
9.4.15 EFFECT OF A RESET outputs a '1' on SDA by letting SDA float high and
A RESET disables the MSSP module and terminates another master asserts a '0'. When the SCL pin floats
the current transfer. high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
9.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
In Multi-Master mode, the interrupt generation on the I2C port to its IDLE state (Figure 9-25).
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP If a transmit was in progress when the bus collision
(P) and START (S) bits are cleared from a RESET or occurred, the transmission is halted, the BF flag is
when the MSSP module is disabled. Control of the I 2C cleared, the SDA and SCL lines are de-asserted, and
bus may be taken when the P bit (SSPSTAT<4>) is set, the SSPBUF can be written to. When the user services
or the bus is IDLE, with both the S and P bits clear. the bus collision Interrupt Service Routine, and if the
When the bus is busy, enabling the SSP Interrupt will I2C bus is free, the user can resume communication by
generate the interrupt when the STOP condition asserting a START condition.
occurs. If a START, Repeated START, STOP, or Acknowledge
In multi-master operation, the SDA line must be moni- condition was in progress when the bus collision
tored for arbitration, to see if the signal level is at the occurred, the condition is aborted, the SDA and SCL
expected output level. This check is performed in hard- lines are de-asserted, and the respective control bits in
ware, with the result placed in the BCLIF bit. the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
The states where arbitration can be lost are: the I2C bus is free, the user can resume communication
• Address Transfer by asserting a START condition.
• Data Transfer The Master will continue to monitor the SDA and SCL
• A START Condition pins. If a STOP condition occurs, the SSPIF bit will be set.
• A Repeated START Condition A write to the SSPBUF will start the transmission of
• An Acknowledge Condition data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.

FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Data changes SDA line pulled low Sample SDA. While SCL is high
while SCL = 0 by another source data doesn’t match what is driven
by the master. Bus collision has occurred.
SDA released
by master

SDA

SCL Set bus collision

interrupt (BCLIF).

BCLIF

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9.4.17.3 Bus Collision During a STOP The STOP condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a STOP condition if:
the baud rate generator is loaded with SSPADD<6:0>
a) After the SDA pin has been de-asserted and and counts down to 0. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out. occurred. This is due to another master attempting to
b) After the SCL pin is de-asserted, SCL is sam- drive a data ’0’ (Figure 9-31). If the SCL pin is sampled
pled low before SDA goes high. low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data ’0’ (Figure 9-32).

FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCLIF.
SDA

SDA asserted low

SCL

PEN

BCLIF

P ’0’

SSPIF ’0’

FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG TBRG TBRG

SDA
Assert SDA SCL goes low before SDA goes high,
set BCLIF.
SCL

PEN

BCLIF

P ’0’

SSPIF ’0’

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10.1 USART Baud Rate Generator It may be advantageous to use the high baud rate
(BRG) (BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
The BRG supports both the Asynchronous and Syn- baud rate error in some cases.
chronous modes of the USART. It is a dedicated 8-bit
Writing a new value to the SPBRG register causes the
baud rate generator. The SPBRG register controls the
BRG timer to be reset (or cleared). This ensures the
period of a free running 8-bit timer. In Asynchronous
BRG does not wait for a timer overflow before output-
mode, bit BRGH (TXSTA<2>) also controls the baud
ting the new baud rate.
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the 10.1.1 SAMPLING
baud rate for different USART modes which only apply
in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
Given the desired baud rate and FOSC, the nearest
low level is present at the RX pin.
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.

TABLE 10-1: BAUD RATE FORMULA

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)

0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1))
1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A
X = value in SPBRG (0 to 255)

TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

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10.2.2 USART ASYNCHRONOUS is possible for two bytes of data to be received and
RECEIVER transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
The receiver block diagram is shown in Figure 10-4. the STOP bit of the third byte, if the RCREG register is
The data is received on the RC7/RX/DT pin and drives still full, the overrun error bit OERR (RCSTA<1>) will be
the data recovery block. The data recovery block is set. The word in the RSR will be lost. The RCREG reg-
actually a high speed shifter, operating at x16 times the ister can be read twice to retrieve the two bytes in the
baud rate; whereas, the main receive serial shifter FIFO. Overrun bit OERR has to be cleared in software.
operates at the bit rate or at FOSC. This is done by resetting the receive logic (CREN is
Once Asynchronous mode is selected, reception is cleared and then set). If bit OERR is set, transfers from
enabled by setting bit CREN (RCSTA<4>). the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
The heart of the receiver is the receive (serial) shift reg-
essential to clear error bit OERR if it is set. Framing
ister (RSR). After sampling the STOP bit, the received
error bit FERR (RCSTA<2>) is set if a STOP bit is
data in the RSR is transferred to the RCREG register (if
detected as clear. Bit FERR and the 9th receive bit are
it is empty). If the transfer is complete, flag bit RCIF
buffered the same way as the receive data. Reading
(PIR1<5>) is set. The actual interrupt can be enabled/
the RCREG will load bits RX9D and FERR with new
disabled by setting/clearing enable bit RCIE
values, therefore, it is essential for the user to read the
(PIE1<5>). Flag bit RCIF is a read only bit, which is
RCSTA register before reading the RCREG register in
cleared by the hardware. It is cleared when the RCREG
order not to lose the old FERR and RX9D information.
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It

FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK FERR

OERR
CREN
FOSC
SPBRG
÷64 MSb RSR Register LSb
or
Baud Rate Generator ÷16 STOP (8) 7 • • • 1 0 START

RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9

SPEN RX9D RCREG Register

FIFO

Interrupt RCIF
Data Bus
RCIE

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10.3 USART Synchronous Clearing enable bit TXEN during a transmission will
Master Mode cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-
In Synchronous Master mode, the data is transmitted in impedance. If either bit CREN or bit SREN is set during
a half-duplex manner (i.e., transmission and reception a transmission, the transmission is aborted and the DT
do not occur at the same time). When transmitting data, pin reverts to a hi-impedance state (for a reception).
the reception is inhibited and vice versa. Synchronous The CK pin will remain an output if bit CSRC is set
mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic, however, is not
addition, enable bit SPEN (RCSTA<7>) is set in order reset, although it is disconnected from the pins. In order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins to reset the transmitter, the user has to clear bit TXEN.
to CK (clock) and DT (data) lines, respectively. The If bit SREN is set (to interrupt an on-going transmission
Master mode indicates that the processor transmits the and receive a single word), then after the single word is
master clock on the CK line. The Master mode is received, bit SREN will be cleared and the serial port
entered by setting bit CSRC (TXSTA<7>). will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-
10.3.1 USART SYNCHRONOUS MASTER impedance Receive mode to transmit and start driving.
TRANSMISSION To avoid this, bit TXEN should be cleared.
The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9
Figure 10-6. The heart of the transmitter is the transmit (TXSTA<6>) bit should be set and the ninth bit should
(serial) shift register (TSR). The shift register obtains its be written to bit TX9D (TXSTA<0>). The ninth bit must
data from the read/write transmit buffer register, be written before writing the 8-bit data to the TXREG
TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can
software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR
bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and
soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D,
with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded.
TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master
(occurs in one TCYCLE), the TXREG is empty and inter- Transmission:
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE 1. Initialize the SPBRG register for the appropriate
(PIE1<4>). Flag bit TXIF will be set, regardless of the baud rate (Section 10.1).
state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by
ware. It will reset only when new data is loaded into the setting bits SYNC, SPEN and CSRC.
TXREG register. While flag bit TXIF indicates the status 3. If interrupts are desired, set enable bit TXIE.
of the TXREG register, another bit TRMT (TXSTA<1>) 4. If 9-bit transmission is desired, set bit TX9.
shows the status of the TSR register. TRMT is a read 5. Enable the transmission by setting bit TXEN.
only bit which is set when the TSR is empty. No inter-
6. If 9-bit transmission is selected, the ninth bit
rupt logic is tied to this bit, so the user has to poll this
should be loaded in bit TX9D.
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not 7. Start transmission by loading data to the TXREG
available to the user. register.
8. If using interrupts, ensure that GIE and PEIE
Transmission is enabled by setting enable bit TXEN
(bits 7 and 6) of the INTCON register are set.
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-10). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.

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TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
RESETS
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.

10.4.2 USART SYNCHRONOUS SLAVE When setting up a Synchronous Slave Reception, fol-
RECEPTION low these steps:

The operation of the Synchronous Master and Slave 1. Enable the synchronous master serial port by
modes is identical, except in the case of the SLEEP setting bits SYNC and SPEN and clearing bit
mode. Bit SREN is a “don't care” in Slave mode. CSRC.
2. If interrupts are desired, set enable bit RCIE.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during 3. If 9-bit reception is desired, set bit RX9.
SLEEP. On completely receiving the word, the RSR 4. To enable reception, set enable bit CREN.
register will transfer the data to the RCREG register 5. Flag bit RCIF will be set when reception is com-
and if enable bit RCIE bit is set, the interrupt generated plete and an interrupt will be generated, if
will wake the chip from SLEEP. If the global interrupt is enable bit RCIE was set.
enabled, the program will branch to the interrupt vector 6. Read the RCSTA register to get the ninth bit (if
(0004h). enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.

TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on
Value on:
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
RESETS
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.

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The ADRESH:ADRESL registers contain the 10-bit 2. Configure A/D interrupt (if desired):
result of the A/D conversion. When the A/D conversion • Clear ADIF bit
is complete, the result is loaded into this A/D result reg- • Set ADIE bit
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
• Set PEIE bit
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1. • Set GIE bit
3. Wait the required acquisition time.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con- 4. Start conversion:
version is started. The analog input channels must • Set GO/DONE bit (ADCON0)
have their corresponding TRIS bits selected as inputs. 5. Wait for A/D conversion to complete, by either:
To determine sample time, see Section 11.1. After this • Polling for the GO/DONE bit to be cleared
acquisition time has elapsed, the A/D conversion can (with interrupts enabled); OR
be started. • Waiting for the A/D interrupt
These steps should be followed for doing an A/D 6. Read A/D result register pair
Conversion: (ADRESH:ADRESL), clear bit ADIF, if required.
1. Configure the A/D module: 7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
• Configure analog pins/voltage reference and
defined as TAD.
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)

FIGURE 11-1: A/D BLOCK DIAGRAM

CHS2:CHS0

111
RE2/AN7(1)
110
RE1/AN6(1)

101
RE0/AN5(1)

100
RA5/AN4
VAIN
(Input Voltage) 011
RA3/AN3/VREF+

A/D 010
Converter RA2/AN2/VREF-

001
VDD RA1/AN1

000
VREF+ RA0/AN0

(Reference
Voltage)

PCFG3:PCFG0

VREF-

(Reference
Voltage)
VSS
PCFG3:PCFG0

Note 1: Not available on 28-pin devices.

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11.5 A/D Operation During SLEEP Note: For the A/D module to operate in SLEEP,
The A/D module can operate during SLEEP mode. This the A/D clock source must be set to RC
requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). To allow the con-
(ADCS1:ADCS0 = 11). When the RC clock source is version to occur during SLEEP, ensure the
selected, the A/D module waits one instruction cycle SLEEP instruction immediately follows the
before starting the conversion. This allows the SLEEP instruction that sets the GO/DONE bit.
instruction to be executed, which eliminates all digital 11.6 Effects of a RESET
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and A device RESET forces all registers to their RESET
the result loaded into the ADRES register. If the A/D state. This forces the A/D module to be turned off, and
interrupt is enabled, the device will wake-up from any conversion is aborted. All A/D input pins are con-
SLEEP. If the A/D interrupt is not enabled, the A/D mod- figured as analog inputs.
ule will then be turned off, although the ADON bit will The value that is in the ADRESH:ADRESL registers is
remain set. not modified for a Power-on Reset. The
When the A/D clock source is another clock option (not ADRESH:ADRESL registers will contain unknown data
RC), a SLEEP instruction will cause the present conver- after a Power-on Reset.
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.

TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D

Value on Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, MCLR,
BOR WDT
0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
9Fh ADCON1 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
(1)
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers are not available on 28-pin devices.

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12.2 Comparator Operation 12.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 12-2 along with The comparator module also allows the selection of an
the relationship between the analog input levels and internally generated voltage reference for the
the digital output. When the analog input at VIN+ is less comparators. Section 13.0 contains a detailed descrip-
than the analog input VIN–, the output of the tion of the Comparator Voltage Reference Module that
comparator is a digital low level. When the analog input provides this signal. The internal reference signal is
at VIN+ is greater than the analog input VIN–, the output used when comparators are in mode CM<2:0> = 110
of the comparator is a digital high level. The shaded (Figure 12-1). In this mode, the internal voltage refer-
areas of the output of the comparator in Figure 12-2 ence is applied to the VIN+ pin of both comparators.
represent the uncertainty due to input offsets and
response time. 12.4 Comparator Response Time
Response time is the minimum time, after selecting a
12.3 Comparator Reference
new reference voltage or input source, before the
An external or internal reference signal may be used comparator output has a valid level. If the internal ref-
depending on the comparator operating mode. The erence is changed, the maximum delay of the internal
analog signal present at VIN– is compared to the signal voltage reference must be considered when using the
at VIN+, and the digital output of the comparator is comparator outputs. Otherwise, the maximum delay of
adjusted accordingly (Figure 12-2). the comparators should be used (Section 17.0).

FIGURE 12-2: SINGLE COMPARATOR 12.5 Comparator Outputs

The comparator outputs are read through the CMCON
Register. These bits are read only. The comparator
VIN+ + outputs may also be directly output to the RA4 and RA5
Output I/O pins. When enabled, multiplexors in the output path
VIN– – of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 12-3 shows the com-
parator output block diagram.
VIN–
VIN–
The TRISA bits will still function as an output
VIN+
VIN+ enable/disable for the RA4 and RA5 pins while in this
mode.
The polarity of the comparator outputs can be changed
Output
utput using the C2INV and C1INV bits (CMCON<4:5>).
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
12.3.1 EXTERNAL REFERENCE SIGNAL convert an analog input, according to the
When external voltage references are used, the Schmitt Trigger input specification.
comparator module can be configured to have the com- 2: Analog levels on any pin defined as a dig-
parators operate from the same, or different reference ital input, may cause the input buffer to
sources. However, threshold detector applications may consume more current than is specified.
require the same reference. The reference signal must 3: RA4 is an open collector I/O pin. When
be between VSS and VDD, and can be applied to either used as an output, a pull-up resistor is
pin of the comparator(s). required.

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13.0 COMPARATOR VOLTAGE supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should be noted, however, that the
REFERENCE MODULE voltage at the top of the ladder is CVRSRC - VSAT, where
The Comparator Voltage Reference Generator is a VSAT is the saturation voltage of the power switch tran-
16-tap resistor ladder network that provides a fixed sistor. This reference will only be as accurate as the
voltage reference when the comparators are in mode values of CVRSRC and VSAT.
110. A programmable register controls the function of The output of the reference generator may be con-
the reference generator. Register 13-1 lists the bit func- nected to the RA2/AN2/VREF-/CVREF pin. This can be
tions of the CVRCON register. used as a simple D/A function by the user, if a very high
As shown in Figure 13-1, the resistor ladder is seg- impedance load is used. The primary purpose of this
mented to provide two ranges of CVREF values and has function is to provide a test path for testing the refer-
a power-down function to conserve power when the ence generator function.
reference is not being used. The comparator reference

REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0
bit 7 bit 0

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 ≤ VR3:VR0 ≤ 15
When CVRR = 1:
CVREF = (VR<3:0>/ 24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (VR3:VR0/ 32) • (CVRSRC)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

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14.2 Oscillator Configurations FIGURE 14-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
14.2.1 OSCILLATOR TYPES LP OSC
The PIC16F87XA can be operated in four different CONFIGURATION)
oscillator modes. The user can program two configura-
tion bits (FOSC1 and FOSC0) to select one of these
four modes: OSC1
Clock from
• LP Low Power Crystal Ext. System PIC16F87XA
• XT Crystal/Resonator Open OSC2
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor

14.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator TABLE 14-1: CERAMIC RESONATORS
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-1). The Ranges Tested:
PIC16F87XA oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give Mode Freq. OSC1 OSC2
a frequency out of the crystal manufacturers specifica- XT 455 kHz 68 - 100 pF 68 - 100 pF
tions. When in XT, LP or HS modes, the device can 2.0 MHz 15 - 68 pF 15 - 68 pF
have an external clock source to drive the OSC1/ 4.0 MHz 15 - 68 pF 15 - 68 pF
CLKIN pin (Figure 14-2). HS 8.0 MHz 10 - 68 pF 10 - 68 pF
16.0 MHz 10 - 22 pF 10 - 22 pF
FIGURE 14-1: CRYSTAL/CERAMIC
These values are for design guidance only.
RESONATOR OPERATION See notes following Table 14-2.
(HS, XT OR LP
OSC CONFIGURATION) Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
C1(1) OSC1
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
To
Internal 4.0 MHz Murata Erie CSA4.00MG ± 0.5%
XTAL
RF(3)
Logic 8.0 MHz Murata Erie CSA8.00MT ± 0.5%
OSC2 16.0 MHz Murata Erie CSA16.00MX ± 0.5%
SLEEP
Rs(2) All resonators used did not have built-in capacitors.
C2(1) PIC16F87XA

Note 1: See Table 14-1 and Table 14-2 for recom-

mended values of C1 and C2.
2: A series resistor (Rs) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.

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14.10 Power Control/Status Register occurred. When the Brown-out Reset is disabled, the
(PCON) state of the BOR bit is unpredictable and is, therefore,
not valid at any time.
The Power Control/Status Register, PCON, has up to
Bit1 is POR (Power-on Reset Status bit). It is cleared on
two bits depending upon the device.
a Power-on Reset and unaffected otherwise. The user
Bit0 is the Brown-out Reset Status bit, BOR. The BOR must set this bit following a Power-on Reset.
bit is unknown on a Power-on Reset. It must then be set
by the user and checked on subsequent RESETS to see
if it has been cleared, indicating that a BOR has

TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS

Power-up Wake-up from

Oscillator Configuration Brown-out
PWRTE = 0 PWRTE = 1 SLEEP

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — 72 ms —

TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE

POR BOR TO PD
0 x 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 1 1 Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x = don’t care, u = unchanged

TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON

Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).

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14.11 Interrupts The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
The PIC16F87XA family has up to 15 sources of inter- tained in the INTCON register.
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi- The peripheral interrupt flags are contained in the spe-
vidual and global interrupt enable bits. cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
Note: Individual interrupt flag bits are set, regard- function registers, PIE1 and PIE2, and the peripheral
less of the status of their corresponding interrupt enable bit is contained in special function reg-
mask bit, or the GIE bit. ister INTCON.
A global interrupt enable bit, GIE (INTCON<7>) When an interrupt is responded to, the GIE bit is
enables (if set) all unmasked interrupts, or disables (if cleared to disable any further interrupt, the return
cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded
interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the
vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling
abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be
ous registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to
regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts.
cleared on RESET.
For external interrupt events, such as the INT pin or
The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be
the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency
re-enables interrupts. depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.

FIGURE 14-10: INTERRUPT LOGIC

EEIF
EEIE
PSPIF(1)
PSPIE(1)
ADIF
ADIE
Wake-up (If in SLEEP mode)
RCIF TMR0IF
RCIE TMR0IE
INTF
TXIF
INTE
TXIE Interrupt to CPU
RBIF
SSPIF RBIE
SSPIE

CCP1IF PEIE
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE

CMIF
CMIE

Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.

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FIGURE 14-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)

INT pin
INTF Flag
(INTCON<1>) Interrupt Latency(2)

GIE bit
(INTCON<7>) Processor in
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(0004h)
Fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0005h)
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
Executed Inst(PC - 1) Inst(0004h)

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.

14.15 In-Circuit Debugger 14.16 Program Verification/Code

When the DEBUG bit in the configuration word is pro-
Protection
grammed to a ’0’, the In-Circuit Debugger functionality If the code protection bit(s) have not been pro-
is enabled. This function allows simple debugging func- grammed, the on-chip program memory can be read
tions when used with MPLAB® ICD. When the micro- out for verification purposes.
controller has this feature enabled, some of the
resources are not available for general use. Table 14-8 14.17 ID Locations
shows which features are consumed by the back-
ground debugger. Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
TABLE 14-8: DEBUGGER RESOURCES
not accessible during normal execution, but are read-
I/O pins RB6, RB7 able and writable during program/verify. It is recom-
Stack 1 level mended that only the 4 Least Significant bits of the ID
location are used.
Program Memory Address 0000h must be NOP
Last 100h words
Data Memory 0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.

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PIC16F87XA
15.2 Instruction Descriptions
ADDLW Add Literal and W BCF Bit Clear f
Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) + k → (W) 0≤b≤7

Status Affected: C, DC, Z Operation: 0 → (f<b>)

Description: The contents of the W register Status Affected: None

are added to the eight-bit literal ’k’ Description: Bit 'b' in register 'f' is cleared.
and the result is placed in the W
register.

ADDWF Add W and f BSF Bit Set f

Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] 0≤b≤7
Operation: (W) + (f) → (destination) Operation: 1 → (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit 'b' in register 'f' is set.
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.

ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set

Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
0≤b<7
Operation: (W) .AND. (k) → (W)
Operation: skip if (f<b>) = 1
Status Affected: Z
Status Affected: None
Description: The contents of W register are
AND’ed with the eight-bit literal Description: If bit 'b' in register 'f' is '0', the next
'k'. The result is placed in the W instruction is executed.
register. If bit 'b' is '1', then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2TCY instruction.

ANDWF AND W with f BTFSC Bit Test, Skip if Clear

Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] 0≤b≤7
Operation: (W) .AND. (f) → (destination) Operation: skip if (f<b>) = 0
Status Affected: Z Status Affected: None
Description: AND the W register with register Description: If bit 'b' in register 'f' is '1', the next
'f'. If 'd' is 0, the result is stored in instruction is executed.
the W register. If 'd' is 1, the result If bit 'b', in register 'f', is '0', the
is stored back in register 'f'. next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 159

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PIC16F87XA

RLF Rotate Left f through Carry SLEEP

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0 ≤ f ≤ 127 Operands: None
d ∈ [0,1] Operation: 00h → WDT,
Operation: See description below 0 → WDT prescaler,
Status Affected: C 1 → TO,
0 → PD
Description: The contents of register ’f’ are rotated
one bit to the left through the Carry Status Affected: TO, PD
Flag. If ’d’ is 0, the result is placed in Description: The power-down status bit, PD is
the W register. If ’d’ is 1, the result is cleared. Time-out status bit, TO
stored back in register ’f’. is set. Watchdog Timer and its
C Register f prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.

RETURN Return from Subroutine SUBLW Subtract W from Literal

Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k
Operands: None Operands: 0 ≤ k ≤ 255
Operation: TOS → PC Operation: k - (W) → (W)
Status Affected: None Status Affected: C, DC, Z
Description: Return from subroutine. The stack Description: The W register is subtracted (2’s
is POPed and the top of the stack complement method) from the
(TOS) is loaded into the program eight-bit literal 'k'. The result is
counter. This is a two-cycle placed in the W register.
instruction.

RRF Rotate Right f through Carry SUBWF Subtract W from f

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] d ∈ [0,1]
Operation: See description below Operation: (f) - (W) → (destination)
Status Affected: C Status C, DC, Z
Description: The contents of register ’f’ are Affected:
rotated one bit to the right through Description: Subtract (2’s complement method)
the Carry Flag. If ’d’ is 0, the result W register from register 'f'. If 'd' is 0,
is placed in the W register. If ’d’ is the result is stored in the W
1, the result is placed back in register. If 'd' is 1, the result is
register ’f’. stored back in register 'f'.
C Register f

 2001 Microchip Technology Inc. Advance Information DS39582A-page 163

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PIC16F87XA
16.8 MPLAB ICD In-Circuit Debugger 16.11 PICDEM 1 Low Cost PICmicro
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
Demonstration Board
erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board
based on the FLASH PICmicro MCUs and can be used which demonstrates the capabilities of several of
to develop for this and other PICmicro microcontrollers. Microchip’s microcontrollers. The microcontrollers sup-
The MPLAB ICD utilizes the in-circuit debugging capa- ported are: PIC16C5X (PIC16C54 to PIC16C58A),
bility built into the FLASH devices. This feature, along PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
with Microchip’s In-Circuit Serial ProgrammingTM proto- PIC17C42, PIC17C43 and PIC17C44. All necessary
col, offers cost-effective in-circuit FLASH debugging hardware and software is included to run basic demo
from the graphical user interface of the MPLAB programs. The user can program the sample microcon-
Integrated Development Environment. This enables a trollers provided with the PICDEM 1 demonstration
designer to develop and debug source code by watch- board on a PRO MATE II device programmer, or a
ing variables, single-stepping and setting break points. PICSTART Plus development programmer, and easily
Running at full speed enables testing hardware in real- test firmware. The user can also connect the
time. PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
16.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the
Programmer user to build some additional hardware and connect it
The PRO MATE II universal device programmer is a to the microcontroller socket(s). Some of the features
full-featured programmer, capable of operating in include an RS-232 interface, a potentiometer for simu-
stand-alone mode, as well as PC-hosted mode. The lated analog input, push button switches and eight
PRO MATE II device programmer is CE compliant. LEDs connected to PORTB.

The PRO MATE II device programmer has program- 16.12 PICDEM 2 Low Cost PIC16CXX
mable VDD and VPP supplies, which allow it to verify Demonstration Board
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem-
and error messages, keys to enter commands and a onstration board that supports the PIC16C62,
modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74
package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft-
device programmer can read, verify, or program ware is included to run the basic demonstration pro-
PICmicro devices. It can also set code protection in this grams. The user can program the sample
mode. microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
16.10 PICSTART Plus Entry Level or a PICSTART Plus development programmer, and
Development Programmer easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
The PICSTART Plus development programmer is an board to test firmware. A prototype area has been pro-
easy-to-use, low cost, prototype programmer. It con- vided to the user for adding additional hardware and
nects to the PC via a COM (RS-232) port. MPLAB connecting it to the microcontroller socket(s). Some of
Integrated Development Environment software makes the features include a RS-232 interface, push button
using the programmer simple and efficient. switches, a potentiometer for simulated analog input, a
The PICSTART Plus development programmer sup- serial EEPROM to demonstrate usage of the I2CTM bus
ports all PICmicro devices with up to 40 pins. Larger pin and separate headers for connection to an LCD
count devices, such as the PIC16C92X and module and a keypad.
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 167

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PIC16F87XA
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Voltage on RA4 with respect to Vss ..................................................................................................................0 to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 171

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PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF873A/874A/876A/877A (Industrial)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC16F873A/874A/876A/877A (Industrial)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param Symbol Characteristic/ Min Typ† Max Units Conditions
No. Device
IPD Power-down Current(3,5)
D020 16LF87XA — 7.5 30 µA VDD = 3.0V, WDT enabled,
-40°C to +85°C
D020 16F87XA — 10.5 42 µA VDD = 4.0V, WDT enabled,
-40°C to +85°C
D021 16LF87XA — 0.9 5 µA VDD = 3.0V, WDT disabled,
0°C to +70°C
D021 16F87XA — 1.5 16 µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
D021A 16LF87XA 0.9 5 µA VDD = 3.0V, WDT disabled,
-40°C to +85°C
D021A 16F87XA 1.5 19 µA VDD = 4.0V, WDT disabled,
-40°C to +85°C
D023 ∆IBOR Brown-out — 85 200 µA BOR enabled, VDD = 5.0V
Reset Current(6)
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 175

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PIC16F87XA
17.3 Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition

FIGURE 17-3: LOAD CONDITIONS

Load Condition 1 Load Condition 2

VDD/2

RL

CL CL
Pin Pin

VSS VSS
RL = 464 Ω
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 179

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PIC16F87XA
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

40 41

42

RC0/T1OSO/T1CKI

45 46

47 48

TMR0 or
TMR1

Note: Refer to Figure 17-3 for load conditions.

TABLE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
Symbol Characteristic Min Typ† Max Units Conditions
No.

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
With Prescaler 10 — — ns parameter 42
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
With Prescaler 10 — — ns parameter 42
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of: — — ns N = prescale value
20 or TCY + 40 (2, 4,..., 256)
N
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
Synchronous, Standard(F) 15 — — ns parameter 47
Prescaler = 2,4,8 Extended(LF) 25 — — ns
Asynchronous Standard(F) 30 — — ns
Extended(LF) 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
Synchronous, Standard(F) 15 — — ns parameter 47
Prescaler = 2,4,8 Extended(LF) 25 — — ns
Asynchronous Standard(F) 30 — — ns
Extended(LF) 50 — — ns
47* Tt1P T1CKI input Synchronous Standard(F) Greater of: — — ns N = prescale value
period 30 OR TCY + 40 (1, 2, 4, 8)
N
Extended(LF) Greater of: N = prescale value
50 OR TCY + 40 (1, 2, 4, 8)
N
Asynchronous Standard(F) 60 — — ns
Extended(LF) 100 — — ns
Ft1 Timer1 Oscillator Input Frequency Range DC — 200 kHz
(oscillator enabled by setting bit T1OSCEN)
48 TCKEZtmr1 Delay from external clock edge to timer increment 2TOSC — 7TOSC —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 183

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PIC16F87XA
FIGURE 17-13: SPI SLAVE MODE TIMING (CKE = 0)

SS

70
SCK
(CKP = 0) 83

71 72
78 79

SCK
(CKP = 1)

79 78
80

SDO MSb BIT6 - - - - - -1 LSb

75, 76 77

SDI MSb IN BIT6 - - - -1 LSb IN

74
73

Note: Refer to Figure 17-3 for load conditions.

FIGURE 17-14: SPI SLAVE MODE TIMING (CKE = 1)

82
SS

70
SCK
83
(CKP = 0)

71 72

SCK
(CKP = 1)
80

SDO MSb BIT6 - - - - - -1 LSb

75, 76 77

SDI
MSb IN BIT6 - - - -1 LSb IN

74

Note: Refer to Figure 17-3 for load conditions.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 187

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PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK
Pin 121
121
RC7/RX/DT
Pin

120
122
Note: Refer to Figure 17-3 for load conditions.

TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param
Sym Characteristic Min Typ† Max Units Conditions
No.

120 TckH2dtV SYNC XMIT (MASTER & Standard(F)

SLAVE) — — 80 ns
Clock high to data out valid Extended(LF) — — 100 ns
121 Tckrf Clock out rise time and fall time Standard(F) — — 45 ns
(Master mode) Extended(LF) — — 50 ns
122 Tdtrf Data out rise time and fall time Standard(F) — — 45 ns
Extended(LF) — — 50 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

FIGURE 17-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK
pin 125
RC7/RX/DT
pin

126

Note: Refer to Figure 17-3 for load conditions.

TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Parameter
Sym Characteristic Min Typ† Max Units Conditions
No.

125 TdtV2ckL SYNC RCV (MASTER & SLAVE)

Data setup before CK↓ (DT setup time) 15 — — ns
126 TckL2dtl Data hold after CK↓ (DT hold time) 15 — — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 191

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PIC16F87XA
18.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs are not available at this time.

 2001 Microchip Technology Inc. Advance Information DS39582A-page 195

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PIC16F87XA
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

E1

2 α
n 1

A A2

L
c

β B1
A1
eB B p

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 40 40
Pitch p .100 2.54
Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83
Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88
Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22
Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45
Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016

 2001 Microchip Technology Inc. Advance Information DS39582A-page 199

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PIC16F87XA
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

E
E1
p

B
2
n 1

h
α

45°

c
A A2

φ
β L A1

Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 28 28
Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59
Overall Length D .695 .704 .712 17.65 17.87 18.08
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle Top φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .013 0.23 0.28 0.33
Lead Width B .014 .017 .020 0.36 0.42 0.51
Mold Draft Angle Top α 0 12 15 0 12 15
Mold Draft Angle Bottom β 0 12 15 0 12 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052

 2001 Microchip Technology Inc. Advance Information DS39582A-page 203

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PIC16F87XA
APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE
DIFFERENCES
Version Date Revision Description
The differences between the devices in this data sheet
A 11/2001 Original revision.
are listed in Table B-1.
The devices presented are
enhanced versions of the
PIC16F87X microcontrollers dis-
cussed in the “PIC16F87X Data
Sheet” (DS30292).

TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY

PIC16F873A PIC16F874A PIC16F876A PIC16F877A

FLASH Program Memory 4K 4K 8K 8K

(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Slave Port no yes no yes
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Packages 28-pin PDIP 40-pin PDIP 28-pin PDIP 40-pin PDIP
28-pin SOIC 44-pin PLCC 28-pin SOIC 44-pin PLCC
28-pin SSOP 44-pin QFP 28-pin SSOP 44-pin QFP
28-pin MLF 28-pin MLF

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PIC16F87XA
General Call Address Support ................................... 92 INT Interrupt (RB0/INT). See Interrupt Sources.
Master Mode .............................................................. 93 INTCON ............................................................................. 19
Operation ........................................................... 94 INTCON Register ............................................................... 22
Repeated START Timing ................................... 98 GIE Bit ....................................................................... 22
Master Mode Reception ............................................. 99 INTE Bit ..................................................................... 22
Master Mode START Condition ................................. 97 INTF Bit ..................................................................... 22
Master Mode Transmission ........................................ 99 PEIE Bit ..................................................................... 22
Multi-Master Communication, Bus Collision RBIE Bit ..................................................................... 22
and Arbitration ......................................... 103 RBIF Bit ................................................................22, 42
Multi-Master Mode ................................................... 103 TMR0IE Bit ................................................................ 22
Read/Write Bit Information (R/W Bit) ................... 82, 83 TMR0IF Bit ................................................................. 22
Serial Clock (RC3/SCK/SCL) ..................................... 83 Inter-Integrated Circuit. See I2C.
Slave Mode ................................................................ 82 Internal Reference Signal ................................................ 135
Addressing ......................................................... 82 Internal Sampling Switch (Rss) Impedance ..................... 128
Reception ........................................................... 83 Interrupt Sources ......................................................141, 151
Transmission ...................................................... 83 Interrupt-on-Change (RB7:RB4 ) ............................... 42
SLEEP Operation ..................................................... 103 RB0/INT Pin, External ..................................... 9, 11, 152
STOP Condition Timing ........................................... 102 TMR0 Overflow ........................................................ 152
ICEPIC In-Circuit Emulator .............................................. 166 USART Receive/Transmit Complete ....................... 109
ID Locations ............................................................. 141, 155 Interrupts
In-Circuit Debugger .................................................. 141, 155 Bus Collision Interrupt ................................................ 26
Resources ................................................................ 155 Synchronous Serial Port Interrupt .............................. 24
In-Circuit Serial Programming (ICSP) ...................... 141, 156 Interrupts, Context Saving During .................................... 152
INDF ................................................................................... 19 Interrupts, Enable Bits
INDF Register .........................................................17, 18, 29 Global Interrupt Enable (GIE Bit) ........................22, 151
Indirect Addressing ............................................................ 29 Interrupt-on-Change (RB7:RB4) Enable
FSR Register ............................................................. 14 (RBIE Bit) ............................................22, 152
Instruction Format ............................................................ 157 Peripheral Interrupt Enable (PEIE Bit) ....................... 22
Instruction Set .................................................................. 157 RB0/INT Enable (INTE Bit) ........................................ 22
ADDLW .................................................................... 159 TMR0 Overflow Enable (TMR0IE Bit) ........................ 22
ADDWF .................................................................... 159 Interrupts, Flag Bits
ANDLW .................................................................... 159 Interrupt-on-Change (RB7:RB4) Flag
ANDWF .................................................................... 159 (RBIF Bit) ...................................... 22, 42, 152
BCF .......................................................................... 159 RB0/INT Flag (INTF Bit) ............................................ 22
BSF .......................................................................... 159 TMR0 Overflow Flag (TMR0IF Bit) .....................22, 152
BTFSC ..................................................................... 159
BTFSS ..................................................................... 159 K
CALL ........................................................................ 160 KEELOQ Evaluation and Programming Tools ................... 168
CLRF ........................................................................ 160
CLRW ...................................................................... 160
L
CLRWDT .................................................................. 160 Loading of PC .................................................................... 28
COMF ...................................................................... 160 Low Voltage ICSP Programming ..................................... 156
DECF ....................................................................... 160 Low Voltage In-Circuit Serial Programming ..................... 141
DECFSZ ................................................................... 161
M
GOTO ...................................................................... 161
INCF ......................................................................... 161 Master Clear (MCLR) ........................................................... 8
INCFSZ .................................................................... 161 MCLR Reset, Normal Operation ............... 145, 147, 148
IORLW ..................................................................... 161 MCLR Reset, SLEEP ................................ 145, 147, 148
IORWF ..................................................................... 161 Master Synchronous Serial Port (MSSP).
MOVF ....................................................................... 162 See MSSP.
MOVLW ................................................................... 162 Master Synchronous Serial Port. See MSSP
MOVWF ................................................................... 162 MCLR ............................................................................... 146
NOP ......................................................................... 162 MCLR/VPP ......................................................................... 10
RETFIE .................................................................... 162 Memory Organization ........................................................ 13
RETLW .................................................................... 162 Data EEPROM Memory ............................................. 31
RETURN .................................................................. 163 Data Memory ............................................................. 14
RLF .......................................................................... 163 FLASH Program Memory .......................................... 31
RRF .......................................................................... 163 Program Memory ....................................................... 13
SLEEP ..................................................................... 163 MPLAB C17 and MPLAB C18 C Compilers .................... 165
SUBLW .................................................................... 163 MPLAB ICD In-Circuit Debugger ..................................... 167
SUBWF .................................................................... 163 MPLAB ICE High Performance Universal In-Circuit
SWAPF .................................................................... 164 Emulator with MPLAB IDE ....................................... 166
XORLW .................................................................... 164 MPLAB Integrated Development Environment
XORWF .................................................................... 164 Software .................................................................. 165
Summary Table ........................................................ 158 MPLINK Object Linker/MPLIB Object Librarian ............... 166

 2001 Microchip Technology Inc. Advance Information DS39582A-page 211

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PIC16F87XA
Timing Diagrams .............................................................. 103 SPI Mode Timing (Slave Mode with CKE = 1) ........... 76
A/D Conversion ........................................................ 193 SPI Slave Mode (CKE = 0) ...................................... 187
Acknowledge Sequence .......................................... 102 SPI Slave Mode (CKE = 1) ...................................... 187
Asynchronous Master Transmission ........................ 114 Start-up Timer .......................................................... 182
Asynchronous Master Transmission STOP Condition Receive or Transmit Mode ............ 102
(Back to Back) ......................................... 114 Synchronous Reception (Master Mode, SREN) ...... 122
Asynchronous Reception ......................................... 116 Synchronous Transmission ..................................... 120
Asynchronous Reception with Synchronous Transmission (Through TXEN) .......... 120
Address Byte Frist ................................... 118 Time-out Sequence on Power-up
Asynchronous Reception with (MCLR Not Tied to VDD)
Address Detect ........................................ 118 Case 1 ............................................................. 150
Baud Rate Generator with Clock Arbitration .............. 96 Case 2 ............................................................. 150
BRG Reset Due to SDA Arbitration During Time-out Sequence on Power-up (MCLR Tied to
START Condition ..................................... 105 VDD via RC Network) ............................... 149
Brown-out Reset ...................................................... 182 Timer0 ..................................................................... 183
Bus Collision During a Repeated START Timer1 ..................................................................... 183
Condition (Case 1) ................................... 106 USART Synchronous Receive (Master/Slave) ........ 191
Bus Collision During Repeated START USART Synchronous Transmission
Condition (Case 2) ................................... 106 (Master/Slave) ......................................... 191
Bus Collision During START Condition Wake-up from SLEEP via Interrupt .......................... 155
(SCL = 0) ................................................. 105 Watchdog Timer ...................................................... 182
Bus Collision During START Condition TMR0 ................................................................................. 19
(SDA Only) ............................................... 104 TMR0 Register ................................................................... 17
Bus Collision During STOP Condition TMR1CS bit ....................................................................... 55
(Case 1) ................................................... 107 TMR1H .............................................................................. 19
Bus Collision During STOP Condition TMR1H Register ................................................................ 17
(Case 2) ................................................... 107 TMR1L ............................................................................... 19
Capture/Compare/PWM (CCP1 and CCP2) ............ 184 TMR1L Register ................................................................. 17
CLKOUT and I/O ...................................................... 181 TMR1ON bit ....................................................................... 55
Clock Synchronization ............................................... 89 TMR2 ................................................................................. 19
First START Bit Timing .............................................. 97 TMR2 Register ................................................................... 17
I2C Bus Data ............................................................ 189 TMR2ON bit ....................................................................... 59
I2C Bus START/STOP Bits ...................................... 188 TMRO Register .................................................................. 19
I2C Master Mode (Reception, TOUTPS0 bit ..................................................................... 59
7-bit Address) .......................................... 101 TOUTPS1 bit ..................................................................... 59
I2C Master Mode (Transmission, 7 or TOUTPS2 bit ..................................................................... 59
10-bit Address) ........................................ 100 TOUTPS3 bit ..................................................................... 59
I2C Slave Mode Timing (Transmission, TRISA Register .................................................................. 18
10-bit Address) .......................................... 87 TRISB Register .................................................................. 18
I2C Slave Mode Timing (Transmission, TRISC Register .................................................................. 18
7-bit Address) ............................................ 85 TRISD Register .................................................................. 18
I2C Slave Mode Timing SEN = 1 (Reception, TRISE Register .............................................................18, 47
10-bit Address) .......................................... 91 IBF Bit ........................................................................ 48
I2C Slave Mode Timing with SEN = 0 IBOV Bit ..................................................................... 48
(Reception, 10-bit Address) ....................... 86 OBF Bit ...................................................................... 48
I2C Slave Mode Timing with SEN = 0 PSPMODE Bit ........................................... 46, 47, 48, 49
(Reception, 7-bit Address) ......................... 84 TXREG .............................................................................. 19
I2C Slave Mode Timing with SEN = 1 TXREG Register ................................................................ 17
(Reception, 7-bit Address) ......................... 90 TXSTA Register ................................................................. 18
Parallel Slave Port (PSP) BRGH Bit ................................................................. 109
Read Waveforms ............................................... 50 CSRC Bit ................................................................. 109
Write Waveforms ............................................... 50 SYNC Bit ................................................................. 109
Parallel Slave Port Timing TRMT Bit .................................................................. 109
(PIC16F874A/877A Only) ........................ 185 TX9 Bit ..................................................................... 109
Power-up Timer ....................................................... 182 TX9D Bit .................................................................. 109
Repeat START Condition .......................................... 98 TXEN Bit .................................................................. 109
RESET ..................................................................... 182
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ........................ 92
Slave Synchronization ............................................... 75
Slow Rise Time (MCLR Tied to VDD via
RC Network) ............................................ 150
SPI Master Mode (CKE = 0, SMP = 0) .................... 186
SPI Mode Timing (Master Mode) ............................... 74
SPI Mode Timing (Slave Mode with CKE = 0) ........... 76

 2001 Microchip Technology Inc. Advance Information DS39582A-page 215

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PIC16F87XA
PIC16F87XA PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX XXX
Examples:
Device Temperature Package Pattern a) PIC16F873A - I/P 301 = Industrial temp., PDIP
Range package, normal VDD limits, QTP pattern #301.
b) PIC16LF876A - I/SO = Industrial temp., SOIC
package, Extended VDD limits.
c) PIC16F877A - I/P = Industrial temp., PDIP
Device PIC16F87XA(1), PIC16F87XAT(2); VDD range 4.0V to 5.5V package, 10MHz, normal VDD limits.
PIC16LF87XA(1), PIC16LF87XAT(2 ); VDD range 2.0V to 5.5V

Temperature Range I = -40°C to +85°C (Industrial)

Package ML = MLF (Metal Lead Frame)

PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic DIP
P = PDIP
L = PLCC
Note 1: F = CMOS FLASH
LF = Low Power CMOS FLASH
2: T = in tape and reel - SOIC, PLCC,
TQFP packages only.

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

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 2001 Microchip Technology Inc. Advance Information DS39582A-page 219

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