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Balanced Rectifier Using Antiparallel-Diode

Configuration
Muh-Dey Wei and Renato Negra
Chair of High Frequency Electronics
RWTH Aachen University, 52062 Aachen, Germany

Abstract—A constant input impedance over input power can

be achieved in a typical balanced rectifier but two rectified
output voltages need to be summed up using power management
modules (PMMs). In this paper a balanced rectifier using
an antiparallel-diode configuration is presented. The rectified
output voltage can be acquired directly instead of two separate
nodes. Hence, a PMM can be removed and the efficiency
degradation by the PMM is also eliminated. To retain the
constant input impedance, the effect of changing the polarity
of a diode is studied. A prototype for proof-of-concept is
implemented. Measured S11 is below −23.5 dB from an input
power of −20 dBm to 20 dBm. Measured peak efficiency is
56.8% at 2.24 GHz.
Index Terms—Balanced, Rectifier, Polarity of diode, Energy Fig. 1. Original balanced rectifier [5].
recovering

I. I NTRODUCTION
Terminations are used in many RF circuits such as power
combiners and rat-race couplers to fulfill the matching
condition. Using an RF rectifier to replace the termination
is one of the methods to recycle the energy wasted in
the termination [1]. One important requirement for the RF
rectifier is that the input impedance (e.g. 50 Ω) should be
as constant as possible over the input power to imitate the
behaviour of the termination. However, a nonlinear device (a)
(e.g. Schottky diodes) used in a rectifier has a significant
impedance variation over input power. For example the
reflection coefficient (Γ) of a Schottky diode may vary from
0.1 to 0.9 over input power at a single frequency.
Resistance compression networks (RCNs) have been
presented in [2], [3], [4] to relief this impedance variation.
A rectifier employing a balanced configuration, as shown (b)
in Fig. 1, is demonstrated in [5] to reach good reflection
coefficient over a very wide input power. The dc output Fig. 2. (a) Proposed balanced rectifier using antiparallel-diode configuration
and (b) the class F −1 matching network of the subrectifier.
voltages, Vout1 and Vout2 , are acquired from the two identical
subrectifiers, Ry1 and Ry2 .
If each rectifier is separate, output voltage can be directly a balanced rectifier using the antiparallel-diode configuration
summed up in series configuration. In balanced structure is proposed to overcome the voltage summing problem.
voltage summing, however, is not possible due to the common
ground of the two subrectifiers i.e. the dc output voltages of II. C IRCUIT D ESIGN
the subrectifiers have the same ground. Therefore, a summing Fig. 2(a) shows the balanced rectifier using the proposed
method is necessary. One method suggested in [5] is to use antiparallel-diode configuration. It consists of a 3 dB
the power management modules (PMMs) to combine the dc branch-line coupler (BLC) and two subrectifiers. Each
output voltages [6] for a typical balanced rectifier. Having subrectifier is composed of a matching network, a diode,
more PMMs increases the production cost and moreover, the a bypass capacitor and a dc load. Both of the subrectifiers
PMM has its conversion efficiency resulting in reduction of are the identical expect the polarity of the diode is reversed
the overall efficiency of the balanced rectifier. In this paper, in one, as illustrated in Fig. 2(a). Since D1 and D2 are in

‹,((( 
 (a) (a)

(b) (b)

Fig. 3. Investigations of the polarity of the diode: (a) S11 over input power Fig. 4. Investigations of the polarity of the diode: (a) S11 over frequency
and (b) efficiency versus input power. and (b) efficiency versus frequency.

antiparallel, D1 sources the dc current to the load, RL1 , and subrectifiers over the input power as well as the operation
D2 sinks the dc current from the load, RL2 , resulting in a frequency. When Γ1 and Γ2 behave like each other, a constant
positive and a negative output voltage across the dc load, impedance is achieved according to the concept of balanced
respectively. Therefore, the rectified dc output voltage can circuits [10].
be taken differentially [7]. The output node of one of the
subrectifiers is treated as the dc ground which is different If the polarity of the diode changes, the characteristics of
from the RF ground. the reflection coefficient actually do not change. Fig. 3(a) and
Fig. 3(b) show the simulated S11 and normalized efficiencies
Broadcom® HSMS-2820 Schottky diodes with SOT-23
over the input power for two subrectifiers at 2.4 GHz. As
package are used to implement the prototype as an example.
expected, Γ1 and Γ2 as well as the efficiency are the same
A class F −1 matching network, as plotted in Fig. 2(b)
over the input power. The simulations are carried out in
is employed here for high efficiency. The impedances and
Keysight® ADS with the diode model provided by Broadcom.
electric lengths of TL1 , TL2 , TL3 , and TL4 are 16 Ω/119◦ ,
50 Ω/90◦ , 50 Ω/45◦ and 50 Ω/30◦ , respectively. The short Fig. 4(a) and Fig. 4(b) plot the simulated S11 and
stub, TL2 , supports the dc current path. A 4/λ open stub normalized efficiencies over the operation frequency at an
and a 8.2 pF capacitor from ATC are placed for AC ground. input power of 15.9 dBm. The behaviour of the subrectifiers
The dc load, RL , is 1 kΩ for each subrectifier and RT is over the operation frequency are identical.
an external 50 Ω termination. Note that any type of rectifier According to these investigations, the reflection coefficients
such as class E [8] or class F [9] can be used in the proposed and efficiencies are unchanged regardless of the polarity of
balanced structure. the diode implying that using an antiparallel-diode connection
To maintain a constant input impedance in the balanced in a balanced rectifier will still maintain a constant input
configuration, it is important to investigate the behaviour impedance. Besides, the overall efficiency will not be
of the input reflection coefficients, Γ1 and Γ2 , of the two degraded by an additional PMM for voltage summing.


 TABLE I
D IMENSION OF THE PROTOTYPE
Element Width (mm) Length (mm)
TL1 10.06 27.6
TL2 1.1 13.3
TL3 1.1 6.8
TL4 1.36 4.96
TL5 1.1 13.6
TL6 1.82 18.8
Fig. 5. Photograph of the prototype of the balanced rectifier.
TL7 1.1 18.2

III. I MPLEMENTATION AND M EASUREMENT

The prototype of the balanced rectifier is implemented on
a Rogers® RO4350 substrate with a thickness of 0.5 mm and
copper cladding of 17 μm. Keysight® ADS Momentum is
used for EM simulation of the final layout. Fig. 5 shows
the prototype of the rectifier and the actual dimensions are
summarised in Table I.
The input reflection coefficients are measured using a
Rohde & Schwarz® (R&S) ZVA under a source power of
+18 dBm. Fig. 6 shows the measured input reflection
coefficients of the two subrectifiers and the balanced rectifier.
The centre frequency of each subrectifier is shifted to
2.24 GHz. The discrepancy may be caused by the inaccurate
diode model Nevertheless, the two subrectifiers provide
similar input reflection coefficients resulting in good reflection
coefficient for the balanced rectifier. At 2.24 GHz the phase
difference of 1◦ in the BLC is not significant and therefore, Fig. 6. Measured S11 : subrectifier with A-C diode connection (dashed), with
C-A diode connection (dot) and the balanced rectifier (solid)
it is still acceptable to maintain the balanced concept.
Fig. 7 shows measured S11 versus input power for the
two subrectifiers and the balanced rectifier at 2.24 GHz. As
expected, measured S11 of each subrectifier is poor due to
its high impedance for the input power of less than 0 dBm.
Within the balanced structure measured S11 is better than
−23.5 dB which is suitable for energy recovering.
Fig. 8 illustrates the efficiency measurement setup. An
input signal is generated from an R&S SMBV100A signal
generator and the output voltage is acquired by a Yokogawa®
multimeter. The output voltage in the prototype is captured
directly compared to the original balanced rectifier [5]. The
measured efficiency at 2.24 GHz is plotted in Fig. 9. As can
be seen the efficiency of the two subrectifiers are close to each
other. Peak efficiencies of 63.7 % and 64.3 % are achieved at
an input power of 21 dBm in the subrectifier with A-C and
C-A diode connection, respectively. Peak efficiency of the
balanced rectifier is 56.8 %.
Since the prototype is a proof-of-concept, the subrectifiers Fig. 7. Measured S11 versus input power at 2.24 GHz: subrectifier with
A-C diode connection (dashed), with C-A diode connection (dot) and the
are connected to the 2.4 GHz BLC through SMA connectors. balanced rectifier (solid)
The interconnections between the branch-line coupler and the
subrectifiers may cause the efficiency degradation of around
7 %. When the BLC and the subrectifiers are implemented
on the same PCB, the losses of the SMA connectors can be is at 2.4 GHz. The mismatch leads to slightly higher insertion
eliminated. Besides, the subrectifiers have a frequency shift of loss from the coupler compared to the centre frequency of
around 160 MHz. The centre frequency of the BLC however 2.4 GHz.


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Fig. 9. Measured efficiency: subrectifier with A-C diode connection (o),

with C-A diode connection (+), balanced rectifier (X) and simulation of the
balanced rectifier(−−)

IV. C ONCLUSION
The proposed balanced rectifier takes advantage of the
anti-paralle-diode configuration. Thus, the rectified dc output
voltage can be acquired directly. The voltage summing
problem in the typical balanced rectifier can be solved.
The constant input reflection coefficient of the proposed
rectifier is kept because the impedance characteristics over
input power as well as operation frequency are unchanged
regardless of the polarity of the diode. The prototype has
been implemented and measured as a proof-of-concept. The
antiparallel shunt-diode connection also can be used instead
of a series connection in the prototype.
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