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Assignment - 1 Basics of VLSI: Submitted By: Name - Roll no.-M.Tech VLSI Systems

The document summarizes an experiment on analyzing the DC characteristics of a CMOS inverter. The objectives are to obtain the DC transfer characteristics, observe how they change with different PMOS widths, and determine the transistor sizes needed for equal rise and fall times. The tools used are Cadence Analog Virtuoso simulator and a UMC 180nm CMOS technology. The DC characteristics are obtained by sweeping the input voltage and measuring the output. Parametric sweeps are done by varying the PMOS width, showing its effect on the characteristics. Finally, transistor widths of Wp=6.344um and Wn=2um are determined to give equal rise and fall times of 157.75ps.

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Paramesh Waran
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96 views5 pages

Assignment - 1 Basics of VLSI: Submitted By: Name - Roll no.-M.Tech VLSI Systems

The document summarizes an experiment on analyzing the DC characteristics of a CMOS inverter. The objectives are to obtain the DC transfer characteristics, observe how they change with different PMOS widths, and determine the transistor sizes needed for equal rise and fall times. The tools used are Cadence Analog Virtuoso simulator and a UMC 180nm CMOS technology. The DC characteristics are obtained by sweeping the input voltage and measuring the output. Parametric sweeps are done by varying the PMOS width, showing its effect on the characteristics. Finally, transistor widths of Wp=6.344um and Wn=2um are determined to give equal rise and fall times of 157.75ps.

Uploaded by

Paramesh Waran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Assignment -1

Basics of VLSI

Submitted by:
Name –
Roll no.-
M.Tech VLSI systems
Parametric Analysis of CMOS Inverter
OBJECTIVE :
1. To obtain DC characteristics.
2. To observe DC characteristics for various widths of PMOS.
3. Size of transistor to get equal rise and fall time.
TOOLS AND SOFTWARE USED:
1. Cadence analog virtuoso simulator
2. UMC’s CMOS 180 nm technology
1. To obtain DC characteristics:
The input voltage Vin is a pulse with pulse amplitude 1.8V and pulse width 5ns with
period 10ns is applied .The supply voltage Vdc is 1.8 V.
The structure of the CMOS inverter is given below:
Figure 1: CMOS inverter Schematic

Figure 2: DC Transfer characteristics


The above figure shows the DC transfer characteristics of CMOS inverter where the
input voltage Vin is varied from 0 to 1.8V and Vdd is at 1.8V
The widths of transistors M1 and M2 are fixed as Wn=2um and Wp=4um
respectively.
The output Vout is taken across the 1pf capacitor.
2. Parametric analysis of CMOS inverter
The simulation is run by varying βp values from 1μm to 4μm.

Figure 3: Parametric analysis of CMOS inverter

The simulation is run for different values of beta p from 2um to 6um with step size
2um i.e. beta ratio<1(red), beta ratio=1(yellow), and beta ratio>1(green).
3. Size of transistor to get equal rise and fall time
Rise time is calculated by considering initial value 0V and final value 1.8V,
between 10% to 90% of the waveform and similarly the fall time is calculated by
considering initial value 1.8V and final value 0V, between 90% to 10% of the
waveform. The rise time equals to fall time i.e. tr=tf=157.75ps at Wp =6.344 um
and Wn= 2um, aprox. βp/ βn=3.172.

Figure 4: tr and tf for inverter.

INPUT AND OUTPUT WAVEFORM

Figure 5: Input and output waveform.

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