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Parul Institute of Engineering and Technology, Limda Electronics & Communication Engineering Department

This document contains code for modeling half adder, full adder, and half subtractor circuits using a data flow style. For each circuit, it defines the entity with input and output ports, then uses a concurrent architecture with signal assignments to model the logic functions for the sum and carry outputs based on the input values.

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37 views3 pages

Parul Institute of Engineering and Technology, Limda Electronics & Communication Engineering Department

This document contains code for modeling half adder, full adder, and half subtractor circuits using a data flow style. For each circuit, it defines the entity with input and output ports, then uses a concurrent architecture with signal assignments to model the logic functions for the sum and carry outputs based on the input values.

Uploaded by

abhishek33335
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PARUL INSTITUTE OF ENGINEERING AND TECHNOLOGY, LIMDA

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Class : 6th Sem Subject : VLSI


Practical No. : 4(a), (b), (c) Subject Code : 161004

4(a) Data flow modeling and simulation of half Adder.

-- Company:
-- Engineer:
--
-- Create Date: -- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ha_adder is -- Entity is declared here which defines input and output
ports
-- of digital circuits
port ( a,b:in bit; sum, carry:out bit);
end ha_adder;

architecture concur of ha_adder is


begin -- concurrent statements starts from here
sum <= a xor b;
carry <= a and b;
end concur;
4(b) Data flow modeling and simulation of full adder.

-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Data flow style of modelling is normally used to model COMBINATIONA circuits


entity full_adder is
port ( a,b,cin:in bit; sum, carry:out bit);
end full_adder;
architecture concur of full_adder is
signal s1: bit; -- this signal is internal to entity.
begin -- concurrent statements starts from here
s1 <= a xor b;
sum <= s1 xor cin;
carry <= (a and b) or (a and cin) or ( b and cin);
end concur;
4 (c) Data flow modeling and simulation of half subtractor.

-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Data flow style of modelling is normally used to model COMBINATIONA circuits

entity half_sub is
port( a,b:in bit; result,borrow:out bit);
end half_sub;
-- input node a is MSB and b is LSB

architecture concur of half_sub is


signal s:bit;
begin
-- concurrent statements starts from here
result <= a xor b;
s <= not a;
borrow <= s and b;
end concur;

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