Verilog Code For CLK
Verilog Code For CLK
//Execute the always blocks when the Clock or reset inputs are
//changing from 0 to 1(positive edge of the signal)
always @(posedge(Clk_1sec) or posedge(reset))
begin
if(reset == 1'b1) begin //check for active high reset.
//reset the time.
seconds = 0;
minutes = 0;
hours = 0; end
else if(Clk_1sec == 1'b1) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
if(seconds == 60) begin //check for max value of sec
seconds = 0; //reset seconds
minutes = minutes + 1; //increment minutes
if(minutes == 60) begin //check for max value of min
minutes = 0; //reset minutes
hours = hours + 1; //increment hours
if(hours == 24) begin //check for max value of hours
hours = 0; //reset hours
end
end
end
end
end
endmodule
module tb_clock;
// Inputs
reg Clk_1sec;
reg reset;
// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
Digital_Clock uut (
.Clk_1sec(Clk_1sec),
.reset(reset),
.seconds(seconds),
.minutes(minutes),
.hours(hours)
);
initial begin
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
end
endmodule