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Verilog Code For CLK

This document describes a digital clock module that takes in a 1Hz clock signal and active high reset signal as inputs. It outputs the current seconds, minutes, and hours as 6-bit, 6-bit, and 5-bit signals respectively. The module contains registers that increment the time values on each rising edge of the clock, resetting seconds to 0 after 60 seconds, minutes after 60 minutes, and hours after 24 hours. A testbench is provided that generates a toggling 1Hz clock and applies a reset pulse to verify the clock module functionality.

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131 views2 pages

Verilog Code For CLK

This document describes a digital clock module that takes in a 1Hz clock signal and active high reset signal as inputs. It outputs the current seconds, minutes, and hours as 6-bit, 6-bit, and 5-bit signals respectively. The module contains registers that increment the time values on each rising edge of the clock, resetting seconds to 0 after 60 seconds, minutes after 60 minutes, and hours after 24 hours. A testbench is provided that generates a toggling 1Hz clock and applies a reset pulse to verify the clock module functionality.

Uploaded by

SHREE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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module Digital_Clock(

Clk_1sec, //Clock with 1 Hz frequency


reset, //active high reset
seconds,
minutes,
hours);

//What are the Inputs?


input Clk_1sec;
input reset;
//What are the Outputs?
output [5:0] seconds;
output [5:0] minutes;
output [4:0] hours;
//Internal variables.
reg [5:0] seconds;
reg [5:0] minutes;
reg [4:0] hours;

//Execute the always blocks when the Clock or reset inputs are
//changing from 0 to 1(positive edge of the signal)
always @(posedge(Clk_1sec) or posedge(reset))
begin
if(reset == 1'b1) begin //check for active high reset.
//reset the time.
seconds = 0;
minutes = 0;
hours = 0; end
else if(Clk_1sec == 1'b1) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
if(seconds == 60) begin //check for max value of sec
seconds = 0; //reset seconds
minutes = minutes + 1; //increment minutes
if(minutes == 60) begin //check for max value of min
minutes = 0; //reset minutes
hours = hours + 1; //increment hours
if(hours == 24) begin //check for max value of hours
hours = 0; //reset hours
end
end
end
end
end

endmodule

Testbench for Digital Clock:

module tb_clock;

// Inputs
reg Clk_1sec;
reg reset;

// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
// Instantiate the Unit Under Test (UUT)
Digital_Clock uut (
.Clk_1sec(Clk_1sec),
.reset(reset),
.seconds(seconds),
.minutes(minutes),
.hours(hours)
);

//Generating the Clock with `1 Hz frequency


initial Clk_1sec = 0;
always #50000000 Clk_1sec = ~Clk_1sec; //Every 0.5 sec toggle the clock.

initial begin
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
end

endmodule

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