Introduction to Digital Design Using Digilent FPGA Boards — Block Diagram / VHDL Examples Richard E. Haskell Darrin M. Hanna ukland University, Rochester, Michigan LBE Books Rochester Hill, MICopyright 2009 by LBE Books, LLC. All rights reserved, ISBN 978.0-9801337-6.9, Second Printing Published by LBE Books, LLC 1202 Walton Boulevard Suite 214 Rochester Hills, MI 48307 ‘www.lbebooks.comPreface ‘A major revolution in digital design has taken place over the past decade. Field programmable gate arrays (FPGAs) can now contain over a million equivalent logic gates and tens of thousands of flip-flops. This means that itis nat possible to use traditional methods of logic design involving the drawing of logic diagrams ‘when the digital circuit may contain thousands of gates, ‘The reality is that today digital systems are designed by writing software in the form of hardware description languages (HDLs). The most common HDLs used today are VHDL. and Verilog. Both are in widespread use. When using these hardware description languages the designer typically describes the behavior of the logic cireit rather than writing traditional Boolean logie equations. Computer-aided design tools are used to both simudate the VHDL of Verilog design and to spmshesize the design to actual hardware. This book assumes no previous knowledge of digital design. We use 30 examples to show you how to get started designing digital cireits that you can implement on a Xilinx Spartan3E FPGA using either the Digilent BASYS™ system board that can be purchased from yovwdigilenting.com for $59 or the Digilent Nexys-2 board that costs $99. We will use Active-HDL from Aldee to design, simulate, synthesize, and implement our digital designs. A free student edition of Active-HDL is available from Aldec, Inc. (ww.aldee.com), To synthesize your designs to a Spartan3E FPGA you will need to download the free ISE WebPACK from Xilinx, Ine. (wsw.xilins.com). The Xilinx synthesis tools are called from. within the Aldec Active-HDL integrated GUI. We will use the ExPort utility to download your synthesized design to the Spartan3E FPGA. ExPor is part of the Adept software suite that you can dowmload free from Digilent, Inc (wu w.tigilemtine.com). A more complete book called Digital Design Using Digilent FPGA Boards ~ VHDL / Active-HDL Edition is also available from Digilent oF LBE Books (yww.lbebooks.com). This more comprehensive book contains over 75 examples including examples of using the VGA and PS/2 por Similar books that use Verilog ae also available from Digilent or LBE Books. Many colleagues and students have influenced the development of this book. Their stimulating discussions, probing questions, and ital comments are really appreciated Richard E. Haskell Darrin M. HannaIntroduction to Digital Design Using Digilent FPGA Boards — Block Diagram / VHDL Examples Table of Contents Introduction ~ Digital Design Using FPGAs Example 1 ~ Switches and LEDs Example 2—2-Input Gates Example 3 ~ Multiple-Input Gates Example 4 ~ Equality Detector Example 5 ~2-o-I Multiplexer Example 6 — Quad 2-1o-1 Multiplexer Example 7 —4-to-1 Multiplexer Example 8 ~ Clocks and Counters Example 9 ~ 7-Segment Decoder Example 10 ~ 7-Sepment Displays: x7seg and x7segb Example 11 ~2's Complement 4-Bit Saturator Example 12 —Full Adder Example 13 —4-Bit Adder Example 14 —-Bit Adder Example 15 — 0-Bit Comparator Example 16 — Edge-Triggered D Example 17 —D Flip-Flops in VDL. Example 18 ~ Divide-by-2 Counter Example 19 Registers Example 20 ~ N-Bit Register in VHDL Example 21 ~ Shift Registers Example 22 — Ring Counters Example 23 — Johnson Counters Example 24 —Debounce Pushbuttons Example 25 ~ Clock Pulse Example 26 ~ Arbitrary Waveform Example 27 ~ Pulse-Width Modulation (PWM) Example 28 — Controlling the Postion of a Servo Example 29 — Scrolling the 7-Segment Display Example 30 — Fibonacei SequenceAppendix A — Aldee Active-HDL Tutorial Part 1: Project Setup Part 2: Design Entry ~sw2led.bde Part 3: Synthesis and Implementation Par 4: Program FPGA Board Part 5: Design Entry ~ gates2.bde Part 6: Simulation Part 7: Design Entry ~ HDE Part 8: Simulation ~ gates? Appendix B — Number Systems B.1 Counting in Binary and Hexadecimal B.2 Positional Notation 3 Fractional Numbers BA Number System Conversions BS Negative Numbers Appendix C — Basic Logie Gates C.1 Truth Tables and Logie Equations C2 Positive and Negative Logie: De Morgan's Theorem C3 Sum of Produets Design C4 Product of Sums Design Appendix D — Boolean Algebra and Logic Equations D.1 Boolean Theorems D2 Kamaugh Maps Appendix E ~ VHDL Quick Reference Guide 123 123 27 130 134 136 142 146 149 1st 154 158 159 159 167 167 aN 133 1m 176 176 182 189Inosuction 1 Introduction Digital Design Using FPGAs The fist integrated circuits that were developed in the early 1960s contained less that 100 transistors on a chip and are called small-scale integrated (SSI) circuits. Medium-scale integrated (MSI) circuits, developed in the late 1960s, contain up to several hundreds of transistors on a chip. By the mid 1970s large-scale integrated (LSI) cireuits containing several thousands of transistors had been developed. Very-large-scale integrated (VLSI) cireuits containing over 100,000 transistors had been developed by the carly 1980s, This trend has continued to the present day with 1,000,000 transistors on a chip by the late 1980s, 10,000,000 transistors on a chip by the mid-1990s, over 100,000,000 transistors by 2004, and up to 1,000,000,000 transistors on a chip today. This exponential growth in the amount of digital logic that can be packed into a single chip has produced serious problems for the digital designer. How can an engineer, of even a team of engineers, design a digital logic cireuit that will end up containing millions of transistors? In Appendix C we show that any digital log circuit ean be made from only three types of basic gates: AND, OR, and NOT. In fact, we will see that any digital logic circuit can be made using only NAND gates (or only NOR gates), where each NAND oF NOR gate contains four transistors. These basic gates were provided in SSI chips using various technologies, the most popular being transistor-ransistor logic (TTL). These TTL chips were the mainstay of digital design throughout the 1960s and 1970s. Many MSI TTL chips became available for performing all types of digital logie functions such ts decoders, adders, multiplexers, comparators, and many others. By the 1980s thousands of gates could fit on a single chip. Thus, several diferent varieties of programmable logic devices (PLDs) were developed in which arrays containing large numbers of AND, OR, and NOT gates were arranged in a single chip without any predetermined function. Rather, the designer could design any type of digital circuit and implement it by connecting the intemal gates in partculat Way. This is usually done by opening up fuse links within the chip using computer-aided tools, Eventually the equivalent of many PLDs on a single chip led to complex programmable logie devices (CPLDs). Field Programmable Gate Arrays (FPGAs) A completely different architecture was introduced in the mid-1980"s that uses RAM-based lookup tables instead of AND-OR gates to implement combinational loge, ‘These devices are called field programmable gate arrays (FPGAs). The device consists of an array of configurable logie blocks (CLBs) surrounded by an array of VO blocks, ‘The Spartan-3E from Xilinx also contains some blocks of RAM, 18 x 18 multipliers, as well as Digital Clock Manager (DCM) blocks. These DCMs are used to eliminate clock distribution delay and can also increase or decrease the frequency of the clock,2 Introduction Each CLB in the Spartan-3E FPGA contains four slices, each of which eontains two 16 x | RAM look-up tables (LUTS), which can implement any combinational logic function of four variables. In addition t two look-up tables, each slice contains two D flip-flops which act as storage devices for bits. The basic architecture of @ Spartan-3E FPGA is shown in Fig. 1. Figure 1 Architecture of a Spartan FPGA The BASYS board fom Digilent contains a Xilinx Spartan3E-100 TQ144 FPGA, ‘This chip contains 240 CLBs arranged as 22 rows and 16 columns. There are therefore 960 slices with a total of 1,920 LUTS and flip-flops. This part also contains 73,728 of block RAM. Half ofthe LUTs on the chip can be used for a maximum of 15,360 bi of distributed RAM. By contrast the Nexys-2 board from Digilent contains a Xilinx Spartan3E-500 FG320 FPGA. This chip contains 1,164 CLBs arranged as 46 rows and 34 columns, ‘There are therefore 4,656 slices with & total of 9,312 LUTS and fip-lops. This part also contains 368,640 bits of block RAM. Half of the LUTs on the chip ean be used for a ‘maximum of 74,752 bits of distributed RAM, In general, FPGAs ean implement much larger digital systems than CPLDs as illustrated in Table 1. The column labeled No. of Gates is really equivalent gates as we have seen that FPGAS really don’t have AND and OR gates, but rather just RAM look-up tables. (Fach slice does include two AND gates and two XOR gates as part of carry and arithmetic logic used when implementing arithmetic functions including addition andIntroduction a multiplication.) Note from Table | that FPGAs can have the equivalent of millions of gates and tens of thousands of flip-flops, ‘Table 1 Comparing Xiline CPLDs and FPGAS Wing Pant | No.of Gates | No. of YOs | No.of CLBs | No, of Flip-flops | Block RAM (bits) PLDs 500 family ‘ao -6.400| 34-182 3-288 i FPGAS i ‘Spartan | 6000-0000 | _77=70a] 00 — 7ea| 360-2018 ‘Spartanii_|16,000—200,000| 98284) 96—1,176| _642—5.558| 16.384 57.344 ‘Spartan NE | 25,000~ 600,000 182-514] 384 3.456 | 2,082 ~ 16,368 32.768 —204 912, ‘Spartans | 60.000 ~6,000,000| 12474) 192—8,320| 2.280 71.264 73,728 - 1,916,928 Spartan _| 700,000 = 1,600,000 | 108-376 | 240-3688] _1,920-29,506| 73,728 - 653.552 Vitex | 57,908 —1,124,022| 180 512) 384— 6,146 | 2.076~26.112| 52.768— 131,072 Vitex | 71,693 4,074,387 | 176 606] s8é 16.224 | 1,888—65,50¢ 65.535 251,086 ‘itexsii | 40,960 ~ 8,388,608 | —65~1,108] 64 11,606| 1,040 - 09,652 173,728 - 3,098 576. Modern Design of Digital Systems ‘The waditional way of designing digital cireuits is to draw logie diagrams containing SSI gates and MSI logic functions. However, by the late 1980s and early 1990s such a process was becoming problematic. How ean you draw schematic diagrams containing hundreds of thousands er millions of gales? As programmable logic devices replaced TTL chips in new designs a new approach to digital design became necessary Computer-aided tools are essential to designing digital cieuits today. What has become clear over the last decade is that today’s digital engineer designs digital systems by ‘writing software! This is @ major paradigm shift from the traditional method of designing digital systems. Many of the traditional design methods that were important when using ‘TTL chips are less important when designing for programmable logic devices. Today digital designers use hardware description languages (HDLS) to design digital systems. "The most widely used HDLs are VHDL and Verilog. Both of these hardware description languages allow the user to design digital systems by writing a program that describes the behavior ofthe digital circuit. The program can then be used to both simulate the operation of the cicuit and synrhesize an actual implementation of the circuit in a CPLD, an FPGA, or an application specific integrated circuit (ASIC), ‘Another recent tren is to design digital circuits using block diagrams or graphic symbols that represent higher-level design constructs. These block diagrams ean then be compiled to produce Verilog or VHDL code. We will illustrate this method in this book. We will use Active-HDL from Aldec for designing our digital circuits. This integrated too! allows you to enter your design using either a block diagram editor (BDE) or by writing Verilog or VHDL code using the hardware description editor (HDE). Once your hardware has been described you ean use the funetional simulator to produce ‘waveforms that will verify your design. This hardware description can then be synthesized to logic equations and implemented or mapped to the FPGA architecture,4 Introduction We include a torial for using Active-HDL in Appendix A. A fee student version of Active HDL is available on thee website! We will use Xilin ISE for synhesizng our VHDL designs. You ean download a free version of ISE"™ WebPACK™ from the Xilinx website? This WebPACK™ synthesis tool ean be run from within the Aldec Active-HDL development environment as shown in the tutorial in Appendix A. The implementation process creates a .bir file that is downloaded to a Xilinx FPGA on the BASYS board or Nexys-2 shown in Fig. 2. The BASYS boatd is available to students for $59 from Digilent, Inc3 This board includes a 100k-gate equivalent Xilinx Spartan3E FPGA (250k-gate capacity is also availabe), 8 slide switehes, 4 pushbutton switches, 8 LEDs, and four 7-segment displays, The frequency of an on-board clock ean be set to 25 MHz, 50 MHz, or 100 MHz using a jumper. These are connectors that allow the board to be interfaced to external circuits. The board also includes a VGA port and a PS2 port. The use of these ports are described in a different book! Another more advanced board, the Nexys-2 board, is also available to students for $99 from Digilent. ‘The Nexys-2 board is similar to the BASYS board except that it contains a 500k- or 1200k-gate equivalent Spartan 3E FPGA, a Hirose FX2 interface for additional add-on component boards, 16 MB of cellular RAM, 16 MB of flash memory, a $0 MHz clock and a socket for 2 second oscillator. The Nexys-2 is ideally suited for embedded processors, Al of the examples in this book can be used on both the BASYS board and the Nexys-2 board. The only difference is that you would use the file busys2.uef to define the pinouts on the BASYS board and you would use the file nexps2.uef to define the pinouts on the Nexys-2 board. Both of these files are available to download fom wwuulbebooks.com, Table 2 shows the jumper settings you would use on the two boards. @ © Figuee 2 (2) BASYS boar (b) Nexys-2 Board 1 pw ade comiedvetion! 2hupstowilinecom 3 hp iiletine com 4 Digi Design Ung Diglon FPGA Boards ~ VHDL /Active-HDL Editon, available fiom srw bebooks.com.Introduction 5 ‘Tablo 1.2 Board Jumper Settings BASYS Board Nexs-2 Board ‘Sate IPS ariper to JTAG Salthe POWER SELECT jumper to USS Remove the JP4 jumper se1GHS SOMA | Sethe MODE jumperto JTAG dock VHDL. ‘VHDL is based on the Ada software programming language but itis not Ada nor is ita software programming language. VHDL is a hardware description language that is designed to model digital logic circuits. It simply has syntax similar to the Ada programming language but the way it behaves is different. In this book you will learn ‘VHDL by studying the examples we use to deseribe digital logic and then doing some of the VHDL problems at the end ofeach chapter. In this book we begin by using the Active-HDL block diagram editor to draw logic cireuits using basic gates. When you compile these block diagrams Active-HDL. will generate the corresponding VHDL code. The block diagram representing your logic circuit can then be used as a module in a higher-level digital design. This higher-level, design can then be compiled to produce its corresponding VHDL code. This hierachical block diagram editor will make it easy to design top-level design. Sometimes it will be easier to design a digital module by waiting @ VHDL. program directly rather than drawing it using gates. When you do this you ean still use the block diagram for this module in higher-level designs. We will illustrate this process in many of our examples. Just like any programming language, you can only lear VHDL by actually \writing VHDL programs and simulating the designs using a VHDL simulator that will, display the waveforms of the signals in your design. This is a good way to learn not only VEDI but digital logic as wel A companion book® that uses Verilog instead of VHDL is available from swune.digilentine.com or wwwlbebooks.com. More comprehensive Verilog and VDL. books are also available.” 5 inroduction to Digital Desig Usa Dien FPGA Boards ~ Blok Diagram Verlog Examples { Digital Design Using Digit FPGA Board - Verifog/ Atve-HDL Ealion, LBE Books, 2008, 7 Digit Design Using Digien FPGA Boards - VHDL etive-HDL Editon, LBE Books, 20096 Example 1 Example 1 Switches and LEDs In this example we will show the basic structure of a VHDL program and how to ‘write logie equations for 2-input gates. Example 1a will show the simulation results using Adee Active-HDL and Example 1b will show how to synthesize the program to a Xilinx FPGA on the BASYS or Nexys-2 board. Prerequisite knowledge: ‘None ‘Learned in this Example: Use of Aldce Active-HDL ~ Appendix A 1.1 Slide Switches The side siches on te BASYS and Nayea banat coaecnd Hee e 23V0— Tee imghs neha re 7 The va of 87 KD on te DASYS tod 1k aw Im 1080 one expe? tou, When be se tune FCA nrede topes Thee iessich Rupiisumeset33 gen tek mch emecen an! the np) oe FPGA ed wae There are eight slide switches on the BASYS and Nexys-2 boards, The eight pin numbers on the FPGA corresponding to the eight slide switches are given in @ «ef file ‘The file basys2.uof shown in Listing 1.1 defines the pin numbers for all VO on the BASYS board. Note that we have named the slide switches sw(), 1 = 0:7, which correspond to the switch labels on the board, We will always name the slide switehes ‘sw(i) in our top-level designs so that we can use the basys2.ucf file without change. ‘Because the pin numbers on the Nexys-2 board are different from those on the BASYS board we will use a different file called nexys2.uef to define the pin numbers on the Nexys-2 board. The names of the 1/O ports, however, will be the same for both boards, ‘Therefore, all of the examples inthis book can be wed with either board by simply using the proper .ucf file when implementing the design. Both of these .ucf files can be downloaded from ww Jbehooks com, 4.2 LEDs A Light emitting diode (LED) emits light when current flows through it in the re direction as shown in Fig. 1.2. Current flows through the LED when the voltage fon the anode side (the wide side of the black triangle) is made higher than the voltage on‘Switches end LEDS 7 the cathode side (the straight line connected to the apex of the black triangle). When ‘current flows through @ lighted LED the forward voltage across the LED is typically between +1.5 and +2.0 volts. If voltage 72 in Fig. 1.2 is les than or equal to voltage V2 then no current can flow through the LED and therefore no light will be emitted. If voltage 2 is greater than voltage /T then current will low through the resistor R and the LED. The resistor is used to limit the amount of current that flows through the LED. ‘Typical currents needed to ight LEDs range from 2 to 15 milliamps. NER slacose er slacise 4 pin assignnent for slide euieches NET towe?s" Loe = NET “wea! MEP "ewes" ries XeD oc > psa # Pin assignment for clock er tmelke Loe = "p54"3 Example t ‘There are two different ways that an VO pogurert pong pin of an FPGA can be used to umn on an LED. yz yyy“ vi sve ‘The first is to connect the FPGA pin to V2 in Fig. ® Leb 1.2and t connect V7 to ground, Bringing the pin (V2) igh will then turn on the LED. To turn off the LED the output pin would be brought lov. cunent po This isthe method used for the LEDs ld(7)~ ld{0) SUT on the BASYS and Nexys-2 boards ve 9} ive The second method is to connect the Ro uD FPGA pin to V7 in Fig. 12 and t0 connect ¥210 figure 1.2 Taming onan LED 8 constant voltage. Bringing the pin (7) low will then turn on the LED. To turn off the LED the output pin would be brought high. ‘This voltage should be equal to 72 to make sure ‘no current flows through the LED, This scond method is the method used for the 7- segment displays on the BASYS and Nexys-2 boards, Examples 9 and 10 will show how to display hex digits on the 7-segment displays. 1.3 Connecting the Switches to the LEDs Part 1 of the tutorial in Appendix A shows how to connect inp ishcrathe bea EDe ag check Gee eee a at Stan edo (ODE) im Acie HDL The eat shown rei, i) Figure 1.3 Connecting the eight switches tothe eight LEDs‘Switches and LEDS ° Compiling the file sw2led.bde generates the VHDL file sw2led.vid shown in Listing 1.2. Alternatively, by selecting the hardware description editor (HDE) the entity and architecture declarations are automatically generated but you will need to write your ‘own assignment statements. This can lead to the simpler VHDL program shown in Listing 1.3 where we can write a single assignment statement using the assignment ‘operator, ©, f0 replace the two intermediate assignment statements in Listing 1.2. It is ‘unnecessary to define the intermediate bus BUS23(7:0). Listing 1.2 821 Library EEE. taee ISEB. std logic_1164.012, shes entity sy2led is ort ov + dn STD_LoGIC_VECTOR(? downto 0); 14 : out STB_LOGIG_VECTOR(7 downto 0} y fend sw2eas architecture swlied of sw21ed 4e Signal declarations used on the diagram ‘ignal 8US23 ; STD_LOGIC_YECTOR (7 downto 0) begin Terminal assignment ---- BusE3 <= ews -+ Output\butfer terminals aa ce BUSES Listing 1.3 sw2ed2.vhd Library EEE; fuse TEBE, std_logic_a164 eneiey ouated? 4a port ld : out STD_LOGIe VECTOR(7 downto 0} ds end exzied2s architecture ou2led? of avaled2 ie begin10 Example + Note in the entity in Listing 1.3 thatthe input sr and the output Id are defined to be of type STD_LOGIC_VECTOR (7 dovnio 0). For simulation purposes this type is defined to have nine possible values. In addition to the usual 0 and 1 the other seven possible values are U (uninitialized), X (unknown), Z (high impedance), W (weak unknown), L (weak 0), H (weak 1), and — (don’t care). In Parts 2 and 3 of the tutorial in Appendix A. we show how to synthesize, implement, and download the design to the EPGA board. In summary, the steps you follow to implement a digital design on the BASYS or Nexys-? board are the following: Create a new project and design name, Using the BDE create a logie diagram. Save and compile the be file Optionally simulate the design (see Example 2) Synthesize the design selecting the Spartan3E: family and the 3s100etq)44 device forthe BASYS board and the 3s500efu320 device for the Nexys-2 board 66. Implement the design using ether basys2.uef or nexys2.uefas the custom constraint file. Check Allow Unmatched LOC Constrains under Translate and uncheck Do Not Run Bitgen under BitSiream, Select JTAG (Clock asthe start-up clock under Startup Options. 7. Use EePort to download the .bi file to the FPGA boned. At this point the switches are connected to the LEDs. Turning on a switel will light up the corresponding LED. Problem 1.1 ‘The four pushbuttons on the BASYS and Nexys-2 boards are connected to pins on the FPGA using the circuit shown in Fig. 1.4. The value of & is 4.7 k& on the BASYS board and 10 KO on the Nexys-2 board. When the pushbutton is up the ‘wo resistors pull the input down to ground and the input byn() to the FPGA is read asa logic 0. When the pushbutton is pressed the input is pulled up to 33 V and the input bin( to the FPGA is read as a logic 1. Create a Ade file using Active-HDL. that will connect the four pushbuttons to the rightmost four LEDs. Compile and implement the program. Download the .hir file to the FPGA board and test it by pressing the pushbuttons, R 3ave—h A btn) om Figure 1.4 Pushbutton connection2input Gates " Example 2 2-Input Gates In this example we will design a circuit containing six different 2-input gates. Example 2a will show the simulation results using Aldec Active-HDL. and Example 26 will show how to synthesize the program to a Xilinx FPGA on a Digilent board, Prerequisite knowledge: ‘Appendix C ~ Basie Logie Gates “Appendix A — Use of Aldee Active-HDL 24 Generating the Design File gates2.bde Part 4 of the tutorial in Appendix A shows how to connect two inputs @ and b to the inputs of six different gates using the block diagram editor (BDE) in Active-HDL. ‘The result is shown in Fig. 2.1. Note that we have named the outputs of the gates the name of the gate including an underscore. Identifier names in VHDL can contain any letter, digit, underscore _, or S. The identifier ean not begin with a digit or be @ VHDL. keyword. VHDL is nor ease sensitiv. ‘The name of this file is gares2.bde, When you compile this file the VHDL. program gares2.vhd shown in Listing 2.1 is generated Figure 21 Circuit diagram for Example 212 Example 2 Listing 24 gatos2.vhd ‘Eeample Ze; gatesd ary, TEBE? EEE. std logic 1164.ab1; entity gates? te pore( ‘a: dn STD rosie; bi dn stp-toare; and_gate + out. §10_LosrC; Bend_gate + out STD LoGic; Ror_gate + out STO ZoaIC, or.gate : out st ioarcy snor_gate © out 88D LOOiC; zor gate + out S10 LOGIC ) ‘end gatee2; architecture gates? of gates? is begin andigate <+ band a and gate <= aot (b and a); orgate «= bora nor-gate c= not ib oF a); sorigate <1 b xor ay snoz gate <= not (b nor a} fend gates? ‘The logic diagram in Fig. 2.1 contains six different gates. This logic circuit is eseribed by the VHDL program shown in Listing 2.1. The firs line in Listing 2.1 is a comment. Comments in VADL follow the double dash. All VHDL programs begin with an entity statement containing the name of the entity (gares2 in this ease) followed by a list ofall input and output signals together with their direction and type. We will generally use lower case names for signals. The direction ofthe input and output signals, is given by the VHDL statements in, out, or inout (fora bi-directional signal), ‘To describe the output of each gate in Fig. 2.1 we simply write the logie equation for that gate preceded by the assignment operator, <=. These are concurrent assignment statements which means thatthe statements can be witten in any order 2.2 Simulating the Design gates2.bde Part 4 ofthe tutorial in Appendix A shows how to simulate this VHDL program using Active-HDL. The simulation produced in Appendix A is shown in Fig. 2.2. Note that the waveforms shown in Fig, 2.2 verify the tuth tables forthe six gates. Also note that two clock stimulators were used forthe inputs @ and b. By making the period of the clock stimulator for the input a twice the period ofthe clock stimulator for the input ball ‘our combinations of the inputs a and 6 will be generated in one period ofthe input a,2input Gates 2 [paeeslparsaaqqelwn ase Figure 22 Simulation of oie ceuitn Fig. 2.4 2.3 Generating a Top-Level Design Part Sof the tutorial in Appendix A shows how to ereate a top-level design forthe sgates2cireuit. In order to use the constraint files hasys2.uef or nexys2.uef described in Example 1 we must name the switch inputs sw() and the LED outputs fd). This top- level design as created in Part 5 of Appendix A is shown in Fig. 23. The module gates? in Fig. 2.3 contains the logic cireuit shown in Fig. 2.1. Note that each wire connected 19 «bus must be labeled to identify its connection othe bus lines. ul sw(1:0) B—, 2a P 60 sgt ees ee ee est snort gates2 Figure 2.3 Topsevel design for Example 24 Example? Compiling the top-level design shown in Fig. 2.3 will generate the VHDL program shown in Listing 2.2. The inputs are now the two rightmost slide switches, ‘sw(:0), and the outputs are the six right-most LEDs 5:0). To associate these inputs ‘and outputs withthe inputs @ and 6 and the six output in the gares2 component in Fig. 2,1 and Listing 2.1 we use the VHDL port map statement 1415), hand gate => 14(4), por_gate => 1813), or-gate => 1412), saotigete => 1a), xor_gate => 1410) ” Listing 22 gates2_top.vhd == Eeanple 2b: gatee2_Top Library. Ieee ee IBHE. ota. logic_2164.a11 entity gates top ie port fe ¢ dm STD_LOGIC_YECTOR(1 dowto 0) 14 + out ST5_LosTe_vECTOR(s downto 0) ds fend gatee2_topy architecture gates! Component gates? ere | 2: dn ota togic; fang_gate out std logic bs in etd logic; nand_gate 7 out std logic nor gate + out std logic: or gate : out eta losic, maar gate + out sta josie; xor_gate + out stalogic top of gates?_top se Ms fend component begin un: gates Bes owia), BI awial fand_gate +> 1a(5) hand-gate <> 1a(4), for gete => 14(3) or gave => 1402) waarigate «> 1a(), yor_gate => 14(0) ys fend gatesz_tops2input Gates 5 This VHDL port map statement begins with an arbitrary name forthe component in the top-level design. Here we call it Ul. This is followed by the name of the component being instantiated, in this case gates? from Listing 2.1. Then using the port ‘map statement enclosed in parentheses are the inputs and outputs from Listing 2.1 associated with corresponding inputs and outputs inthe top-level desig in Fig. 23. Note that we connect the input a in Listing 21 10 the input s0(1) on the FPGA board. The input b in Listing 2.1 is connected to sw(0) and the outputs and gare, nand gate, or gate, nor gate, xor_gate, ad xnor gate are connected to the comesponding LED outputs (50). These associations can Be made inthis way in any order. ‘The port map statement in Listing 2.2 generated from the top-level block diagram are associated in alphabetical order. Follow the steps in the ttoril in Appendix A and implement tis design on the FPGA board. Nole that when you change the settings of the two right-most slide switches the LEDs will indicate the outputs of the six gates.a tas Example 3 Multiple-Input Gates In this example we will design a circuit containing multiple-input gates. We will create a logic circuit containing 4-input AND, OR, and XOR gates. We will leave it as a problem for you to create a logie circuit containing 4-input NAND, NOR, and XNOR ates Prerequisite knowledge: ‘Appendix C — Basic Logie Gates Appendix A — Use of Aldee Active-HDL 3.1 Behavior of Multiple-Input Gates The AND, OR, NAND, NOR, XOR, and XNOR gates we studied in Example I had two inputs. The basic definitions hold "2 {for multiple inputs, A multiple-input AND gate is shown in Fig. yy 3.1. The ouput of an AND gate is HIGH only ifall inputs are HIGH, To describe this multipleinput AND gate in VHDL. we Fioueat ‘ould simply write the logic equation as Mulipiesnpit AND gta, 2 x(1) amd x@) and .. and x(0); ” A multiple-input OR gate is shown in Fig. 3.2. The "> . put of an OR gare is LOW 0 us are LOW. ast ‘As with the AND gate we ean write the logic equation as aaa 2 <2 (2) oF £12) oF... oF xia); se ceamaee ‘A multiple-input NAND gate is shown in Fig. 3.3. The ouput of a NAND gate is LOW only if all puss are "21 HIGH, We can waite the logic equation as a 2 ex not (x(t) and x12) and... and x(a!) Figure 33 Mutiptoinput NAND gate, A multple-input NOR gate is shown in Fig. 34. The, ‘ouput of a NOR gate is HIGH only ifall inputs are LOW. We *~ ‘can write the logic equation as “ Figure 34 ‘Muttpiesnput NOR. 2 <= not(x(1) oF (2) oF ... oF x(n)Multiple Input Gatos 7 A. multiplesinput XOR gate is shown in Fig. 35. What is the meaning of this multipteinput gate? Following a — the methods we used for the previous multiple-input gates we 2! —] can write the logic equation as | Fegwe 35 2 ce (2) gor (2) MOE... KOE snl Mutipleinput XOR gate, We will rest a 4-nput XOR gate inthis example to 0 —Y determine is meaning but fst consider the mulipleipt. "=| , NOR gate shown in Fig 3.6. Whats the meaning of ita» imutileipat gate?" (See Problem 3.1 atthe end of this Chample for he answer) Following the methods we sed yuo 28 for the previous multiple-input gates we can write the logic eC as cavation ss fee nobtnta) aor x12) nor so HO Hs ‘or we can use the following gate instantiation statement for an XNOR gate. 2 ce (1) mor x(2) enor... amor x(0)7 3.2 Generating the Design File gates4.bde Use the block diagram editor (BDE) in Active-HDL. to ereate the logic cireuit called gates4. de shown in Fig. 3.7. A simulation of this circuit is shown in Fig. 3.8 From this simulation we see that the ouput of an XOR gate is HIGH only ifthe number of HIGH inputs is ODD. 40) TB ance_gate ort_gale Figure 3.7 Block diagram for gates bde18 Examples If you look at the ile gates4.vhd that is generated when you compile gates4.bde you will see thet Active-HDL defines separate components forthe 4-input AND, OR, and XOR gates and then uses a VHDL instantiation and port map statement to "wire" them together. ‘Altematively, we could use the HDE editor to write the simpler VHDL program called gates4b.vhd shown in Listing 3.1 that uses standard VHDL logical operators to implement the three 4-input gates. This VHDL program will produce the same simulation as shown in Fig. 3.8 ae aS Oe Bn Rae oe bony aaaeie Figure 3.8 Simulation ofthe design gatesé.bde shown in Fig. 37 Listing 2.1: gatesdtvhe) ~-Exaupie J; 4-inpat Gatee Library 1222; fuse IEER.STD_LOGIC_1264,a11; ‘entity gateeth to pores x + 4m STD_LOGIC_VECTOR(4 downto 1); andt_gate 7 out S10_LosIC; out s7D foarte; architecture gates of gatesth te Begin fnd4_gate <= x(1) and x(2) and x(3) and x4); Ord gate <= x{1) oF x{2) of x12) oF id); xord gate <= x(1) amor x(2) smor (2) nor x14)Mutiptenput Gates 16 3.3 Generating the Top-Level Design gates4_top.bde Fig. 39 shows the block diagram of the top-level design gates top.bde. ‘The module gates4 shown in Fig, 3.9 contains the logic cireuit shown in Fig. 3.4. If you compile gates 1op.hde the VHDL program garesd_top shown in Listing 3.2 will be generated. Compile, synthesize, implement, and download this design to the FPGA board ut vay [Pe GOD —foo san] ES oe 20) atest Figure 3.9 Block diagram for the top-level design gatosé_top bdo Listing 3.2: gates4 top.v Samet pa cinren xvas peo eiavel Library’ THE; twee IEEE, ctd logic 1164-411; Library Ba0@LE3; entity gatest_top te ‘port ey + tm etd logic vector(3 downto 0} 1d: out STH_LoGre vEcTOR'2 downto 0) Ms end gateed_tops architecture gatesd top of gatesé top te ‘component gates pore | X tin std logic_vector(3 dewte 0); ands_gate 7 out st logic: Gra gate + out sta logic, xori_gate : out std_iogic ie ‘end component begin, UL: gates pore map andt_gate => 1412), Seagate = 1d). xort_gate => 14(0) end gateot tops20 Example 3 Problem 32 Use the BDE to create a logi circuit containing 4-input NAND, NOR, and XNOR gates. ‘Simulate your design and verify that she ouput of an XNOR gare is HIGH ‘only ifthe number of HIGHT inpuss is EVEN, Create a top-level design that connects the four inputs to the rightmost four slide switches and the three outputs tothe three rightmost LEDs. Implement your design and download it to the FPGA board, table with (x(1), x(0)) as the inputs and »(0:3) as the L —_ outputs. What is the behavior of this decoder? 1Equaliy Detector 2 Example 4 Equality Detector In this example we will design a 2-bit equality detector using two NAND gates and an AND gate, Prerequisite knowledge: ‘Appendix C ~ Basie Logie Gates Appendix A ~ Use of Aldec Active-HDL 4.1 Generating the Design File eqdet2.bde The truth tale for a 2-input XNOR gate is shown in Fig. 4.1. Note that the ‘output is I when the inputs x andy are equal. Thus, the XNOR gate can be used asa 1- bit equality detector. XNOR Figure 4.1 The XNOR gates tit equality detector By using two XNOR gates and an AND gate we can design a 2-bit equality detector as shown in Fig. 4.2. Use the BDE to ereate the file eqdet2.Ade using Active HDL. 1:0 Lk es 0) Perel nee Figure 42. Block diagram ofa 2-bit equality detector, eqdet2 bdo22 Examples Ifyou compile the file egder2.dde Active-HDL will generate the VHDL program cegdet2.vhd shown in Listing 4.1. simulation of egder2.bde is shown in Fig. 4.3. Note that the output eg is 1 only ifa(1:0) is equal to (1:0). Listing 4:1: eqdeta.vha = Title eqie? Library 1885; use IEEE. std logic 2164.11; entity eqdet2 is ‘pore ‘a + Am STD_LOGIC_VECTOR(L demto 0): + dm STD_LOGIC_VECTOR(L downto 0); eq: out STD Losic ds fend cadet; architecture egdet2 of aqdet? is Signal eqi + STD Locre; signal eq? : STD_LoGrcy begin eg < not (b(2) xor a (3); eq2 <= not (b(0) wor a10))) eq <= eq2 and eql; [s@elom [Rate QQgRei wun” [vae|Sinmo [9 ws em we Figure 43 Simulation ofthe 2-bt equally detector, eqdet2 bdo Create a top-level design called eqder2_top. ae that connects a(1:0) and B{1:0) 19 the rightmost four slide switches and eonneeis the output eg to Ia{0). Implement your design and download it to the FPGA board.2410-1 Multiplexer: if Statement 23, Example 5 2-to-1 Multiplexer: if Statement In this example we will show how to design a 2-to-1 multiplexer and will introduce the VHDL ifstatement. Section 5.1 will define a multiplexer and derive the logic equations for a 2-0-1 multiplexer. Section 5.2 will illustrate the use of two versions of the VHDL if statement Prerequisite knowled Kamaugh Maps. Use of Aldec Active-HDL. - Appendix A 5.1 Multiplexers An r-input multiplexer (called a MUX) is an n-way digital switch that switches fone of inputs to the output. A. 2-input multiplexer ig shown in Fig. 5.1. The switeh is controlled by the single contol line s. This bit selects one of the two inputs 10 be connected” to the output. This means that the logical value of the output will be the same as the logical value of the selected input From the truth table in Fig, 5.1 we see that y= ifs= 0 and y= 6 ifs 1. The Karnaugh map for the truth table in Fig. $.1 is shown in Fig. 5.2. We see thatthe logie ‘equation for yis y= -s6aleub 6.2) [Note that this logic equation deseribes the circuit diagram shown in Fig. 53. — 2x1 Mux » Figure 8.1 A2-1o-1 mutiplxer Figure 52 Kemap for 20-1 multiplexer26 Examples Use the BDE to ereate the block diagram mux2/.bde shown in Fig. 5.3 that implements logic equation (5.1). Compiling mu2/.bde will generate a VHDL, fie, ‘mux? -vhd, tat is equivalent to Listing 5.1. A simulation of mur2J.bde is shown in Fig, 544. Note in the simulation that y=aif's=Oand y= bif's= 1. 22 ee D> we Figure 5 3 Block cagram for a 2-0-1 muliplexe, mux21.boe Listing 5:1 Examplesa.vhd = Example Sa: 2-Co-1 WOK using Yogic equations Library’ THEE; lube IEEE. etd Logic_i164.a11; entity muxzi te ore ‘a an stp vocre; D+ am stD-toare; 8 + 4n stp_toate, y + out STB Lore ds fend mux21: arenieacture mis22 of mx2l te ‘ignal sout + S1D_L00rG; Hgnal bout | STD_LoGTG, Signal nots : STD_LoSIC; begin ‘aout <= note and ay Bout <2 and by pots <= notla): yee bout or aout, fond mid2to-1 Multiplexer Statement 25 fle Eat Seach Ye! Wigksnace Qesgn Sain” Wavefo Teo tron Hep « [eG i eelookaemaaq* Nore [ene [Sindio] > 0 © wm Figure §.4 Simulation ofthe 240-1 MUXin Fig. 53 5.2 The VHDL if statement ‘The behavior of the 2.x | multiplexer shown in Fig. 5.1 ean be deseribed by the VHDL statements ‘We saw that the assignment statements in VHDL using the assignment operator <= are concurrent and execute in parallel. On the other hand the if statement is an example of @ procedural, or sequential, statement. Procedural statements must be ‘contained within a process and ate executed in the order that they appear in the code. Thus, the VHDL ifstatement must be contained in a process as shown in Listing 5.2 The process begins with the statement labels: process (csoneitivity List) Where the sensitivity ist contains a list of ll signals that will affect the outputs generated by the process block and the label isan arbitrary name of your choice following typical variable naming conventions. In Listing 5.2 the seasitivity lit contains the inputs a, by and s, so that a change in any ofthese three inputs will affect the output y. If you do not include a signal in the sensitivity list then the circuit that is generated may not be the one that you want. This is a common error that is sometimes hard to detect. The VHDL. code in Listing $2 will be compiled to produce the logic circuit shown in Fig. 5.3. A simulation ofthe VHDL code in Listing 5.2 will produce the same waveform as shown in Fig. 54.2% Examples Listing 5.2. Exampledo vha == Exanple 4b: 2-to-1 WOK using if Seavamane Aibrary’THE8, ‘uae IEEE.STD. LOGIC 1164.11; ‘entity ouxib de pores b : 4m sTO-LoaIC; 5 + in sto_Losre; ¥ + out stb tosre ” architecture miczib of mixgab Le fend mxziby Create a top-level design called mux2/_top.bde that connects @ and 4 to the rightmost two slide switches, connects s to bin(@), and connects the output y to 140), Implement your design and download it to the FPGA. board. Test the operation of the ‘multiplexer by changing the position of the toggle switehes and pressing pushbutton bin)Quad 240-1 Mutilexer 2 Example 6 Quad 2-to-1 Multiplexer In this example we will show how to design « quad 2-to-1 multiplexer, In Section 6.1 we will make the quad 2-10-1 multiplexer by wiring together four of the 2-to-1 multiplexers that we designed in Example 5. In Section 6.2 we will show how the quad 2-to-1 multiplexer ean be designed using a single VHDL if statement. Finally, in Section 6.3 we will show how to use a VHDL parameter to define a generic 2to-1 multiplexer ‘with arbitrary bus sizes Prerequisite knowledge: Example 5 ~ 20-1 Multiplexer 6.1. Generating the Design File mux42.bde By using four instances of the 2-to-l MUX, mux21.bale, that we designed in ‘Example 5, we can design a quad 2-to-1 multiplexer as shown in Fig. 6.1. Use the BDE to create the file mox24.bde using Active-HDL. Note that you will need to add the fle ‘mux? bde wo your project tE0) Figure 6.1. The quad 2-0-1 MUX, mux24.bde, contains four 2-0-1 MUXS2 Example Ifyou compile the file mux24.hde Active-HDL will generate the VHDL program ‘muc24.vhd show in Listing 6.1. A simulation of mux24.dde is shown in Fig, 6.2. Note that the output (3:0) will be ether a(3:0) or 53:0) depending on the vale of s, Listing 6.1 Examplo6a.vind =~ Bxanple sa: wuxzé ‘use IEEE. ctalogic 2164.11, Library EXAMPLE; entity monas ds ‘port 8 + dn atd Logie; a + dn STDILOGIE VECTOR(3 downto 0); bs dn smp-Loore_vEctoR(a downto 0); Y : out STD_Locre_vecroR(> domes 0} archivecture sw24 of mxo4 ie Component sud) pert | 4 + dm etd togie; Bi: dn std logics 2: dn eed togier y + out std logic , fend component begin ‘pore map Bo ald), bas BI), 8 = 5, ¥ => ia! 2 = mona, ‘port map\ See a2), b => BI), @ => a, 7 => yl2) > U3 + muxai port map Be> a), bas BU), ee, ye ya) ua + suxaa ‘port mapl Bes alo), b => B«O), 1 Ly es 700) ond m4(uae 2-0-1 Mutiplexer 2 RQSm eQQRi a” Figure 6.2 Simulation of the quad 210-1 MUXin ig. 6.4 Use the BDE to create the top-level design called mux2/_top.bde shown in Fig 63, Note that a(3:0) are connected to the four leftmost slide switches, (3:0) are connected to the rightmost four slide switches, and 3(3:0) are connected to the four rightmost LEDs. Also note thats is connected to bin(0), and the input b(0:0) must be declared as a sic! fogic_vector, even though there is only one clement, so that we ean USE the constraint fle busys2.uef or nexys2.uef without change. Implement your design and download it to the FPGA board. Test the operation of the quad 2-o-i multiplexer by setting the switch values and pressing pushbutton b1m(). Ifyou compile the file mux24_top.hde Active-HDL will generate the VHDL program ‘mux24_top.vhd shown in Listing 62. A simulation of mux24 top.hde is shown in Fig. 64, oa? 0) ut 28 ho) y90fr—Drid(3 0) va 2% bin(0.0)- ob Figure 6.8 Top-evel design for testing the quad 2-0-1 MUX Listing 6.2 Examples vid ~~ Example Sb: mx24_tOp Library TEEE; use IEEE. ota” logic 2164.11; Tibeary ZUMPLEC; fentity mux24_top de pore btn 1 Am STD_LOGIC_VECTOR(O downto 0) ev : An eta logic vector(7 downto 0); 14: out std logid vector (> downto 0)20 Example Listing 6.2 (cont) Examplabb.vha architecture mini top of musdl_fop Te port 42 Am std togie vector(3 domte 6); BD: im sta logic vector(3 dowte 6) Y : out std logic _vector(3 dowto 0) fend component begin port map BIO) => aw(4) 2) 2 avis) 212) => Sule, 313) 2 ew) Bio) => swlo), bal 2 awit), BG) 23 em(2), BO) = emia), Biato), 18 ds end’ mux24_top? Figure 6.4 Simulation of mux24_top bao n Fig 61 6.2 A Quad 2-to-1 Multiplexer Using an if Statement In Listing 5.2 of Example 5 we used a VHDL if statement to implement @ 2-to-1 MUX. Listing 6.3 is a direct extension of Listing 5.2 where now the inputs and outputs are 4-bit values rather that a single bit. The VHDL. program shown in Listing 6.3 will produce the same simulation as shown in Fig. 6.2. The module mux24b defined by the EDL program in Listing 6.3 could be used in place of the miet24 module in the top- level design in Fig. 63,(Qua6 240-1 Multiplexer a” Listing 6.3. mux2ab.vha —-Exanple Ger Quad 2-to7d WE using Tf Statement Library TEE; tase THEE, STO. LOGIC 1164.11; entity muztb te port ( + im 81D Loare_vECTOR(3 downto 0); Y : owt STD_LOGIC_VECTOR(3 downto 0) fend mux24bs architecture muc24b of mnaeb ie Signal 24: STD_LOGIC VECTOR(3 downto 0); begin pi: proces begin ces os ena mena, (abe 8) arameters We can use the VHDL generic statement to design a generic 2-to-1 multiplexer ‘with input and output bus widths of arbitrary size. Listing 64 shows a VHDL program fora generic 2-t0-1 MUX. Note the use of the generic statement that defines the bus width N to have a default value of 4, This value can be overridden when the multiplexer is instantiated as shown in Listing 6.5 for an 8-line 2-o-1 multiplexer called MB. ‘The parameter overtide clause is automatically included in the port map statement when you copy it in Active- HDL as shown in Listing 6.5. We will always use upper-case names for parameters. The simulation of Listing 6. is shown in Fig. 6.5. If you compile the VHDL program me2g.vhd shown in Listing 64 it will generate a’block diagram for this module when you go to BDE. Ifyou right-click on the symbol for muac2g and select Properties, you can change the default value of the parameter by selecting the Parameters tab and entering an actual value for N.Example 6 Listing 6.4 mux2g.vha = Example Gd: Generis 2-to-1 WOK weing @ Parameter Library 1265; ‘use IGHE.STD.LOGIC_1164.a11; fencity mxzg 42 nerie(Nsintager = 4) eres 4 + am S1D_LOGIC VECTORIN-1 downto 0); 5: dn StD-LOGre_VECTORIN-2 downto 0}; 8 + an srD_Locrc; Y $ eut STB LOGIC VECTOR(N-1 downto 0} yy end mux architecture muxzg of muxag Le begin I! process (a, b, @) Begin, Listing 6.5 mux28.vhd Example 6e; 8-1ine 2-to-l MOK using @ paranater use TEBE.STD_LOGIC_1164.al1; entity mz te pore 2 + dn 8TD_Logre vECTORI7 downto 0) D+ dm STD_LOGIC_VECTOR(7 deweo 0); 8 + dm sro_uosre; Y eut S19 LOGIC VECTOR(7 downto 0} " fend muxz8 archivecture mux2e of muxze ie Component muxzg ta ‘Sonerieill: posteive t= 4); pores im ST0_LoGIC_vECTOR(N-1 downto 0) im STO LOGIC VECTOR(N-1 downto 0} in st0_toste; ‘out ST_LOGIC_VECTOR(N-1 downto 0} a fend component(Que 240-1 Mutiplexer Listing 65 (cont) mux28.vhd begin Mos mux2g generic map(t! <> 8) port map Gea, fond mux28; Figure6.5. Simulation resut ftom the VHOL program in Listing 6.54 Example? Example 7 4-to-1 Multiplexer In this example we will show how to design a 4to-1 multiplexer. In Section 7.1 wwe will make a 4-to-1 multiplexer by wiring together three ofthe 2-to-1 multiplexers that wwe designed in Example 5. In Section 7.2 we will derive the logic equation for a 4-0-1 MUX. In Section 7.3 we will show how a 4-to-1 multiplexer ean be designed using a single VHDL case statement and in Section 74 we design a quad 4-o-1 multiplexer. Prerequisite knowledge: Example $—2-o-1 Multiplexer 7.1 Designing a 4-to-1 MUX Using 2-to-1 Modules ‘A d-to-1 multiplexer has the truth table shown in Fig. 7.1. By using three instances of the 2-to-1 MUX, mur21. ba, that we ‘designed in Example 5, we ean design a 4-0-1 multiplexer as shown in Fig. 7.2. Use the BDE to create the file mucrd/.bde using Active-HDL.. Note that you will need to add the file ‘mux? -hde to your project. In Fig. 7.2 when s(1) = 0 iis v, the output of U2 Figure 7.1 that gets through to 2. If s(0) = 0 in U2 then it is c(0) Truth table for a4to-t MUX: that gets through to v and therefore to z. If's(0) = 1 in U2 them it is o(1) that gets through to v and therefore to z (30) [wf (0 Figure 7.2 The 44o-1 MUX, mux.bde, contains four 24o-1 MUX.410-1 Mutiplexer 26 If, on the other hand, s(1) = I in UL then it is w, the output of U3 that gets through toz, If-s(0) = 0 in U3 then it is c(2) that gets through to w and therefore to 2. If (0) = 1 in US then iis 3) that gets through to w and therefore to z. Thus you can see that the circuit in Fig. 7.2 will implement the truth table in Fig, 7.1 When you compile the file mot4I.bde Active-HDL will generate the VHDL program mot4I.v shown in Listing 7.1. A simulation of mu. be is shown in Fig. 73. [Note thatthe output z will be one of the four inputs e(3:0) depending on the value of (1:0) Listing 74 muxét.vhd <= Exseple 7a: 4-to-d WOK using nodule inevaneiation eee IBEE,otd logic_1168.a12, Library EXAMPLE; ‘port © + dn 8TD_LOoTC vECTOR(3 downto 0): 3: dm STD-Logie_vEcTOR(1 downto 0) 2: out std_logic , fend muxeial architecture mucila of mixtia ie Component mux2 port | a + 4a etd togie: Bm sta_logic: 8 + in sta_togic; y } out std logic o ‘end component; etd_logie std_logie pore aap Pov be we sah yore » ‘port map Ber c(0), b= cl}, es ala), ys ‘port map aes (2) 200)6 Example Figure 7.8. Simulation ofthe VHDL program in Listing 7.1 I you were going to create this top-level design using HDE instead of BDE you ‘would begin by defining the inputs (3:0) and s(1:0) and the output z and the two signals, vand w. You would then “wire” te three components together using the three por! map statements shown in Listing 7.1 ‘The easiest way to generate this port map statement is to fist compile the file ‘mux2I-vhd from Example 5 using Active-HDL, expand the library icon (click the plus sign, right click on mux2i, and seleet Copy VHDL Instantiation as shown in Fig. 74, Paste this into your top-level muxd/.vhd file. (Sone ¥ mao ime) rca aor ents Figure 7.4 Generating @ module instatiaton prototype40-1 Muttplexer st At this point you would have the statement tabela : mux2t port map bob, fo Make three copies of this prototype and change the name of Label? to Ul, U2, and U3 in the three statements, Now you just “wire up” each input and output variable by changing the values in the parentheses to the signal that it is connected to, For ‘example, the mux Ul input a is connected to the wire v so we would write a => x. Ina similar way the mux input 6 is connected to wire w and the mux input sis connected to input s(1). The mux output y is connected to the output z in Fig. 7.2. Thus, the final version of this port map statement would be port map The other two modules, U2 and U3, are “wired up” using similar port map statements 7.2. The Logic Equation for a 4-to-1 MUX ‘The 4-to-1 MUX designed in Fig. 7.2 can be represented by the logie symbol shown in Fig. 7.5. This multiplexer acts lke a digital switch in which one ofthe inputs G0) gets connected to the output z. The switch is controlled by the two contol lines (1:0), The two bits on these control lines select one ofthe four inputs to be "connected" to the output, Note that we consiructed this 4-to-1 multiplexer using three 20-1 ‘multiplexers in a ee fashion as shown in Fig, 7.2. Ut spon | ston muta Figure 7.5 A41o-1 mulipiexer28 Example Recall from Eq. (5.1) in Example 5 that the logic equation for a 20-1 MUX is, given by ys -staleap on Applying this equation to the three 2-10-1 MUXs in Fig. 7.2 we can write the ‘equations for that 4x 1 MUX as follows. Be-stavi sey s- (80 & 60 | 60 @ cl) | st & (50 & ez | 90 4 3) z= 82 & ~20 & co jc t sce oa | sie so ceo | sie sees Equation (7.2) for also follows from the truth table in Fig. 7.1. Note thatthe ‘tee structure in Fig. 7.2 can be expanded to implement an 8-10-I multiplexer and a 16-to- 1 multiplexer. ‘A VHDL program that implements a 4-1-1 MUX using the logic equation (7.2) is given in Listing 7.2. simulation of this program will produce the same result asin Fig. 7.3 (without the wire signals v and w). Listing 7.2 muxatb.vna == Example Tb: 4-tonl NOX waing logis equation je TSE, STD LOGIC_1164.412; fentdey muxaab te pore © + am S1D_LOGIC_VECTOR(3 downto 0); + Am STO_LOGIC_VECTOR(2 downto 0); : st architecture miciib of muti 42 begin zi fond maxes, architecture mixéd of muxts is begin l: process ix, 8) begin X13 downto 0} 21 downto 4); 2 <= x(15 downto 12) Set xOo"domeo 0)‘4041 Multiplexer a“ le ER Sek Yow Wakpace Deis Gras Wnelam Toa Boo kAsm Q@age tr” Shae] Figure 7.8 Simulation of he quad 4-0-1 MUXin Listing 74 ut fam zon}6 Has ued Figure 7.7 A quad 4to-1 muitiplexer42 Example Example 8 Clocks and Counters The Nexys-2 board has an onboard 50 MHz clock. The BASYS board has a Jumper that allows you to set the clock to 100 MHz, 50 MHz, or 25 MHz. All of the ‘examples in this book will assume an input clock frequency of 50 MHiz. Ifyou are using the BASYS board you should remove the clock jumper, which will set the clock frequeney to 50 MHz. This 50 MHz clock signal isa square wave with a period of 20 ns, ‘The FPGA pin associated with this clock signal is defined in the constraints file ‘basys2.uef or nexys2.uef with the name melt In this example we will show how to design an Nt to.se a counter to generate clock signals of lower Frequencies. counter in VHDL and how Prerequisite knowledge: Appendix A — Use of Aldee Ak 8.1 N-Bit Counter ive-HDL ‘The BDE symbol for an N-bit counter is shown in Fig. 8.1. Ifthe input efr = 1 then all N of the outputs q(@) are cleared to zero asynchronously, i... regardless of the value of the input clk. If fr = 0, then on the next rising edge of the clock input el the N- bit binary output g(N-1:0) will be incremented by 1. That is, on th rising edge of the clock the A-bit binary output g(N-1:0) will eount from 0 to N-1 and then wrap around to 6. ut » fee gavin} counter Figure 8.1 An N-bt counter ‘The VHDL program shown in Listing 8.1 was used to generate the symbol shown in Fig. 8.1. Note that the sensitivity lst of the process contains the signals clk and elr. This means that theif satement within the process will exsoute whenever either clr or elk _80¢s high. If clr goes high then the output g(N-1:0) will go to zero. The statement count <= (others => 10"); sets all bits of couns(N-1:0) to 20. The phrase clktevent and clk = ‘1(Cocks and Counters 4 in the elsif clause in Listing 8.1 means that there was an event on the signal ell, ie. it ‘changed value and it ended up at 1. That i, there was a rising edge of the clock. Thus, if ‘lr = 0 and there isa ising edge of the clock signal elt then the output g(-1:0) will be incremented by 1. Note that count(N1:0) is defined to be a signal in Listing 8.1. This is necessary because the output g can not be read and therefore you can no! use a statement sch as qatar in Listing 8.1. Rather you must inerement the signal coum(N-1:0) within the process in Listing 81 and then assign the output gto coun outside the process. Listing 8.1 counter.vh Library’ #53; ‘use IEEE.STD_LOGIC_1264. 412 fuse IEEE.Stt generseiN + integer s= 8); port clk 4 + ue STO LOGIC YECTOR|N-1 downto 0) architecture counter of counter is Signal count: STD_LOGIC_VECTOR(N-2 downto 0} Bessa seers 1a Af clkvevent and clk elk, eis) fend counter; ‘The default value ofthe parameter N in Listing 8.1 is 4. A simulation ofthis 4-bit counter is shown in Fig. 82. Note that this counter counts from 0 to F and then wraps around to 0. To instantiate an 8-bit counter from Listing 8.1 that would eount from 0 255 (or 00 — FF hex) you would use an instantiation statement something like cots + counter generic map port map cir => clr, clk = elk, a=44 ample 8 You can also set the value of the parameter NV from the block diagram editor (BDE) by right-clicking on the symbol in Fig. 8.1 and selecting Properties and then the Parameters tab, Note in Listing 8.1 that we have included the additional use statement 185E.570_LOGIC_uneigned.ai2; ‘This statement will include the library file ansigned.whd in the project. This is required {in order to use the + sign to implement the counter by adding 1 tothe signal count Be ER Seach Vow Warspae Geagn Srulsion Ueto Toa Wed Figure 8.2 Simulation ofa 4-it counter using Listing 8 1 Inthe simulation in Fig. 8.2 note thatthe output q(0) is a square wave at half the frequency of the input clk. “Similarly, the output g(1) is a square wave at half the frequeney of the input q(0), the output q(2) is a square wave at half the frequency of the input g(1), and the output q(3) is a square wave at half the frequency of the input 42), [Note how the binary numbers 93:0) in Fig, 8.2 count from 0000 to 1111 ‘The simulation shown in Fig. 82 shows how we can oblain a lower clock frequency by simply using one of the outputs g(). We will use this feature to produce a 24-bit clock divider inthe next section, 8.2 Clock Divider ‘The simulation in Fig. 82 shows thatthe outputs 4() of a counter are square ‘waves where the output q(0) has a frequeney half ofthe clock frequency, the outptg(1) asa frequency half of q(0), etc. Thus, a counter ean be used to divide the requency for a clock, where the frequency of the output g(i) is f= f/2'". The frequencies and period ofthe outputs ofa 24-it counter diven by a SO MHz clock are shown in Table 8.1. Note in Table 8.1 tht the ouput g(0) has afequency of 25 MHz, the output g(17) has a frequency of 190.73 Hz, and the output q@23) has afequeney of 2.98 He.‘Clocks and Counters “s “Table 8.1 Clock divide frequencies a) | Frequency (He) | Petiod (ns) i sovo0000.00 | 0.0900 ‘2 25000000.00 | 0.00008 *1|42800000.00 | 0.00008: | 6250000 00 | 0.00086 '3[ 3125000 00 | 0.00082 ‘41562600 00 [0.00064 | 7et25000| 0.00128 6 7 3 3 "390625.00 | 0.00288 195912.50 | 0.00512, 197655.25 | 0.01024 8628.13 | 0.02046. 70 | 24a 06 | 0.04005, it ‘12207 05 | 0.08162 12 6103.52 | 0.16384 13 3051.76[ 032768 14 1625.88 | 065596 15 7ez04 [1.31072 16 aeia7 | 202ie 7 07a [5.24288 18 95.37 | 10.48676 18 ‘47.68 [2097182 20 23.4 [41.9430 21 1.92 | 53.6608 2 5.96 | 767.7216 2 2.06 | 236 54432 ‘The VHDL program shown in Listing 8.2 is a 24-bit counter that has three ‘outputs, a 25 MHz clock (clk2), a 190 Hz clock (cHk190), and a 3 He elock (el3). You can modify this clkdiv module to produce any output frequency given in Table 8.1. We will use such a clock divider module in many of our top-level designs. Listing @.2 elkav.vhd = example ab: clock divider Library 1E55, ‘use IEHE_STOLOGIC_uneigned. all; enedty clkasy to port Sir = tn eto. Locre, elke : out S10 Lore | '46 Example’ architecture clsciv of cima iF Signal ¢:STD_LOGICVECTOR(23 downto 0); ‘clock divider (vel, ele) proet begin feels = 11! chen. a <= xraon0o", eleit melk‘event and metk = 1! then elkts <= (20); -- 48 ue elise <.qi28); => 180 He end clkaivs Note in Listing 8.2 that we define the internal signal (23:0). The BDE symbol generated by compiling Listing 8.2 is shown in Fig. 8.3. You can edit either Listing 8 or the block diagram shown in Fig. 8.3 to bring out only the clock frequencies you nee in particular design. For example, the top-level design shown in Fig. 8.4 will cause the cight LEDs on the FPGA board to count in binary at a rate of about three counts pee second, The corresponding top-level VHDL program is shown in Listing 8.3. ut {mee cs} ee ehtso| cas] > elkdiv Figure 8.3 A clock aver ut u2 em 110-1470) melk Jet ea] poms) | ‘counter bing) > Figure 8.4 Counting in binary onthe eight LEDsClocks and Counters a Listing @.3 count top.v ‘Beampie gc: countl_top Library EXAMPLES; _1164.a11; entity counte_top Se ‘pore! btn + in STD_LOGIC_VBCTOR(3 downto 3); 1a: out stallogiclvector(? downto 0) ds fend count®_top. architecture counts top of counts top te Component clkaiv pert | cus + tm oud testes c1k3 : out std_tozic » fend component: generic No INTEGER := 8 » port ( cak + tn sta toate: clr + im std logic! 4 + out std fogic vector{-1 downto 0) » signal clks + std logic: Oh elkasy ‘port map! 1k} => clk3, clr ss bem(3), meth => act) ‘generic map ( => 8) port mapi elk > clk, ele => ben(3}, q => 1a 7 dowmte 01); fend count top: Internally, a counter contains a collection of flip-flops. We saw in Fig. 1 of the Introduction that each of the four slices in a CLB of a Spartan3E FPGA contains two flip-flops. Such flip-flops are central to the operation of all synchronous sequential circuits in which changes take place on the rising edge of a clock. ‘The examples in the second half ofthis book will involve sequential circuits beginning with an example of an ‘edge-triggered D flip-flop in Example 16.48 Examples Example 9 7-Segment Decoder In this section we will show how to design a 7-segment decoder using Kamaugh ‘maps and write a VHDL program to implement the resulting logic equations. We will also solve the same problem using a VHDL case statement. Prerequisite knowledge: ‘Kamaugh maps ~ Appendix D case statement ~ Example 7 LEDs— Example 1 9.1 7-Segment Displays Seven LEDs can be arranged in a patter to Form different digits as shown in Fig 9.1. Digital watches use similar 7-segment displays using liquid crystals rather than LEDs, The red digits on digital clocks are LEDs. Seven segment displays come in two flavors: common anode and common cathode. common anode 7-segment display has all of the anodes tied together while a common cathode 7-segment display has all the cathodes ted together as shown in Fig. 9.1. wav commen “anode ‘ > abegets commen snags a Figure 9.1 A 7-segment display contains seven light emitng ciodes (LEDs) ‘The BASYS and Nexys2 boards have four common-anode 7-segment displays. ‘This means that all the anodes are tied together and connected through a pnp transistor to +33V. A different FPGA. output pin is connected through a 1000 eurrent-limiting resistor to each of the eathodes, a g, plus the decimal point. In the common-anode case, ‘an output 0 will urn on a segment and an output 1 will tum it off. The table shown in7-Segment Decoder 4 Fig. 9.2 shows output cathode values for each segment « ~ g needed to display all hex values from 0—F. ab 00 a 10 do do 1 = off oe t b oa oon 9 on oo 00 ote) e ° 00 aa o1 a 10 o1 on Figure 92 Segment values required to splay hex igs 0—F 9.2 7-Segment Decoder: Logic Equations The problem isto design a hex fo 7-segment decoder, called. her7seg, that is storm in Fig. 93. The input a4 hex umber, «@!0), andthe outputs are the 7- tegen values a— given by the bath 9:6) ——ol me tablein Fig. 92. We ean make a Kamaugh *°01—*] hex?seg mm 910.916°] imap for each segment and then write logic quits forthe segments 0 — g. For txample, the Kenap forthe segment, eis gUe8.3 Ahexto segment ecoder showm in Figure 9 051 6x0 [13 8x28 et HDB et BHO 8) “bo oy 11 to 00) a wanes wl a) ~28- a0 Figure 8.4 K-map forthe sogment onthe 7-sogmont decoder50 Exampieg You can write the Kamaugh maps for the other six segments and then write the VHDL program for the 7-segment decoder shown in Listing 9.1. A simulation of this program is shown in Fig. 9.5. Note thatthe simulation ares wth he wu table in Fig, Listing 8.1 hox7eog le.vhd ‘Bxample 9a; Hex to 7-eagnent Gecoder) 2g active Tow Library IEEE {use TEHE.STD_LOGIC 1164411, entity hex?seg le ie port X 1 Am STD_LOGIC_VECTOR(3 downto 0}; 4.to.g + eat STO LOGIC VECTOR(6 domto 0} My fend hextses_le7 architecture hexiseg_le of hexIseg_le 48 begin ‘Sito g{6) <= (not x(3) and not x(2) and aot (2) and x10))--3 OF (not (3) and x(2) and not 11) and not x(0}) OF (x13) and (2) and aot {1} ana =(0)) OF (213) and nae (2) and x11} sna 101); a.tog(5) S (212) and x(1) and aoe x(0)) —. for (213) and (1) and 101) OF (hot x(3} and x(2) and not x(2) and x(0)) OF (x13) and x(2) and not X(2) and noe (0) ato g(4) < thot x13) and not x(2) and xi) ana not ix(0)) oF (x13) and x(2) end x(2)) OF (x13) and #2) and noe (01) ato.g(3) <= (ot x13) and not x(2) and not x(1) and x(0))--4 foe (not (2) and 2/2) and not s(1) and not x(0)) Sf (ei9) and not x(2) and x(2) and not (0)? OF (x(2) and x(2) and <(0)) ato.gi2) <= (mot x(3) and x(0)) - OF (not £(3) and X(2) and aot (21) OF (net £(2) and noe x(1) and x(0)) a.to.g(1) S (not £12) and not (2) and x(0)) z fof (ot (3) and not sx(2) and (2) OF (aot (3) snd e(a) and 3(0)) OF (x13) and x(2) and not 21) and x(0)) £0.90) < (not x13) and not x(2) and not x(1)) a oF (13) and (2) end not (1) and not (0) OF (not x(3) and x(2) and X(1) and (017 fond nex7aeg ler etm seath ow Warpow Deogn Susten Waren Tak whew ep «| sa a ~RAtmMaAaQQg wt” oe we DOHOIOOOOTIOOOEE | tial t1abol=l | Figure @.5 Simulation ofthe VHDL program in Listing 8.‘7-Segment Decoser a 9.3 7-Segment Decoder: case Statement ‘We can use a VHDL ease statement to design the same 7-segment decoder that ‘we designed in Section 92 using Kamaueh maps. The VIIDL program show in Listing 92s a hex-to-seven-segment decoder that converts a 4-bit input hex digit, O— Fo the appropriate 7-segment odes, a — g The case statement in Listing 9.2 direey Jmmplements the truth table in Fig 92. Recall that a typical line inthe case statement, such as when "0011" => a to.g <= "0000220"; a will assign the 7-bit binary value, 0000110, t the 7-bit array, a_eo_g, when the input hex value 2:0) is equal to 3 (0011), In the array 2_co_g the value 2 co 46) corresponds fo segment wand the value 2_ro_9(0) corresponds t segment g. . Note that in VHDL a hex number is preceded by an X Tn the case statement the value following the when statement in each line represents the value of the case parameter, in this case the 4-bit input x. The VHDL program in Listing 9.2 shows the implementation of the 7-segment decoder using @ case Recall that all case statements should include a when orhers line as shown in Listing 9.2. This is because all cases need to be covered and while it looks as if we covered all cases in Listing 9.2, as mentioned previously VHDL actually defines mine possible values for each bit of type STD_LOGIC_VECTOR (see Example 1). ‘A simulation of Listing 9.2 will produce the same results as shown in Fig. 9.5. It should be clear ffom this example and Example 7 that using the VHDL ease statement is, ‘often easier than solving for the logic equations using Karnaugh maps, To test the 7-segment displays on the BASYS or Nexys-2 board create & new project and add the files hex7seg.vhd from Listing 9.2 and the top-level design hex 7seg_top.vhd given in Listing 9.3. Each of the four digits on the 7-segment display is enabled by one of the active low signals an(3:0) and all digits share the same a_10_g(6:0) signals. If an(3:0)= 0000 then all digits are enabled and display the same hex digit. This is what we do in Fig. 9.6 and Listing 9.3. Making the output dp = 1 will cause the decimal points to be off. You should be able to display all of the hex digits from 0 —F by changing the four right-most switehes. ur 2n.9)D—f.c9 amxcal-—Da to 9(60) hexTeag vee Ul > dp NO.SHO.SN. HOG 3.9) GND Figure 86 Topevel desig for testing hex 7sogExample 8 Listing 9.2 hex7sog.vhd = Example 9b: Hex to 7 Library IEEE: jegnent decoders a-g active low entity hexteog t pore 2X + dm STD_LOGIC_VECTOR(3 dowto 0); A.to.g + out STD LOGIC VECTOR(G downto 0) fend hota architecture hexiceg of hexTeesbis ates athos actos sites actog ates = aleerg = *no00000" S alters = *no00200" = alke-g < "0001000"; 55 altolg <= "1100000 = aog 3 altong <= “000020 when X°E* 25 alte.g e= "0120000! when others =>a fog <-7-Sagment Decoder Ea ‘eanple Sc; hexTaeg_t0p eneity hex7seg_top ie port ew 1 £m STD_LOGIC_VECTOR(3 dowmto 0); 4S to.g': out STD LOGIC VECTOR(S downto 0}; 8 + out STD_LOGIC VECTOR(3 dawmte 0); > + out STD_Locre " fond eag7teet, architecture hex7seg_top of hex7seg_top ie ‘pore x + dm STD LOGIC VECTOR(2 downto 0}; tog + out STD_LOGIC VECTOR(S downto 0) ) ap 2 sal digite on sap off DA: hex7eeg port map lend hox7sog tops54 Example 10 Example 10 7-Segment Displays: x7seg and x7segb In this example we will show how to display different hex values on the four 7- segment displays Prerequisite knowledge Kamaugh maps ~ Appendix D cease statement ~ Example 7 LEDs ~ Example 1 10.1 Multiplexing 7-Segment Displays We saw in Example 9 that the a_f0_2(6:0) signals go to all of the 7-segment displays and therefore in that example all of the digits displayed the same value, How could we display a 4-digit number such as 1234 that contains different digits? To sce how we might do this, consider the BDE circuit shown in Fig. 10.1. Instead of enabling all four digits at once by setting an(3:0) = "0000" as we did in Fig. 9.6 we connect ‘an(3:0) to the NOT of the four pushbuttons bin(3:0). Thus, a digit will only be enabled ‘when the corresponding pushbutton is being pressed. ‘The quad 4-1o-1 multiplexer, mue-44, from Listing 7.4 is used to display the 16-bit number x(15:0) as 8 4-digit hex value on the 7-segment displays. When you press bin(0) if the control signal s(1:0) is 00 then x(3:0) becomes the input to the hex 7seg module and the value of x(3:0) will be displayed on digit 0. Similarly if you press bin(1) and the control signal s(:0) is 01 then x(7:4) becomes the input to the hex?seg module and the value of 2(7:4) will be displayed on digit |. We can make the value of s(1:0) depend on the value of bn(:0) using the truth table in Fig, 10.2. rom this tuth table we ean write the following logie equations for s(1) and s(0).. s(2) <2 ben (2) oF ben (a); (0) <= ben(a) oF ben(al The two OR gates in Fig. 10.1 will implement these lagi equations for (1:0) “The constant signal assignment for (15:0) can be made by right clicking on the BDE diagram and. selecting VHDLsignal assignments. Then, wite the signal assignment box to the input and place the constant assignment x <— "7234" in the signal assignment box. The VHDL program created by compiling maseg bein Fig. 10.1 i equivalent to the VHDL program shown in Listing 10.1. Ifyou implement the design muse ble shown in Fig. 10.1 and dovnload the i file tothe FPGA board, then when you press7-Sogment Displays: x7s09 and x7segb buttons 0, 1, 2, and 3 the digits 4, 3, 2, and 1 will be displayed on digits 0, 1, 2, and 3 respectively” Try it. pus aoe woofs, vornoef 20H Lo, ou] —Bato.(60) mae Lsignatssinmerts_t 2 Figure 10.1 BDE circuit mux7seg.bde for multiplexing the four 7-segment displays Figure 10.2 Truth able for generating s(:0)in Fig, 101 Listing 10.1 mux7eeg.vhd T- Example 10a: muxTeey, Library TEBE; fuse IEEE.std logic 1264.a11; entity mox7seg is port ‘btn: 4m STD_LOGIC_VECTOR(3 downto 0): e.to_g + out STD LGGIC VECTORS downto 0) SRF eut STD_LOGEC VaCTOR(3 domes 0) ie fend mx720g;55 Baamle 10 Listing 1.4 (cont) mux7sog.vhd Brchitecture mxiseg of muxTaeg = pore | X + Am STD_LOGIC_VECTOR(3 downto 0) tog : out STO LOGIC VECTORIs downto 0) M ‘end component pore ( 5 : An STD_LoGTC_VECTOR(1 downto 0) ; 2% + Am STDLLOGICLVECTOR (1S downto 0); 2 + aut S70 LOGIC VECTOR(3 downto 0) ie fond component signal digit s7D_LocIc_vEcTOR (3 downto 0); Signal ¢ + STD_LOGIC. VECTOR (2 downto 6) signal = 5 St SCTOR (35 downto 0} ; begin ce x02204%; vi: hex7eeg ‘port map( wy Bae aigith ) = ben{3) oF Benin) 212) So ben (a) oF Ben(2) fan (1) <= aot (ben(2)); fan(0) <= aot (ben(0)), ania) <2 aot iben(2)) anQ) <= mot (ben(a)} end oux7aeg: 10.2 7-Segment Displays: x7seg We saw in Section 10.1 that to display a 16-bit hex value on the four 7-segment displays we must multiplex the four hex digits. You can only make it appear that all four digits are on by multiplexing them fast enough (greater than 30 times per second) e0 thst {your eyes retain the values. This is the same way that your TV works where only a single picture element (pixel) is on at any one time, but the entire screen is refreshed 30, times per second so that you peresive the entire image. To do this the value of s(1:0) in Fig. 10.1 must count from 0 to 3 continually at this fast rate. At the same time the value ‘of the outputs an(3:0) must be synchronized with s(1:0) so a8 fo enable the proper digit at the proper time. A circuit for doing ths is shown in Fig. 10.3. The outputs an(3:0) will satisfy the truth table in Fig. 10.4, Note that each output an) is just the maxterm MU) of (10).7-Sogment Displays: x7s0g and x7sepb a ie? cel sf ge = chr © counter wo | ae I RS 2 Laneer [a senf aac f }—a-to-c(60) 34150) D—form, ay nad Figure 10.3 GDE cuit x78e9 bdo for displaying x(15:0) onthe four 7-segment displays : Figure 104 Truth table or generating an(30)n Fig. 10:3 A simulation of x7seg.bde is shown in Fig. 10.5. Note how the an(3:0) output selects one digit at a time to display the value 1234 on the T-segment displays. When _x7seg. be is compiled it creates a VHDL program that is equivalent to Listing 10.2. The top-level design shown in. Eom EUR GE Fig. 106 can be wel w ust ['ag ec lra jaw mal the. a7seg. module on the fie Roxas [rege eee ee FPGA bound The VHDL = program coresponding ths (ot top-level design is given in es] oo —————— Listing 10.3, Note that the x7seg module requires a 190 Hz clock generated by the ‘lock divider module elkaiv ‘rom Example 8. Figure 105 Simulation of the x7segb be cet in Fig, 10.3,58 Example 10 Listing 10.2 x7e0g.vnd Example 10b: x7503 TREE, std_logic 1164. entity x7eeg be port cir + in sto Lostc; x + dn STD_LOGIC_VECTOR(15 downto 0); a.to.g + out STD_LOGIC VECTOR(G downto 0); Sh © out STO LocTc vacToR(> donee 0} architecture s7eeg of x7e0g ie Component counter generic d pore ( elk + am srp_Locrc; clr + im sTD-Locrc; G + ue STD LOGIC YECTOR(-1 dowee 0) Ms component hexTeeg port | 4% + 4m STD_LOGIC_VECTOR(? downto 0); ato.g + out STD LOGIC VECTOR(S downto 0) ie end component 2 + da Sto yoore vECTOR(1 downto 0) 2X} Am STD_LOGIC_VECTOR(15 downto 0} 2 5 que STD_LOGIC_VECTOR(3 downto 0) ‘signal ng0 + S7D_Lo0rC, ‘Signal ngl + STD_LOGIC: fignal digit + ST0_LOGICVECTOR (3 dowsto 0) Signal q : STD_LOGIC_VECToR (1 domes 0} begin OL: nexteeg fog => ates, weer digit gi <= not (q(2)) rngo <= not (qi0))“7-Sagment Displays: x7se9 ane x7s0gb ore map B10] => aio), sai > 4a), 2 > digit > port apt Clk => colk, qe q( 1 downto 0) v an(0) <= g(0) oF ait): S82) <2 ago or git) an(2) < go) oF nat, asG) So ngo or gi; end x78095 ance} 9.19 96.0) oof —D or) jivec 6 Legetsssormes Figure 108 Toptevel design fr testing x7s09 Listing 10.3 x7eeg_top.vhd == fxanple 10er x7seq_top Library’ IEEE, tune THEE. §7D.LOGIC_2164.422 entity xTeeg_top is pore! ncik + im s7p_tostc; en + in 87D EOGIC_VECTOR(> downto 3), a tog + out STD _16GIC_vacTOR(s downto 0) an + out S70 LOGIC VECTOR(> doweo 0) ap: out S70_LoGIe > end _x7a0g_t0p: so60 Example 10 Listing 10.3 (cont) x750g top.vhd, Brchitecture x7seq_top of x7s0g top fe Coaponent 7205 48 port fclk sin em L00I¢, clr + in 81D Locic; % # Am S1D_LOGIC VECTOR (25 downto 0}; Steg + out STD_LOGIC VECTOR IS downto 0) AR + out STD_LOGIC_VECTOR(3 dowate 0) ) Component clair ere ( clr + dn sro_uocre; hncik + fn STD_toate, e1k290 + out S1D, LOGIC Me fend component eignal x: STD_Locre_VECTOR(25 downte 0} Signal clkis07 sto Loci; begin wae eae -+ test dieplay value xis elkdiv port map (elresben(s), melkepmedk, clks 1130) Xa: x1seg port map (eeom, Gelkesetki90, clresben(3), a te gera tes, ‘Sncsan) aay fend x7805 top: 10.3 7-Segment Displays: x7segb When implementing the circuit for x7seg in Fig. 10.3 we must add separate VHDL files to the project for the modules counter, hex7seg and mus4. Alternatively, ‘we can inelude separate processes within a single VHDL file. “A variation of x7seg, called x7segh, that displays leading zeros as blanks is shown in Listing 10.4. This is done by writing logic equations for aen(3:0) that depend on the values of x(15:0). For example, aen(3) will be | (and thus digit 3 will not be blank) ifany one ofthe top four bits of x(15:0) is I. Similarly, aen2) will be 1 ifany one of the top eight bts of (15:0) is I, and aen(1) will be 1 if any one of the top twelve bits of x(15:0) is 1. Note that ‘aen(0) is always 1 so that digit 1 will always be displayed even itt i zero To test the module x7segb you can run the top-level design shown in Listing 10.4 that will display the value of x on the 7-segment displays where x is defined by the following statement x <= ow & ben(2 downto 0) & "01010"; -- digit 0 = A7-Segment Displays: x7seg and x7segb et In this case we form the 16-bit value of x by concatenating the eight switches, the three right-most pushbuttons, and the five bits 01010. Note that if all switches are off an A will be displayed on digit 0 with three leading blanks. Turning on the switches and pushing the thee right-most pushbuttons will display various hex numbers ~ always with leading blanks. Listing 10.4 x7eogb.vha Beanple 10d: w/aeab — Diapiay 7 Anput eclk should be 190° tz Library TERE use ISEE.STO LOGIC _1164.a11 ig with leading Planks port x + dn STD_LOGIC_VECTOR(15 dowto 0); elk + ta sto LosTe, lz + 4a sto_oare, | tog + out STD_LOGIG VECTOR(6 downto 0); Bt ut STD_LOGTC_VECTOR(3 downto 0 ap + out sto_Locr ” fond 7209; architecture x/sogb of sleegb Se signal s+ S7D_LOGIC_VECTOR(2 deweo 0} Signal digit: STD LOGIC_VECTOR(s downto 0); Signal aen: STD_LOGIC VECTOR(9 downto 0); signal clkaiv: ST0_LOGIC_VECTORI20 downto 0} begin 2 <= chkatv(20 dowto 19) fp cet == set aen{3 downto 0) for leading blanks (15) oF x(24) ef 2103) oF (22) X(05) oF x(24) oF 203) oF #(22) oF (22) oF £110) oF x(9) oF x18) aen(a) eo e(05) oF w(24) oF (19) oF x22) oF (11) oF x{10) oF x(3) oF x18) OF (7) oF x(6) oF (3) OF (8); "ity + gigst 0 always on aento) Saad 4-to- MUX: max Begin case = 4 when *00" => digit <= x(2 dewte 0); when 01" Zs digit <= xe(7 downto 4) when "10" Us digit <= (11 downto 8); when others <> sigit < x(25 downto 32);Example 10 process (digit) case digit te when X03" when xn" hen 0000001"; when X°7" 23 altelg s= 0001103" when x00" 22 aot 0000000" : when fend process: Digit select: ancode precesn(e, Begin’ Af aen(conv_integer(s)) = 11" then an(conv integer (a)) <= ‘0° ona if; end’ procs Clock divider (clk, clr! Mf clr = '2" then Slkdiy <= [others => '9") leit clk’event and clk = 1! then end Sey fend process; end 720g,“Segment Displays: x7sag and x7s6gb Listing 0.5 x7segh_top.vha ~ wxample 108: x7se3_top ‘use IESE,STD LOGIC 1164.11; entity xToegb top Le port clk + 4m so_Loare; btn + im STDLOGIC VECTOR(3 downto 0); ow + Am STD_LOGIC_VECTORI7 downto 0); 2.0.9: out STD LOGIC VECTOR's downto 0); 3h: out STD LOGEC VECTOR(3 downto 0) @p : out sro_Locre hb fend x7segb_top: architecture ¥7se3b top of x7eesb top te Component xtacgh ia port x + dm STD_LOGIC_VECTOR(15 downte 0); (ck sim §TD_LOGrC, elz + in sto_uoste; tog + out STD LOGIC VECTOR(s downto 0); 8 + owt STD_LOGIC_VECTOR(2 downto 0), @ + out STO_Losrc Ms fend component: Signal x: STD LOGIC VECTOR(1S downto 0); begin T concatenate switches and 3 buttons ce ow € btn(2 domto 0) @ "01010"; -- digit 0 ese, elr=sbtn (3) sto gee to 9, apeoap lend x7n03b top:66 Example 1 Example 11 2's Complement 4-Bit Saturator In this example we will design a circuit that converts a 6-bt signed number to a4 bit ouput that gets saturated at -8 and +7. Prerequisite knowledge: Basic Gates Appendix C Equality Detector ~ Example 6 (Quad 2-to-1 Multiplexer ~ Example 6 ‘7-Segment Displays ~ Example 10 14.1 Creating the Design sat4bit.bde Figure 11.1 shows a cieuit called sar4bic bl that was deseribed in the November 2001 issue of NASA Tech BriefS. The circuit will take a 6-bit two's complement number with a signed value between -32 and +31 and convert it to a 4-bit two's complement ‘number with a signed value between 8 and +7. Negative input values less than -8 will be saturated at-8. Positive input values greater than +7 will be saturated at *7 ‘Note thatthe two XNOR gates and the AND gate form an equality detector whose output sis 1 when x(3), x(4), and x(5) ate all equa (see Example 4). This willbe the ease ‘when the 6-bit input number x(5:0) is between -8 and #7. In this ease output 3:0) ofthe quad 2-to-1 MUX will be connected tothe input x(3:0). Ifthe top three bits of (5:0) are not equal and 1(5) is 1 then the input value will be less than -8 and the output y(3:0) of the quad 2-to-1 MUX will be saturated at -8. On the other hand if the top three bits of| (5:0) are not equal and x(5) is 0 then the input value will be greater than +7 and the ‘output »:0) ofthe quad 2-10-1 MUX will be saturated at +7 50) — eo, Figure 11.4. Cheut diagram for satabit be2s Complement 4-8itSaturator 65 Listing 11.4 satabitvid T Branple Tar estabie ‘see TEES. std logic 1164.01; entity eatabir te port x + dm STD_LOGIC_VECTOR(S downto 0) Y + out STD LOGI VECTOR(2 downto 0) ds fond sarabit; architecture satsbit of satinit ie pore | 2+ dm STD LOGIC vECTOR(3 dowmto 0) B : 4m STD uOGIC-VECTOR(3 downto ©); 2 + dm Stb-Loare; Y 4 out STD_LOGIC_VECTOR(3 dowto 0} end’ component Signal co: STD_LOGIC; Signed ci : stD_Loote; Signal © «ST LOGIC; Signal xi + STD_Looze;, begin Urs mx24 Ore map(al0) => xi, a(2) => xk, 9(2) => xd, af) => x15), BIO) => x00), BGG) => x(a); BUa) => 3120, Bia} o> tah) ass a, ys vs en ex not (x(a) eee (91) Bi EE Bot (IS) G0 So Rot (EIS) or (4); er cd and cl end satense; A top-level design that ean be used to test sar4bit is shown in Fig. 11.2. The ‘module x7segb1/ is a modification of Listing 10.4 that will display only values between -8 and +7 on the 7-seyment display. Listing 11.2 shows the VHDL. program for the module x7segb/1.. The input to x7segb/1 is the 4-bit output (3:0) from sa/dbit, Note that only the two rightmost 7-segment display are enabled. The two leftmost displays are always blank, The hex7seg process in Listing 11.2 has been modified to display the ‘magnitude of the signed value of y(3:0) ~ 0 to 8. The preceding /-segment display will either be blank or display a minus sign. The quad 4-to-1 MUX and the new 2-t0-1 MUX are used to display the minus sign when aen(1) is enabled ify(3) is I; ie. ify is negative,Example 11 bn @3}- reali — }—Dao:0(60) 513) dp ‘saab cK.0) Figure 11.2 Topslevel design satai_top.no fr testing satbit Listing 14.2 x7eegbtt.vhd ~~ Example Lib: x/eeghil ~ teat aat@bie Library! TEES; ‘uae TREE.STO_LOGIC_UNSIGNED. all; entity x7eegb12 de pore y+ 4m STD_L0GIC_VECTOR(> downto 0); Sel + im StD_LOGIC;, clr + in S10 LOGIC; B.to.g + out STD _LOGIC_VECTOR(S dowto 0); |B: out STD_LOGIC_VECTOR(3 downto Cl; 4p + out sr0_Loare h fend x7sesb1) architecture xTeegb11 of x7segb11 is ‘signal msel: st0_Losrc; gnal 2.30: STO_LOGIC VECTOR(s downto 0); ‘Mgnal agi: STO_LOGIC_VECTOR(G dowto 0); ‘Signal ©: STO_LOGIC_VECTOR|1 downto 017 ‘gnel Gigit: 0D L607 VECTOR(2 downto 0); fignal sen: S10 LOGIC VECTOR (3 downto 0); begin == quad ¢-to-1 MOK: mutt hen "02" when °10" when others fend cases end pres --dieplay minus sign2s Complement 45 Saturtor 67 Listing 11.2 (cont) x7segh "T-segnent decoder: nex7se3 process digit) Degia case digit Se 010020" <= rao01000" when others => a_g0 <= "0000001"; fend poss 2-to-1 MU process (nzel) Begin 4 noel = "1" then sog cliaso cir > peng), ap => ap, yoy ) ss oikasy port map eikLs0 => ciki90, sis ss bent, elk => tele » eo70 Example 12 Example 12 Full Adder In this example we will design a full adder circuit Prerequisite knowledge: Basic Gates ~ Appendix C Kamaugh Maps ~ Appendix D ‘T-Segment Displays ~ Example 10 12.1 Half Adder ‘The truth table fora half adder is shown in Fig. 12.1. In this table bit cis added to bit to produce the sum bit s and the cary bit c. Note that if you add 1 to 1 you get 2, ‘which in binary is 10 or 0 with a cany bit. The BDE logic diagram, hulfadd/ be, for a half adder is also shown in Fig. 12.1. Note thatthe sum s is just the exclusive ofaand ‘band the carry ¢ is just a & 6. The VHDL program corresponding tothe circuit in Fi 12.1is shown in Listing 12.1. A simulation of halfadd bde is shown in Fig. 12.2 o » Pe Frawe 121 Truth able and logic gram hal b fora hattedéer Listing 12.1 halfada.vha == Example 12a; half adder 10, TERE, STD LOGIC 1164.11; fe ZEEE, GTD_LOGIC_uneigned. ald; entity nattaad te pore in stp tose; : in sTD_tocIc; end naifada;Full Adder n Listing 12:4 (cont) hatfedd.vhnd ‘architecture halfadd of halfaad ie begin ‘end haltaday Figure 122 Simulation ofthe haltadder in Fig 12.1 12.2 Full Adder When adding binary numbers we need to consider the carry from one bit to the next, Thus, at any bit position we will be adding three bits: a,b and the eaey-inc}from, the addition of the two bits to the right of the current bit position. The sum ofthese three bits will produce a sum bit, sj and a earry-out, e¢/, which will ‘be the carry-in to the next bit position to the let. This is called a fal adder ad its truth table is shown in Fig. 12.3. The results of ‘the first seven rows in this truth table ean be inferred from the ‘ruth table for the half adder given in Fig. 12.1. In all of these rows only two I's are ever added together. The last row in Fi 12.3 adds three I's. The result is 3, which in binary is 11, oF plus a carry From the truth table in Fig. 12.3 we can write a sum of products expression for s;as [ree ae aaa Figure 123 [ep a nag eo ‘Truth table fora fll adder lee as be ‘We can use the distributive law to factor out ~c; from the frst wo product terms and ¢; from the last two product terms in Eq. (12.1) t obtain ere Le me by | ye by [ete Cate bi | ate bu «a2.2)72 Example 12 which ean be written in terms of XOR and XNOR operations as ay non fa BY | aay 22.3) which further reduees to a) a2.) Fig, 124 shows the K-map for cj+7 from the truth able in Fig. 12.3. The map shown in Fig. 124a leads to the reduced form for c+ given by Sas eb Pore b for ea aaa.s) While this is the reduced form, a more convenient form can be written from Fig. 12.4b as fallows: cha sabe be | es Boag EBs | op Bay & By Sapem Pere Gaye | a 6 BL) Fal edi foie tay by) 2.6! @ Figure 12.4 K-maps for oj for full adgerin Fig, 62 From Eqs. (12.4) and (12.6) we can draw the logie diagram for a full adder as shown in Fig. 12.5, Comparing this diagram to that for a half adder in Fig, 12.1 itis elear that a {ull adder can be made from two half adders plus an OR gate as shown in Fig, 12.6. Figure 12 Logic clagram fora ull adrFull Adder mB a : ratacier_ (2 Bim) natoaaer na Figure 126 A ful adder can be made fom two half acer pus an OR gate From Fig. 12.6 we can create a BDE design, fidladd de, as shown in Fig. 12.7. ‘The VHDL program resulting from compiling this design is equivalent to that shown in, Listing 12.2. simulation ofthis full adder is shown in Fig, 12.8. Note tat the outputs agree with the uth table in Fig. 12.3. ut aD be halfadd u Figure 127 Block ciagram fulacd de fora fll adder Listing 12.2 fulladd. < pxample 2p: fullaaa Library 1865) ‘use TEEE.otd logic 1164.11; Ore a + dn erp Locrc; B: dn stb_Loare, ein in SF LOGIC; a 7 end’ fullada; architecture fulladd of fulladd te Component hal fadd pore 4n 1m _soac, An s1b_Loarc,74 Example 12 Listing 12.2 (cont) fulladdsv Bignal cl + ST2_L0GIC; Signal 62 : sto L0aIc, Signal #1 : STO_LoGIC, begin Oi narfaaa port aap Bins a, Bax by cos cl, e => oily port map a1, fond futladd: Te GR Seah ow Walon Gen Swain Wnwlow Tals Wnion ip (SE) Fee os RAsmAQae te Figure 12.8 Simuiaton of the fll adder in Fig. 12.7 ane Listing 12.24-8 Acder Example 13 4-Bit Adder In this example we will design a 4-bit adder. Prerequisite knowledge: Basie Gates ~ Appendix C Karnaugh Maps ~ Appendix D Full Adder ~ Example 12, 13.1. 4-Bit Adder Four of the full adders in Fig. 12.7 can be comt 75 ed 10 form a 4-bit adder as shown in Fig. 13.1. Not thatthe full adder for the least significant bit will have a carry- in of zero while the remaining bits get their eary-in from the earry-out of the previous bit. The final carry-out, is the cou for the 4-bit addition. The VHDL program ‘corresponding tothe 4-bit adder in Fig. 13.1 is given in Listing 13.1 Seon 101 Figure 121 Bock diagram atlord.bde fora 4-bit adder t—c0)78 Example 13 Listing 15.1 addord.vha ~ Exanple 13a: eddert Library’ EEE; use TSEE. std togic 1164.11; entity adders is port cin : tm sto toate; 2 1 dm STD_LOGIC_VECTOR(3 downto 0); >: dm STO_Loare_vecTOR(> downto 8); cout + out ST0_LOGIC: 1 out STD_LOGIC_YECTOR(3 dewto 0) iy fond adders; architecture adder of adder is Component fal lad Dore f a + 4a sro Locre; Bb: in smD-Losre; ein 1 4m ST0_Losic; Sout + out 8f0_108iC, f+ out STD. LOGIC ds ‘end component port. map( aes a2), > sas eas: bia), cfm => ©, cout => 63, v2: tulteaa port map( (3), b => B(3), elm =» 63, cout => cout, aa), va: tullaaa ‘pore map Sr> a2), b => BI}, cin => el, cout => 02, oa sas, ve: fulladd B'Es ao), b =» B(O), cin «> etn, cour =+ ct, eon end adaer4,4B Adeer ” A simulation of the 4-bit adder in Fig. 13.1 and Listing 13.1 is shown in Fig. 13.2 ‘The value ofa is incremented from 0 to F and is added to the hex value B. The sum sis, always equal to a +b. Note that the carry flag, cou, is equal to 1 when the correct ‘unsigned answer exceeds 15 (ot F). We can test the adder module from Fig. 13.1 and Listing 13.1 on the FPGA board by combining it withthe x7segb module from Listing 10.4 in Example 10 and the clkdiv module from Listing 8.2 from Example 8 to produce the top-level design shown in Listing 13.2. The 4-bit number sw(7:4) will be displayed on the first (leftmost) 7- segment display. The 4-bit number sw(3:0) will be displayed on the second 7-segment display. These two numbers will be added and the 4-bit sum will be displayed on the fourth (right-most) 7-segment display and the carry bt will be displayed on the third 7- segment display. Try it. Figure 13.2 Simulation ofthe 4-bit adder in Fig. 18.1 and Listing 13.4 Listing 13.2 adderé top.vhd ~- Example 13b: adders top Library THES; fuse TERE. STD_LOGIC_a164.a11; eneity eddext_top de pore ben + 4m STD_LOGIC_VECTOR(9 domto 3); se: 4m STO LOGIC VECTOR(7 downto 0); ato qi: oue STD LOGIC VECTOR(s downto 0}; an: out sto Locic vecToR(s downto 0)? ap : out sto vocre; 28: out STO_LOGIC!vecTOR(7 downto 0) d ena adders_top;Te example 13 Listing 13.2 cont) addord top.vha architecture acders_top of addaritop ie component added de ‘pore fein + dm srp_Lostc: a+ dn STD LOGIC VECTOR(3 downto 0); 5: 4m STD LOGIC VECTOR(3 downto 0); cout’: out eTD EAare, 5 out STD_LOGIC_VECTOR(3 downto 0} de end component component x7segb is pore x + Am STD_LoGre_vEcTOR(5 downto 0); tik 1m S1D_LOGTC; clr : am s10_Locrc; a.to_g + out STD_LOGIC VECTOR (s downto 0); ab: out S1D_LOGIC_VECTOR(3 downto 0): @p + out sr0_Locre fend component) component clkdive Le pore elk + im sto_tostc; ele + im st? tose; ‘elki90 1 out S1D_LoGzC ” signal lk190, lr, e4, cin: st0_Loarcy Signa x: S7D LOGIC VECTOR|16 downto 0) ‘gael oun: STO_LOGIC_VECTOR(3 downto 0); begin cin ox(7 domte 4), B ‘cout => ef, 2 > sum; 2v(2 dowto 0) 2s wieegb port map (es xr clk => e1k190, clr => clr, atog => atog, 3s etkdive port map (welk > eclky ele ele, elki90 => eln90) ; fend adsers_topsNt Aor 7% Example 14 N-Bit Adder In this example we will design @ N-bit adder. Prerequisite knowleds “Bit Adder — Example 13, 14.1 4-Bit Adder: Behavioral Statements Te would be convenient tobe able to make a 4-bit adder (or any size adder) by just using a sign in a VHDL statement. In fact, we can! When you write a = 6 in a VHDL, program the compiler will produce a full adder ofthe type we designed in Example 12. ‘The only question is how to create the output carry bit. The trick isto add a leading 0 to ‘and # and then make a S-bit temporary variable to hold the sum as shown in Listing 14.1, ‘The most-significant bit ofthis 5-bit sum will be the carry flag A simulation of this program is shown in Fig. 14.1. Compare this with Fi 12. Listing 141 addorab.vhd ~~ Example Léa: 4-Biv behavioral alder eneity adderad be pert 5 4m STD_LOGIC_VECTOR(2 downto 0) 4m StD_Losrc_vecToR(3 downto 0) + out §TD_LOGIG_VECTOR(3 downto 0); ff: out ST5_LOGIC y architecture adderéb of adder 4 begin precess(a, ) ‘variable temp: STD_LOSIC_VECTOR(4 downto 0) temp r= (10 ea) + (10! B)80 Example 14 Figure 14.1. Simulation ofthe VHDL program in Listing 144 14.2 N- Bit Adder: Behavioral Statements Listing 14.2 shows an N-bit adder that uses a generfe statement. This is a convenient adder to use witen you don’t need the carry flag. An example of using this as an 8-bit adder is shown in the simulation in Fig. 14.2. Note that when the sum exceeds FF itsimply wraps around and the cary fag is lost Listing 14.2 adder.vhd == Example 4b: WIE adder Library IESE: Use TEEE.S7D_LOGIC_uneigned a1; sey adsor 42 Generic (Wvinteger := 8); pore a+ dn STD LoGre _vucroR (-1 downto 0); Bo: 4m sqo-LoGrc_vacroR N-1 downto 0); Y¥ + out STD_LOGIG_VECTOR +1 downto 0) » ond adder: echitecture adder of adder t= Besta Begin (a,b)sit Ader Bt ea mo ee ee Se ee ee 7 SO oe spate aagg vim ealae 4 Figure 142. Simulation of he VHDL program in Listing 142 ‘The top-level design shown in Fig. 14.3 can be used to test this Nbit adder on the FPGA board. In this ease we are adding two 4-bit switch settings and observing the sum ‘on the 7-segment display. To set the parameter W to 4 rightclick on the adder symbol, select Properties and click on the Parameter tab. Set the actual value of N to 4 a J—Bee-060) not an) 1 van of oD ievnsef rE ee a) Figure 14.3 Topevel design for testing the Nit adder on the FPGA boards2 Example 15 Example 15 N-Bit Comparator In this example we will design a N-bit comparator. Prerequisite knowledge: 'N-Bit Adder ~ Example 14 15.1 N-Bit Comparator Using Relational Operators ‘The easiest way to implement a comparator in VHDL isto use the relational and logical operators shown in Table 15.1. An example of using these to implement an N-bit comparator is shown in Listing 15.1. A simulation of this program for the default value of N= 8 is shown in Fig. 15.1 Note in the process in Listing 15.1 we set the values of gf, eq, and It to zero before the if statements. This is important 10 make sure that each output has a value assigned to it If you don’t do this then VHDL will assume you don’t want the value to change and will include a latch in your system. Your circuit will then not be a ‘combinational cireuit ‘Table 18:1 Relational and Logical Operators ‘Operator ‘Meaning. 5 Tegal equality 7 Togical inequality = Less than s (Greater than ar equal noe Logical negation ad AND cs Logical OR Te a Sam lor Wines Goan Sus Wawona Wan Be RQLBeQAg w Figure 16.1 Simulation of the VHDL program in Listing 15.4Nit Comparator 83 Listing 15.1 comp.vha c= Example 171 Nebit conparator using Felational Operators ‘use IBEE.S7D_LOGIC_1164.811; entity comp Le generse (li:integer := 3) pore + Am STDLOGIC VECTOR N-1 downto 0) Se + out S70 Lore: q+ out ST0_LoGIC: fend comps architecture comp of coup ta process ix, begin ey i ‘You can test this comparator on the FPGA board by ereating the BDE block diagram comp4_top.hde shown in Fig. 15.2. To make this a 4-bit eomparator right-click ‘on the comp symbol, select Properties, click on the Parameters tab, and set the actual value of Vo 4. You will be comparing the 4-bit number x(3:0) onthe left four switches, with the 4-bit number (3:0) on the right four switches. The three LEDs {d(42) will, detect the outputs, eq, and It. We selected these three LEDs because on the BASYS board they are three different colors. Compile the design comp top. bie, implement it, and download the .bir file to the FPGA board. Test the comparator by changing the switch settings us 8) Logg alt su) —fona0- [| ise) LO ts2) i) comp Figure 15.2 Topievel design comp4_top.bde to tet abit comparator8 Bxampe 16 Example 16 Edge-Triggered D Flip-Flop In this example we will define an edge-triggered D flip-flop and show how to design one using only NAND gates Prerequisite knowledge: Basie Gates ~ Appendix C ‘Example 8 Clocks and Counters 16.1 Edge-Triggered D Flip-Flop with Set and Clear The logic diagram and truth table for a positive edge-triggered D flip-flop with ‘synchronous set and reset inputs are shown in Fig. 16.1. The upwvard arrow for the CU signal in the truth table indicates that itis a positive edge-triggered flip-flop. ‘This is also indicated by the arrow-type symbol next to the CLK input in the logic diagram. A negative edge-trggered flip-flop would have a bubble added to the CL input. Figure 16.1 Logic diagram for an edge-tiggered D flop with asynchronous set and reset [Note thatthe behavior ofa positive edge-triggered D flip-flop is thatthe value of D gets latched to Q on the rising edge ofthe clock, CLK. Ifthe sot input Sis 1 the output, Qs set to 1 asynchronously, i., regardless ofthe value ofthe clock input. Ifthe reset input Ris I the output Q is cleared to 0 asynchronously. IF both S and R are zero then the ‘output Q changes only on the rising edge of the clock ~ and is st to the eurrent value of the input D. ‘There are many ways to make a D flip-flop. The circuit shown in Fig, 16.2 that contains six NAND gates will hehave like a 9 flin-flap with asynchronous sot and clear. ‘You can create this D flip-llop using the Active HDL BDE. Figure 16.3 shows the simulation ofthis die design. Note from this simulation thatthe cicuit does indeed behave like D flip-flop in which the output g gets latched tothe value of D on the rising ‘edge of the clock, clk. By following all of the internal signals in this simulation you can ‘race exactly how this cieuit works. ‘We saw in Fig. 1 of the Introduction that each of the four slices in each CLB of a Spartan-3E FPGA contains two D flip-flops. The BASYS board contains a. Xilinx Spartan3E-100 TQ144 FPGA with 960 slices and 1,920 flip-flops. The Nexys-2 boardEdge Triggered O Fiprlop 85 contains a Xilinx Spartan3E-S00 FG320 FPGA with 4,656 slices and 9,312 flip-flops. Each U/O block connected o the FPGA pins contains two additional flipflops. Thus you have thousands of flip-flops available for you to use in your FPGA designs. aioe Re eceersnort| ee crea Figue 162 Making an edge-rggeres Dfipop with asynchronous et and reset using NAND gates Eee Sah io wala Rom Sain waa Do a ae melosfratelaeaelty Figure 16.3 Simulation ofthe D fip-fop offbde in Fig. 182Example 17 D Flip-Flops in VHDL In this example we will show how to implement a D flip-flop using VHDL. Prerequisite knowledge: Example 8 ~ Clocks and Counters Example 16 ~Edge- Triggered D Flip-Flop 47.1 D Flip-Flops in VHDL In Example 16 we showed that an edge-triggered D flip-flop could be implemented using only NAND gates and that FPGAS contain thousands of D flip-flops ‘that are implemented in a variety of specialized ways. These D flip-flops normally have aan asynehronous set and clear and behave the same as the simulation in Fig. 163 in Example 16, ‘The way to tell VHDL that you want a positive edge-triggered D flip-top is to describe its behavior in a process that includes an #f statement containing the phrase rising_edge(elk) or efk’event and clock = '1' in the elsif clause as shown in Listing 17.1 The use of ether ofthese phrases is what tells VHDL to use the D flip-lop in the FPGA. Note that ifefr is equal to “I” then q will immediately (asynchronously) become *0'. If clr is not “1° then on the rising edge ofthe clock signal, eZ the value of g will be set to the current value of D, which is exactly the behavior of a positive edge-triggered D flip flop. A simulation of Listing 17.1 is shown in Fig. 17. Listing 17.4 tthe = example 11: D flip-flop with clear Library TBE; entity DEF se port elk + 4m S7D_LoGre; clr : 4m s7b_Loare. Dt dn ero tocre, ena vee: architecture DEf of DEE se bosin Begin Se(ele = 12") chen gen 10) leit (zing edge(cik)) then ae jelk, ele)Flip Fops in VHOL 7 Ee Sea oe wae ae Sema Utena wr « SO) velo oarweQaaiuvrRes an 4a" (er Figure 17.1. Simulation ofthe VHDL program in Listing 17.1 “The BDE symbol for the D flip-flop described in Listing 17.1 is shown 17.2. We will show in Example 18 how (0 use this D flip-flop to create a divide-by-2 counte ut bf Figure 172 8DE symbol forthe D fip-op described in Listing 17.12 Example 18 Example 18 Divide-By-2 Counter In this example we will show how to use a D flip-flop to ereate a divide-by-2 counter. Prerequisite knowledge: ‘Example & ~ Clocks and Counters Example 17 -D Flip-Flops in VHDL. 18.1 Divide-by-2 Counter Consider the D flip-flop with output 40 shown in Fig. 18.1 where we have connected ~0 to the D input of te flip-flop. What will happen? On each rising edge of the clock, the value at D will be latched (after some propagation delay) to 40. Suppose that 90 is intially 0. This means that ~g0 will be I. At the first clock, this ~q0 value of 1 (whieh is at D) will be latched to g0. Therefore, 40 will go from 0 10 1 and ~40 will go from 1 to 0. This means that D will now be 0 so that on the next rising edge ofthe clock, the value of gO will go back to 0, and ~g0 will go back to 1. This process will continually repeat itself, resulting in the frequency of gO being just one-half of the frequency of the clock. We call this a divide-by-2 counter because it divides the frequeney of the clock by two. ole © 00 Figure 18.1 Using 2D fipop as a dvide-by-2 counterDivde-By-2 Counter 80 ‘A top-level BDE design for this divide-by-2 counter is shown in Fig. 18.2 where wwe have used the clock divider from Example 8, We will use a 3 Hz. clock output elf from the clock divider. This elock signal will goto [a(3) and the ouput ofthe divide-by-2 counter will go to /d(2). simulation of this divide-by-2 counter i shown in Fig. 183. I'you implement this design on the BASYS FPGA board the green LED, Za(2), will blink athalf the frequency of the yellow LED, ld(3). Try it vince) clk Figure 183 Simulation ofthe civideby-2 counter in Fig, 18220 Example 19 Example 19 Registers In this example we will show how to use a D flip-lop to create a I-bit register. We will then use two ofthese I-bit registers to form a 2-bit register. Prerequisite knowledge: ‘Example 8 ~ Clocks and Counters Example 17 -D Flip-Flops in VHDL. 19.1 1-Bit Register In Example 17 we sav thatthe D flip-flop can be used to store abit. 1FD is high then on the rising edge ofthe clock the output q ofthe D flip-flop will become 1. If Dis, Jow then on the rising edge of the clock the output q ofthe D flip-flop will become 0. In real digital systems the clock input to a D flip-flop is normally on all the time, This means that on every rising edge of the clock (usually millions of times per second) the current value of D will be latched to g. How ean we make a I-bit register that will load a value (0 or 1) from an input line inp only when we want to? We will add another input Tine ealled ‘oad that is brought high when you want to load a value from inp, and on the next rising edge of the clock the value of inp willbe stored in g. ‘The BDE logic diagram shown in Fig. 19.1 will do this foae bp" Pood nits inp cn on mms | ig ‘The clock signal is assumed to be running continuously and so in order to keep the current value of q unchanged at each clock cycle, this g value is fed back and gated into the OR gate with ~Zoad. This means that when the load signal is LO the value of g is continually reloaded and therefore does not change. When foad is brought HI the value inp is gated to the OR gate so that on the next clock eyele q becomes equal to inp. When the (oad signal goes ZO again this value then remains at g. A simulation of reg/bic Bde is shown in Fig. 192be aa oo ine ep Ekin owen Le am ~hQtw @QQe ts ) ‘ “sil Figure 182 Simulation of he tit register rag bitbde in Fig. 18.1 ‘The logic symbol for this I-bt register is shown in Fig. 19.3. In the next seetion ‘we will combine to ofthese I-bit register modules to form a 2-bit register. ut regibit Figure 18.3 Logie symbol fora t-bt register 19.2 2-Bit Register ‘We can combine two of the 1-it reyister modules shown in Fig. 19.3 with common load clr, and ci signals to implementa 2-bit reuistr called rg2bi as shown in Fig. 19.4 A simulation of reg2bitée is shown in Fi 198. Note that when the Toad sighal is high the two bits inp(1:0) got latched into the repster outputs q(10) on the next sng edge ofthe clock “To test this 2-bit register on the FPGA board you ean create the top-level design shown in Fig. 19.6 and download the resulting bit file to the FPGA board. Pressing byn2) wil display the switch sting s¥(1:0) on the two rightmost LEDs. Note that this clock is running at 50 MHz but switch values get stored in the register only when the Joad signal is highExample 18 el at at) ‘ng toad ee Figure 194 A 2b register rog2bit bo ee ah ay Wa a Sa Raa Te LE Pee) sazwaaae|uun” Figure 195 Simulation ofthe 2-it register reg2bibde shown in Fig, 19.4 ut magi —fs «oo ie( 9) se OP iin(32) reqabi Figure 198 Top-level design reg2bi_top.bde or testing egNit Registerin VOL 98 Example 20 N-Bit Register in VHDL In this example we will show how to make an N-bit register in VHDL and test it fon the FPGA board, Prerequisite knowledge: ‘Example 17 ~D Flip-Flops in VHDL. Example 19 ~ Registers 20.1 N-Bit Register In Example 19 we saw how to make a 2-bit register using two I-bit registers. To make an N-bit register it is easier to generalize the VHDL. program we used in Example 17 to make aD flip-lop. For an N-bit register, if load is 1 then on the next rising edge of the clock elk the N-bit input A(N-1:0) is latched to the N-bit output q(N-1:0), A VDL. ‘program for this egistr is shown in Listing 20.1. A simulation ofthis progeam for N= 8 is shown in Fig, 20.1 Listing 20.1 rogistervhd Beampie 20: An WEE Fe use TEEE.STD_LOGIC_1164,a12; entity rea te generic (tsinteger s+ 8); pore toad + tm st_LoGre; clk + im sto Zoere; elz : in sto_tostc, 4+ dm S10 L6GIC_VECTOR(N-1 dowto 0} 4 + eu STO LOGIE VECTOR(N-2 downta 0} Ms ond rogister; begin process (clk, cls) st cle + nen qc (others => 10"); eleie cikvevent and clk = /1! then ie toaa'= "1" then ge;84 Example 20, Note the use ofthe generic statement in Listing 20.1, which defines the bus width Nito have a default value of 8, We can override this value and make it 4 by right-clicking ‘the register symbol in the top-level design in Fig. 202, seleting Properties, clicking on the Generics tab, and changing the actual value of N10 4 Generate’ the top-level design using the BDE in Active-HDL, implement the design, and download the bit file to the FPGA board, When you press byn(2) the switch settings will be loaded into the register and the register contents will be displayed on the 7-segment displays. Note that although the register clock isthe 50 MElz metk, data will be loaded into the register only when the load signal is high. le EAE Sencch wow wixtopace Gesgn mulation Waveform Toale window Hep [SOs Beos[RaeweaQeg win” a (| Figure 20.1. Simulation ofthe VHDL program in Listing 20:1 tis 21> rs) | —B2.t9:460) fe oof —Bana) a6) of Sap rc i) Figure 20.2 Topuevel design regiser_fop bd for testing register. vdShit Registers 6 Example 21 Shift Registers In this example we will show how to make a 4-bit and A-bit shift register in VHDL. Prerequisite knowled ‘Example 17 —D Flip-Flops in VDL. Example 19 — Registers 21.1 4-Bit Shift Register An Nsbit shift register contains N flip-flops. At each clock pulse data are shifted from one flip-flop to the next. A 4-bit shift register called shif.bde is shown in Fig 21.1. Serial data in the form of a string of bits is fed into the lefi-most flip-flop via data_in. At each clock pulse whatever is at dara_in is moved to 4(3), the old value at {gG) goes to 4(2), the old value at (2) goes to g(1), and the old value at q(1) goes to 4(0) [Note that all data values are shifted simultaneously on the same rising edge of the lock, A simulation of this shift register is shown in Fig. 21.2. } a0) of EE Figure 211 A Abit shit register shits bdo ‘The 4-bit shift register shown in Fig. 21.1 can be modeled using the VHDL program shown in Listing 21-1. In the shift register program shown, we used the 10 signal assignment statements: ae(2) <= data_in, ‘G6(2 downto 0) <= ge(3 downto 2); ‘These two statements are equivalent to (3) <= data_iny ga) = 40) qn) 10") elete Gik'event and clk 11! then 2 downs 8) oe gele-a downto 3); ena is) Gena: fen suittneg, 7 it shit68 Examplozz Example 22 Ring Counters In hs example we wil show how to make an Nbit rng counter in VHDL and lestit onthe FPGA bose. Prerequisite knowledge: Example 17 ~D FlipFlps in VHDL Example 2 ~ Shift Registers 22.4 Ring Counter Ifthe output 4(0) in the shift register in Fig. 21.1 is connected back tothe input of the q(3) Mlip-lop, and if only a single | is present in the four flip-flops, we have what is called a ring counter as shown in Fig, 22.1. We will initially set q(0) to 1 by connecting the cir signal to the ser input of flip-flop q(0) rather than to the clr input. The single 1 in this ring counter is continuously eycled around all four Rip-lops. This means thatthe ‘output 4() on each flip-flop will go H/ once every four clock eyeles — but this pulse will be out of phase by one clock eyele from one flip-flop to the next. We will therefore have generated a 4-phase clock that can be used asthe basis for various timing circuits. Figure 22.1.4 4-bitring counter 22.2 N-Bit Ring Counter A VHDL program for an N-bit ring counter is given in Listing 22.1. Note that ‘when cir is equal to T the value of gis set 1; Le. g(0) 1s 1 and all other values of g(t) are zeros. The simulation of this VHDL program forthe default value of N = 4is shown in Fig. 22.2. Note how the four signals q(3:0) form a 4-phase clock at“ the frequency of ‘the input clock, clk. To test the ring counter on the FPGA board the top-level design ringS_top.bde shown in Fig. 22.3 will eause a single bit to cyele around all eight LEDs. You can set the value of the generic parameter N’to 8 by right-clicking the ring symbol in the top-level design in Fig. 22.3, selecting Properties, clicking on the Generis tab, and changing the ‘actual value of N08.Ring Counters sting 224 ring vhd Example 22; N-bit ting Comte? Library TEE; generic (W:integer == 8); pore elk + tn sro toate, ele : 4a sto LoGrC, | BF Sut STD_ 22016 vecron ra domes 0) fend ing: Signal gs: STD_LOGIC_VECTORIN-1 downto 0); begin (elk, ele) sf clr = 10! then ‘ge <= (others => "0; gor aay elsif lk'event and clk = '2' then geal < gal0); Ge(-2 downto 0) <= ge(Qt-2 downto 2); [oe |tmelocfrasp aaa wut mie” ae CCC ee leet LL ra roms fT e3_ tt a. + (reel 22 foe as eo nal =a = FI =. rr Py ‘ sisiois ss Feral Figure 222 Simulation ofthe VHDL program in Listng 22.1feet 0 Figure 22.3 Top-level design rng_top.bde for esting rng ln ‘angJonnson counters 101 Example 23 Johnson Counters In this example we will show how to make Johason counter in VHDL and test it fon the FPGA board, Prerequisite knowledge: ‘Example 17 ~D Flip-Flops in VHDL. Example 21 ~ Shift Registers 23.1 N-Bit Johnson Counter ‘A 4-bit Johnson counter is shown in Fig. 23.1. ‘The clr signal will cause all q() foutputs to be zero. The value of -4(0) is fed into the D input of (3). A VHDL program for an NV-bit Johnson counter with a default value of = 4 is given in Listing 23.1. A simulation of the 4-bit Johnson counter is shown in Fig. 23.2. Figure 222 Simulation ofthe VHOL program in Listing 23.1102 Example 23, Listing 231 johnson.vhd “= Gample 23: fi-bit Jonneon counter Library’ TEE; ‘ise TBEE.STD_LOGIC_1164.011; eneity johnson te Generie Wsinteger s+ 8); port elk + sn S10 toate, sls + im store, 4G + ue ST0_[0GIC_YECTOR(W-1 dowate 0) fend johneon; architecture johneon of johnson te Signal gs: STD_LOGEC_VECTOR(N-1 dowto 0); begin -+ Nobst Johnson counter processiclk, clr) Begin’ At clr = -2" enen ge <= (others => 10"), etaie Slivevent and clk = "2! then elwe1) <= not gaia); GelW-2 downte 0} <= ena i; (o-1 downto 1); ‘end jotnson! To test the Johnson counter on the FPGA board the top-level design Joknson8_top.bde shown in Fig. 23.3 will cause the eight LEDs to display the output of an 8-bit Johnson counter, Remember to set the value of the generie parameter W to 8 by rightclicking the johnson symbol in the top-level design in Fig, 23.3, selecting Properties, clicking on the Generics tab, and changing the actual value of N to 8 bin3 OE) u2 ut foe ena) +f a0-to—Eidt 7.0) rcikt>——+ ron Lb clk johnson Figure 23.3 Top-tevel design johnson8_top be for testing johnson vidDebounce Pushoutons 108 Example 24 Debounce Pushbuttons In this example we will show how to debounce the four pushbuttons on the FPGA, board Prerequisite knowledge: Example 17 —D Flip-Flops in VDL. Example 21 ~ Shift Registers 24.1 Debouncing the Pushbuttons ‘ips haat dn seat eSrenets ee eee ae cea enema ere D™ Figure 24.1 Debounce cut Listing 24.1 is a VHDL program that implements four versions of the debounce circuit in Fig. 24.1 ~ one for each of the four pushbuttons on the FPGA board. You ean understand how this debounce circuit works by looking at the simulation shown in Fig. 24.2 where a bouncing input signal is used as a stimulator for inp(0). We have indicated bouncing on both pressing and releasing the button. Note thatthe resulting ouput signal ‘owip(0) isa clean signal with all bouncing effects removed. ‘The output will not go high nti the input has been high for three clock eycles. The output will stay low as long as any bounces do not remain high for three clock eyeles. Thus, its important to use alow frequency for cefk to make sure all debounces are eliminated,104 Example 24 Listing 24.1 debounced.vha = example 24: debounce @ pushbattons Library 1555; ‘use IEEE, STD. LOGIC_a166.a11; fentity debounces te port Anp + in S70_LoGIc_YECTOR(? downto 0) ecik + in S19 10010, clr + in 870 L00r¢; utp + out S70 LOGIC vECTOR(3 downto 0} rs fend debouneed architecture debouncet of debounces ie Signal delayi, delay2, delays: STD_LOGIC_VECTOR(3 downto 0): begin process(celk, cle] begin Selay2 <= eiays e= *0000"! etett celk'event and cclk = "1" then Gelayt <= impr Gelaya <= delay; Seisy) So delay? end if; fond proc: fend debounced: ‘olay and delay2 and delays; ee ao ie wae Gan Sue oon To ae [eG] se[oo[eaem aaaaiwunale alae a Figure 242 Simulation of the VHOL program in Listing 24.1Clock Puse 105 Example 25 Clock Pulse ral is example we wl show how to generate a single clock pulse when a pushbutton is presse Prerequisite knowledge: Example 21 ~ Shift Registers Example 24 ~Debounce Pushbuttons 25.1 Generating a Single Clock Pulse A very useful circuit that will produce a single clean clock pulse is shown in Fig 25.1. The only difference from the debounce circuit in Fig. 24.1 is that the complement (of delay3 is the last input to the AND gate. Listing 25.1 is a VHDL program for this erp oh 2 fs es sex] a. t0 (00) Lf rent anc0) x8 ley Bae Boog Figure 25.3 Top-evel design clock_pulse_top.bae for testing clock_pulse vioAira Woven 107 Example 26 Arbitrary Waveform In this example we will show how to generate an atbitrary waveform that repeats itself every 16 clack cycles. Prerequisite knowledge: ‘Example 8 ~ Counters Appendix D ~ Karnaueh Maps 26.1 Generating the Morse Code for EAT ‘You own a restaurant and want to puta sign out in front that says EAT. But you only have a single light bulb. So you decide to blink the word EAT in Morse code! ‘The Morse code for E is dot, for A is dat-dash, and for Tis dash, Therefore you need to blink dot: dot-dash: dash in Morse code. ‘We can use the output of a 4-bit counter as the input to a combinational logie cireuit with output eat. For a dot the output will be high for one clock eyele. For a dash the output will be high for thee clock eyeles. The truth tle to generate the Morse code for EAT is shown in Fig. 26.1 9 ° ° ° Figure 26.1 Truth table for generating the Morse code for EAT The logic equation for ear can be found by using the K-map shown in Fig. 26.2. ‘The resulting logic equation is shown in the VHDL. proy 26.1. Figure 26.2 shows a top-level design that will blink the Morse code for EAT on (0) on the FPGA board. ‘Try itExample 26 Figure 282. Karnaugh map forthe truth able in Fig, 2.4 Listing 26. eatvhd ~~ Example 26: Norae code for EAT Library’ TEBE; eneity eat te q+ dm STD_LOGIC_VECTOR(3 downto 0) Sees out S1D_LoGie y fond eat; architecture ost of eat 4 feat <= (not g(3) and not g(2) and (1) and q(0)) or (q(2) and q(2) and not q(0)) or (q(3) and q(2) and 4(0)) for (q{3) and not q(1) and a0) oF (g(2) and not g{2) and act g(0)); fend oat a eee oa HO elk Mo) lid MC) “counter bin’) >——4 Figure 2.3 Top-ovel design at_Iop.bde for generating the Morse code for EATPulses Madison (PAN) 108 Example 27 Pulse-Width Modulation (PWM) In this example we will show how to generate a PWM signal that can be used to control the speed of a DC motor Prerequisite knowledge: ‘Example 8 ~ Counters Example 15 ~ Comparators 27.4 Controlling the Speed of a DC Motor When connecting a motor or some other load that may draw significant current to 2 digital circuit such as a CPLD, FPGA, or microcontroller a separate circuit and power supply are needed, The speed of « DC motor depends on the voltage applied tothe motor = the higher the voltage the faster the motor will tum. The polarity of the voltage ‘connected tothe motor will determine which way the motor turns. Ifyou want to be able to change the direction of the motor using a digital circuit you will need to use an H- bridge. Digilent sells two Prod H-bridge modules that make it easy to plug into the 6 pin connectors on the BASYS or Nexys-2 boards. ‘The basic idea of how an H-bridge works ean be seen from the diagram shown in Fig. 27.1. We show four relays inthe legs ofthe H with the motor connected across the center of the H. The two top relays A and B are normally closed (where a high signal will open the relay) and the two bottom relays C and D are normally open (where a high signal will close the relay). In areal H-bridge these relays will normally be replaced with MOSFET transistors, “STS Figure 27-1. An H-bridge circuit can contrl the speed and drecton of @ OC motor110 Example 27 In Fig. 27.1 itis assumed that the two digital inputs Dir and pw are both high In this case relays A and D ate both closed and relays B and C are bath open. Curent therefore flows through the motor from let to right in the figure as shown. This wil cause the motor to rotate, sy, clockwise. Assume now thatthe Dir input is brought low with pum remaining high. This will eause relays B and C to close and relays A and D to fpen. Curent will now flow through relays B and C and go through the motor fom right 10 left in the figure. This will eause the motor rotate counterclockwise. Thus, the Dir Jnput controls the dieetion ofthe motor "To control the speed of a DC motor using a digital circuit one normally uses a pulse-width modulated signal ofthe type shown in Fig. 27.2. The period ofthis pulse train remains constant and the width ofthe high time, called diay in Fig. 27.2, is varied ‘The duty cycle of a PWM signal is defined as the percent time that the signal is high ‘Thats, day iy eyele = MH 100% Gav ope iad = te duty [ Figure 27.2 A pulse-width modulated signal ‘The average DC value of the pum signal in Fig. 27.2 will be proportional to the duty eyele. A duty cycle of 100% will have @ DC value equal to the maximum value of the pwm signal. A duty eycle of $0% will have a DC value equal to half of the maximum value of the pwm signal, and so forth Ifthe voltage across the motor is proportional to this pwm signal, then simply changing the pulse width dzy and therefore the duty cycle ‘changes the speed of the motor. If this pwm signal is connected to the pwn input in Fig. 27.1 then when the pwm signal is high the motor is connected to one leg of the H-bridge. However, when the pwm input in low then all relays are open the it is as if we removed the motor from its power source. Thus, the average DC voltage across the motor will depend on the duty cycle of the pwm signal where increasing the duty eyele ofthe pw signal will increase the speed (of the motor. 27.2 Generating a PWM Signal In this section we will show how to generate a pulse-width modulated (PWM) signal of the type shown in Fig. 27.2 using VHDL. To show how you might generate such a pwm signal consider the simulation shown in Fig. 27.3. The basic idea isto use ‘counter (a 4-bit counter is used for illustration in Fig. 272) and have the prem signal go high if the count is less than dluyy and goes low otherwise, The counter will be reset 10 zero when the value of coun is equal to period 1. In the simulation shown in Fig. 27.3Puse-Wlatn Moduaton (PWM) 111 the value of duty is 4 and the value of period is 13 (or hex D). The VHDL program that produced the simulation in Fig 27.3 is piven in Listing 27.1. [ae ea tat oe woes Geo Solna Hoon Te a pasa eaaga Library’ TERE; ‘use TREE. STD_LOGIC_wnesgned.al1 entity peng ie generie( M+ integer := 16); pore ele + 4a sto toate; elk + 4m sto_Loore, Guty + in St LOGI¢_vecToR N-1 downts 0) period : im STD_LOGIC_VECTOR|H-1 dowate 0): , im # owe Sr0_tesre architecture pung of pom 1s Signal count: STD_LOGIC VECTOR(W-1 downto 0) begin elka: process (clk, clr) -- d-bit counter begin Af cle = 11) then count <= (ethers => '0") Af count = period — 1 then ‘Sount <= (others == 10" end tes . ena ie;112 ample 27 Listing 27.4 (cont) pwmg.vhd ‘pewout: process (count) begin Af count < duty then oo Pim <= 10"; ena ie, fend proce imout : 27.3 Generating a 2 kHz PWM Signal Suppose we wish to generate a 2 kHz PWM signal to control the speed of a motor. The period in this ease will be 0.5 ms. Starting with the 50 MHz clock on the FPGA board we see from the clock divide frequencies in Table 8.1 of Example 8 that _g(14) has a period just over 0.5 ms (0.65536). We could therefore use an 8-bit_ counter driven by the clock frequency 4(6) (390.625 kHz) to control the PWM signal. This will allow us to set the period to 0.5 ms by choosing a value of period equal 10 period = (0.5/0.65596)+255 = 195 [C3 hex) ‘The value of duty could then range from hex 00 t0 C3. ‘The simulation shown in Fig. 27.4 uses a clock frequency of 390.625 kHz. with an 8-bit counter (\V= 8) and shows. ‘that this results in a2 kHz PWM signal. If you were to use such a PWM signal to contral the speed of a DC motor using a Pmod H-bridge from Digilent with the BASYS board you would output the pwm signal through one of the expansion connectors labeled JA, 4B, JC, and JD. Four pins on each connector are connected to the FPGA pin numbers shown in Table 27.1. If you were to connect the H-byidge module to connector JA the Dir signal would be connected 10 JA1 from FPGA pin 81 and the pw signal would be connected to JA2 from FPGA pin 91. You would need to add these two signals and pin numbers to the Basys2.nef file ‘Table 27.1 Pin numbers fore BASYS board expansion connectors 8 ac ro TTF TspatipeTape ie syat sey sya BLL ere [ee far | as [as [ee | 7 | as | 76 | as | 75 fe | 74 |e Figure 27.4 Simulation of a2 kHz PWM signalCContoting te Poston ofa Seno 113 Example 28 Controlling the Position of a Servo In this example we will show how to generate a PWM signal that ean be used to control the position ofa servo, Prerequisite knowledge: Example 8 ~ Counters Example 27— PWM 28.1 Controlling the Position of a Servo using PWM A servo motor is special type of device that contains a DC motor some gears, a potentiometer, and lectronie cireuitry for position feedback conteo, all packaged in a single compact deviee. These servos are widely used in model airplanes and radio controlled cars and are therefore mass produced and yey opener! sof ti pe te |g Futaba $3004, is shown in Fig. 28.1. This servo has three wires attached to it: the red wire goes to +5 volts, the black wire goes to ground, and the white wire goes 10 a PWM signal that contols the position Figure 261 of the motor shat. ‘The Futaba $2004 servo ‘The motor shaft is prevented from moving more than about 90 degrees by limit stops. The PWM signal used to control the position ‘of a servo is shown in Fig. 28.2. Note that the period is fixed at 20 ms and the pulse ‘width varies from about I-1 ms to 1.9 ms in order to move the shaft postion through a total angle of about 90 degrees. Fes nm fe seen sen im Figure 28.2 PWM aignal for contaling the postion ofa servo114 Example 28, The VHDL program given in Listing 27.1 in Example 27 can be used to generate the PWM signal in Fig. 28.2. Starting with the 50 MHz.elock on this board we see from the clock divide frequencies in Table 8.1 of Example & that q(19) has a period just over 20ms (20.97125). We could therefore use 16-bit counter driven by the clock frequency 44) G.125 MHz to control the PWM signal. This will allow us to set the period t0 20, ims by choosing a value of period equal to (20/20.97225) #65535 2500 (F424 hex) In this ease the value of duty in Fig. 27.2 would be about 4688 (1250 hex) for the neutral position, 3438 (D6E hex) for the +45 degree position, and 5938 (1732 hex) for the ~45 degree position. A simulation of the VHDL program in Listing 27.1 for N'= 16 and a value of period equal to 62500 (F424 hex) and a value of duty equal to the neutral position of 4688 (1250 hex) is shown in Fig. 28.3. Note that the pulse width is 1S ms and the period is 20 ms, Digilent sells a Pmod servo connector that makes it easy to connect servo motor to the BASYS or Nexys-2 boards. Figure 28.3 Simulation of PWM signal fr sero control,Scrling he 7-SegmentDsrlay 115 Example 29 Scrolling the 7-Segment Display In this example we will show how to seroll a message on the 7-segment display. ‘We will ilustrate the process by scrolling the telephone number 248-656-1490 across the “segment displays Example 10 ~7-Segment Displays 29.1 Scrolling the 7-Segment Display The basic idea in this example will be to modify our x7seg module by changing. the hex7seg decoder part to display a dash (-) for a hex D input and to display blank for ‘a hex F input as shown in Fig. 29.1. The design shown in Fig. 29.2 shows how th scrolling is accomplished. The digits of the telephone number are Stored in a 64-bit register msg_array(0:63). Fig. 29.2 shows how the sixteen bits msg_array(0:13) are connected tothe input x(15:0) of the x7seg_ msg module. On reset the 7-segment display ‘will display the first four characters in the message, namely 248-, The bits in ‘msg_array(0:63) are connected as a shift register so that we shift the contents of ‘msg_array(0:63) four bits the the left on the rising edge of the clock with the value of ‘msg_array(0:3) going into msg_array(60:63).. Thus, alter one clock pulse the value of ‘msg_array{0:13) will contain 48-6, On each successive clock pulse the message will be shifled four bits to the let, We will use the 3 Hz clock to shift the characters on the 7- segment display. iaigic Figure 28.1 Modiied hex7s0g module116 Example 29 x7seg_msg Ppateeed ats ans.nay = mgamayen [4 ae . maaanotetnn [8 oa . mag_arrnyt}2 19) 28. 2 moqanayoaan [6 1 | —— etabit =a 1 1 { { anit sceroynons| | F ak or Figure 282 Scoling a message onthe 7-segment display Listing 29.1 shows how 10 implement the shift register msg_array(0:63) in VHDL. Note that phone number is defined as a 64-bit constant using the constant statement constant PHONE_NO: STD_LOGIC_VECTOR(S3 downto 0) :+ x*248DeseDL4907PFP, ‘The process in Listing 29.1 initializes the value of mog_array when the clr signal is asserted. Then on the rising edge ofthe clock the contents of msg_array are shifted four bits othe left in a circular fashion, The output (15:0) ofthis shift array is just the value of msg_array(0:15). A simulation ofthis shift array is shown in Fig. 29.3, The complete listing of the module x7seg mye is shown in Listing 29.2 and the ‘op_level design is shown in Listing 29.3, Implement and run this program on the FPGA, boafd. Change the phone number to yours Figure 29.3 Simulation of the VHOL program in Listing 28.1Scrolng the 7-Segment Display 117 Listing 201 shitt_aray.vha == Example 2387 sbift_arvay Library! ESE; use ISEE.STO LOGIC 1264.al1+ encity enife_ercay te pore ( clk + 4m sro sosre, clr + im sto_tocic; 2% + Gut STD_LOGIC_YECTOR(15 downto 0) ? ond shift_array: architecture shift_srvay of shift_array 4e signal meg atray: STD LOGIC VECTOR(O to 62) Constant PRONE M10: ST3_LOGIG VECTOR (G3 downto 0) :=K"249D55eD1490FFFF"; begin processiciy, elk) ‘nog array <= PHONE NO; etait (elk'event and clk = '1") then msg array(0 to 58) c= msg_array(4 to 63) Seglerray (60 to 63) ce magarray(0 to 3); and 4 fend process; cresmag.array(0 to 15); eng shift _arrey, Listing 29.2 x7seq_msg.vhd ‘Bxample 29b: x7eeg ag — Dloplay ecrolling easeage input clk should be 130 Hz ‘use IEEE,STD LOGIC 1264.01 ‘Use IEEE, STO_LOGIC_UNSIGNED. all; entity xTseg seg $2 pore x + Am STD_LOGEE_VECTOR(AS downto 0); elk + an si0_tocic; ele + im st0_tocrcy 3to.g = out STD _LOGIC_VECTOR(6 downto 0); Ga rout STD_LoGIC VECTOR(> dowto 0); » Signal ©: S1D_LOGIC_VECTOR(1 downto 0)7 Signal digit: STD _LOGIC_VaCTOR(3 downto 0) signal sen: STD_LGGIC_VECTOR(3 downto 0) Spee a118 Example 28 Listing 282 (cont) x7seq_msg.vhd usd d-ton1 MU: mute procesa(s) Begin +00" a» digit <= x(3 downto 0); worn Is @igit <= x(? downto 4), no others 5 digit <= x(11 downto 8); S digit <= (25 downto 12); (elk, clr) eleif clk'event and clk = '2' then Digit select: ancode processiz, sen) Af Sen(cony integer (e)) = 12" then an(conv_integer(a!) <= °0'r ona if; fend process: <+ Tesegnant decoder: nexteeg (agit) aigit 16 ‘when when whe when S "oo100; xr meee there fend x70. nog‘Scroing the 7-Segment Display Listing 293 scroll top.vhd == example 29¢r Scroll phone Humber on 7ee3 Suaplay ‘use IEEE, STD LOGIC_2164.a11) ‘entity scroli_top 4s port ( nolk + dn st9_toare Den + in ST0_LOGIC_VECTOR(3 downto 3) afo.g + out STD LOGIC VECTOR(s downt 0); an: out Sto Logic. VecTOR(a downto 0); @p : out sta_tocre 1 fend sorol1_top: architecture scroll_top of scroll_top 18 component clkaiy de nuclk + 4m st tote; ele + 4a sto zoare, e1k130 + owt” STD_Loare: ele) + out 81D 1o67¢ ds ‘end component, Component shift arvay ia ort elk + 4m s1D_Loare; ele + an st0_LoGrcy X + Que STD_EOGIC YECTOR(25 downto 0) fend component port ( X + Am STD_LOGIC_vECTOR(:5 dowmto 0); lk 7 dn 65D. LOGEC, lr : dn srB-Loare, a tog + out S™D LOGIC _VEcTOR(s downto 0}; aR © out STD_LOGIC vECTOR(3 downto 0) 4p + out stp Lose i fend component Signal clr, clk190, cik3: st>_Loarc, Signal x: STD_LOGIC_VECTOR(1S downto 0); begin ‘B1E <= ben(3) ui: olkaiy [pore map ( clk3 => elk3} ‘ - ‘ Ort map ( ‘clk => clk3, ele => ely, x => xl ua: s7eee meg port map | aise x, clk => elki90, ele => ete, atog'-> ato, ans> an, dp => dp); 10120 Example 20 Example 30 Fibonacci Sequence In this example we will show how to generate the Fibonacci sequence and display the result on the 7-segment display Prerequisite knowledge: ‘Example 8 ~ Clocks and Counters Example 10~7-Segment Displays. Example 19 ~ Registers 30.4 bonacci Sequence The following sequence of numbers is known asthe Fibonaee! sequence. (0,1, 1,2,3,5,8, 13, 21,34...) ‘The function for generating Fibonacei numbers is FO)=0 FU=1 Fin 2)= Fin) + Fon I) for all n20. In other words, starting with a ero and a one, the next number is generated by adding the previous two numbers. This requires storing previous results, namely the two previous results. This can be done by using two registers fn and find as shown in Fig. 30.1. For cach of these registers, if the load signal rfd is 1, the value coming into the top gets latched to the output coming out the bottom on the rising edge of the clock input cll. The clr input signal causes an asynchronous resetting ofthe oulput to a predetermined initial value (0 for fu and I for fa). nea Figure 301 Circuit for computing the Fitonacc sequenceFibonacci Sequence 21 On the rising edge of the clock the value of fi! gets updated with the sum Jr2 = fas frland fn gets updated with the old value of fad. We will use 16-bit registers the circuit in Fig. 30.1. It is possible to write a single VHDL program involving a ingle process that will implement the Fibonacci sequence algorithm as shown in Listing 30.1, A simulation of this VHDL program is shown in Fig. 30.2, Listing 301 vba w= Beanple 30: FIRONAEET Sequence Library ZEEE; use TEEE.STD_LOGIC_unsigned.al2; entity fib te pore elk + im sto soare, flr + im sTO-LosIc, £ + que STD L6GIC_VECTOR(23 downte 0) ” ond fib architecture fib of fib se Signal ft, fn: STD_LOGIC VECTOR(13 downto 0} Constant fib max: integer = 9999; begin PL: procesa(cik, cls] af clr = 12" then ini <= speosoe00000001" st clx'event and elle = fot + fn: fa co eal else fm <= *Do000000000001"; fend process: Presta end fib: a ae oe ee ee Rae Ee z bOnw @QAQ wun te wan 4a 3K Figure 302 Simulation of the VHOL program in Listing 30.1122 example 30 “The adder is implemented with the + sig. Fig. 30:3 shows a top-level BDE design tha ‘can be implemented on the FPGA board. "The Fibonacci sequence will inrement a a 3 Hzrate. [twill not take long to overflow the 4-digit hex display. Try it. we leant 5 ut srcn— fe eof Hate 2 exe}. (09) or canst ey, nen wrofettSDeb ven wl Bap Figure 30.3 Topevel design for Fibonacci sequenceAldec Actve-HDL Tutorial 123 Appendix A Aldec Active-HDL Tutorial Part 1: Project Setup ‘Start the program by double-clicking the Active-HDL icon on the desktop. Select Create new workspace and lick OK.424 ‘Appandic A Select Create an Empty Design with Design Flow and click Next Click Flow Settings ‘Select HDL Synthesis: Select Xilins ISEWebPack 8.1 XST VHDL/Verilog Press SelectAdee Actve-HDL Tutorial 128 Select Jmplementation Choose Xiliny ISEWebPack 8.1 Press Select Solect Xilinx X SPARTANSE for Family Se | eect al Click oF ee128 AAppendbs A Select VHDL for the Default HDL. Language net Click Next ‘Type sled for the design name and click Next. pepttenemontin Click Finish,‘Adee Actve-HDL Tutoial 127 Part 2: Design Entry ~ sw2led.bde Ck on 2. ik Net es Ee. = | selest PDL and Click Next128 Appendix ‘Type sw2led SET and click Next. eS ea Click New indexes to 7:0 {ace cen ‘Type ld a i iene Sen ncaa poe ickstacer indexes 7.0 Click New: EY 7g | click ou Click Finish,Aloe Actve-HOL Tutorial 129 ‘This will generate a block diagram (schematic) template withthe input and oyfpur ports displayed. ‘You will need to select the output port by dragging the mouse with the left mouse button down and move the output port to the let130 ‘Appendbs A Rightlick on sw2ed be and select Compile. cick synthesis options‘Adee Actve-HOL Tutoral 131 Pull down menu and select sw2led for Top-level Unit | [Check VEL | BASYS Board Select 3s/0etg/44 for Device from pall down ist. Nexys2 Board: Select 35500320 for Device from pull dow list. Click OF After synthesis is complete, elick Close.Click implementation — options Appendix A 2 [ setect Custom constraint fle Browse and select the file hays2.ef (or nexys2.ucf available at wwe Cs oe ob‘Adee Actve-HOL Tutorial 133, Select Translare and check Allow Unmatched LOC Constraints Shift for more options... Select BiStream and uncheck Do Not Rum Big Select Startup Oprions and select JTAG Clock for the FPGA Start-up Clock. Click OF104 Appenctc A Click implementation ‘When implementation is complete click Close. Part 4: Program FPGA Board To program the Spartan3E on the BASYS or Nexys-2 boards we will use the ExPort too! that is part of the the Adept Suite availabe fice from Digitent at hui digilentine.com/Sofiware/Adept.cfn2Nav Double-click the ExPort icon on the desktop. Click snitiaize ChainAldec Actve-HOL Tutorial 135, (Click Browse and go to Example ->swied->implement- Select sw Jled bit, yer ->revl->sw2led bit (Click Program Chain ‘Your program is now running on the board. Change the switches and watch the LEDs,136 ‘Append A Part S: Design Entry ~ gates2.bde Click on BDE, —=—] Click Nest ce Q fetdemarend aa Tr amsare eta ety Select VHDL cee and Click Next‘Aldec Acive-HOL Tuloral 137 ‘Type gates? and click Next. a Yates tnt Bre Click New. Type a. Click New.198 ‘Append ® Touldarenout ken Click New. Toedtapot ect ante Thnyaucanclage a con arse Togs ore eee (Segurisagetaeomantsandwevine se’ | Type and gate ‘Sede ype and ga Click our Continue to sor gate. ick New and add the outputs nand_gate, or gate, nor_gate,xor_gate, and New Source Ile Wiear Soa alae dea aon Tejooveapat. lc ton at and ten cc Click Finish,Adee AciveHOLTulosal 138 ‘This will generate a block diagram (schematic) emplate with the input and onfput ports displayed. Select the output ports by dragging the mouse with the let ‘mouse button down and move the output ports tothe lef Click the Show Symbols Toolbox icon Taek Click Yon Built-in symbols40 Appendic A ‘Grab the and? symbol with the mouse and drag ito the output port and gate Grab the symbols for nand2, or?, nor? xor2, and xnor2 and drag them to the appropriate output port, moving the output ports down as necessary.Aldec Actve-HOL Tutors 141 ‘Select the wize icon and connect the gate inputs toa and b as shown.va ‘Appendix A ect gates? bde ‘and >*and then click OK Click here to select [caren design filesAldec ActveHOL Tutorial 143, Click Use Default Waveform Click OK CCiek fimetional simulation148 ‘Appendc A ‘The waveform window will automatically come up with the simulation already initialized. Make sure the order is a, , and_, nand_, o”_, nor_, xor_, xnor (grab and drag if necessary). Right-click on a and select Stimulators. Click ApplyAld Aetie-HOL Tutoral 145. Click on b, select Clock and set Frequency to 50 MHz8 Appendic A Part 7: Design Entry - HDE, Click on HDE. Seleet VHDL sand Click OK. Click Next Tiaede Testa nc Iie Seppe tp teed wrt Gao “Type gates? W's none and click Nex. ‘tan denon aidee Aetve-HDL Tutorial 147 Click New. Click New. Click New. Types. Set Array Indexes 105.0 Click Finish,148 Appendic A ‘This will generate a VHDL template with the input and output signals filled in. Delete Delete these comments.Aloe Actve-HOL Tutorial 149 2 Tlick Sard 3 T 3 i " ype in these six liek on * a then signal assignment Right-clieon statements ‘gates2.vhd and (see Listing 2.1 of select Compile Example 1) Pius SE Setetesz na 2 Pelick > to move and then Click Ok (Click hereto select design files180 ‘Appendc® (Click Chogse, select gates? asthe top-level design, and click Aad Click OFAldec Actve-HOL Tutorial 154 Click finerional sinutation ‘The waveform window will automatically come up with the simulation already initialized, Make sure the order is a,b, Right-click on g and select Suimulaiors.182 Appendbc A Select Clogk and set Frequeney to 25 MHz Click Apply Click on 6, select Clogk and set Frequency to 50 MHz Click Apply. Click CloseAldec Actve-HOL Tutorial 183 Set simulation time to $0.ns| Click here to run simulation Click # sign to show all elements of Study the waveforms for various magnificati ‘To printout this waveform you can detach it by clicking >> here and then press All Prau Serm to copy ito the clipboard. Then paste it in de fle and pint.154 Append Appendix B Number Systems ata inside a computer are represented by binary digits or bits. The logical values of these binary digits are denoted by 0 and 1, while the corresponding physical values can be any two-state property such as a high (5 volts) or low (0 volts) voltage oF two different directions of magnetization. Itis therefore convenient to represent numbers inside the computer in a binary number system. Hexadecimal and octal numbers are ‘often used as a shorthand for representing binary numbers. Inthis appendix you will learn: + How to count in binary and hexadecimal + How integers and fractional numbers are represented in any base + How to convert numbers from one base to another + How negative numbers are represented inthe computer B.1 Counting in Binary and Hexadecimal Consider a box containing one marble, Ifthe marble isin the box, we will say thatthe box is fl and associate the digit withthe box. If we take the marble out ofthe box, the box will be empty, and we will then associate the digit 0 with the box. The to binary digits 0 and 1 are called bits and with one bit we ean count from zero (box empty) to.one (box fll) as shown in Fig, B.1 Lo Let = eroiy box 1 =fulboe Figure 8.1. You can count rom Oto 1 wit 1b Consider now a second box that can also be full (1) or empty (0). However, when ‘this box is full, it will contain vo marbles as shown in Fig. B.2. With these two boxes (2 bits) we can count from zero to three, as shown in Fig. B.3. Note that the value of each ‘bit binary number shown in Fig. B. is equal to the total number of marbles in the 1wo boxes. Lt Lees empty box 4 =turbox Figure 82 This box can contain ether two marbles (fl) oF no martes.Number Systems 155 Tota no, of marble Lo 7 7 a Lees Li 2 Lees Less Figure 83 Youcan count Fem Oto 3 with two bis We can add a third bit t the binary number by adding a third box that is full (bit = 1) when it contains four marbles and is empty (bit = 0) when it contains no marbles. It, must be either full (bit= 1) or empty (bit = 0). Wit this third box (3 bts), we can count from 0 to 7, as shown in Fig. B.A et leees) Lees Let 7 Figure 84 You can count from 0 t07 with 3 bis I you want to count beyond 7, you must add another box. How many marbles should this fourth box contain when iti full (bit = 1)? It should be clear that this box ‘must contain eight marbles, The binary number 8 would then be written as. 1000. Remember that @ 1 in a binary number means that the corresponding box is full of ‘marbles, and the number of marbles that constitutes a full box varies as 1, 2. 4 8 starting atthe right. This means that with 4 bits we can count from 0 to 15, as shown in Fig. BS. i is convenient to represent the total number of marbles in the four boxes represented by the 4-bit binary numbers shown in Fig. B.S by a single digit. We call this 1 hexadecimal digit, and the 16 hexadecimal digits are shown in the right column in Fig. BS. The hexadecimal digits 0 to 9 are the same as the decimal digits 0 10 9. However, the decimal numbers 10 1015 are represented by the hexadecimal digits A to F. Thus, for example, the hexadecimal digit D is equivalent tothe decimal number 13,16 ‘Appendix B No ofmarbles ineach | Totalno full box (bit= 1) ctmarbies | _Hexalgit a4 24 0000 7 3 000% 1 1 oot0 2 2 0014 3 3 o100 4 4 o10% 5 5 o110 6 8 1a 7 7 1000 8 8 1004 ° ° 1010 0 A todd " a 1100 2 c 1104 3 D 1440 “4 e aaa 6 F Figure B'5 You can count from 01015 with 4 its To count beyond 15 in binary, you must add more boxes. Each full box you add must contain twice as many marbles as the previous full box. With 8 bits you ean count from 0 to 255. A few examples are shown in Fig. B.6. The decimal number that corresponds to a given binary number is equal tothe total number of marbles in all the boxes. To find this number, just add up all the marbles inthe full boxes (the ones with binary digits equal to 1), No.of marbles Total no. ineach full box (bi of marbles ee ae 8 a TOTTI Too % to10 0048 183 ptaaadaad 25 Figure 86 You can count rom 0 10 265 with 8 bits As the length of a binary number increases, it becomes more cumbersome to work with. We then use the corresponding hexadecimal number as a shorthand method of representing the binary number. This is very easy to do. You just divide the binary number into groups of 4 bits starting at the right and then represent each 4-bit group by its corresponding hexadecimal digit given in Fig. B.S. For example, the binary numberNumbor Systems 187 is equivalent to the hexadccimal number $9A. We will often use the dollar sign $ preceding a number to indicate a hexadecimal number. You should verify thatthe total rhumber of marbles represented by this binary number is 154. However, instead of counting the marbles in the binary boxes you can count the marbles in hexadecimal boxes where the first box contains A x I= 10 marbles and the second box contains 9 x 16 = 144 marbles, Therefore the total number of matbles is equal to 144 + 10= 154 ‘A third hexadecimal box would contain a multiple of 162 = 256 marbles, and a fourth hexadecimal number would contain # multiple of 163 = 4,096 marbles. “AS an example, the 16-bit binary number Spe ets is equivalent to the decimal number 34,761 (that i, it represents 34,761 marbles). This ‘ean be seen by expanding the hexadecimal number as follows’ eral = ex 4,096 = 22,768 pried sex 2 3 Table B.1 will allow you to conveniently convert hexadecimal numbers of up to four digits to their decimal equivalent. Note, for example, how the four terms in the conversion of $87C9 can be read directly from the table, Hexadecimal and Decimal Conversion. 18 eae fn — ew — op} — oe — ts — oe = eet Teas “ete a eats geste ste t fits eo ima %188 ‘Appendix B.2 Positional Notation Binary numbers are numbers to the base 2 and hexadecimal numbers are numbers to the base 16, An integer number IV can be written in any base b using the following positional notation: N= PgPsP2P Pi yb! + Pzb3 + Pah? + Pybl+ Poh! \where the number always starts with the leat significant digit onthe right. For example, the decimal number 584 is a base 10 number and can be expressed. = 500 + 80+ 4 ‘A number to the base & must have 6 different digits. Thus, decimal numbers (base 10) use the 10 digits 0t0 9. A binary number isa base 2 number and therefore uses only the wo 1. For example, the binary number 110100 isthe base 2 number Gand rood; = 1225 + vat + O29 + 142? + oa! + ona This is the same as the first example in Fig, B.6 where the total number of marble is 32 (32+ 16 +), "A hexadecimal number is a base 16 number and therefore needs 16 different digits to represent the number. We use the ten digits Oto 9 plus the six letters Ato Fas shown in Fig. B.S. For example, the hexadecimal number 3AF can he written as the base 16 number . 2 base + tons Tn aaa Microcomputers move data around in groups of 8-bit binary bytes. Therefore, it is natural to describe the data in the computer as binary, or base 2, numbers. As we have seen, this is simplified by using hexadecimal numbers where each hex digit represenis 4 binary digits. Some older computers represented binary numbers in groups of 3 bits rather than 4, The resulting number is an octal, ot base 8, number. Octal numbers use only the 8 digits Oto 7. For example, the octal number 437 can he written as the base 8 number = 30310Number Systeme 159 B.3 Fractional Numbers ‘The positional notation given in Section B.2 for integer numbers can be ‘generalized for numbers involving fractions as follows N= P2PLPAPP-2Po3o.= oo Pgh? + Py! + Pobl! + Pay + Pah? + PsbS + As an example, consider the base 10 number 375.17. Using the above definition, this is ‘equal to Me 3202s 7x20) + x100 4 2x20"! + 7x30? 00+ 704 s+ Gl + 0.07 238.27 In this case the radix, or base, is 10 and the radix point (decimal point) separates the integer part of the number from the fraetional pat. Consider now the binary number 1101.11. This is equivalent to what decimal ‘number? Using the above definition, we ean write Following the same technique, we can write the hexadecimal number [AB.6 as 1aB.61¢ + 167 + 10a6t 6 126? + ome? ‘Asa final example consider the octal number 173.28. We ean find the equivalent decimal number by expanding the octal number as follows. 173.259 = 198? 4 W482 + x80 + axa-2 + sxe? sore sera ed The examples inthis section show how you ean convert a number in any’ base 10a decimal number. In the following section we will look at how to convert @ decimal rhumber to any other base and how to convert among binary, hexadecimal, and octal B.4 Number System Conversions In the previous section you saw how you can convert a number in any base to its decimal equivalent by expanding the number using the definition of the positional notation of the number. For a hexadesimal number containing & maximum of four hex digits, it is easy to use Table B.1 to find the conversion by simply adding the corresponding decimal valve from each of the four columns, Note thatthe entries in the160 ‘Append B {our columns of Table B.1 are simply the hex digits multiplied by 163, 162, 161, and 169 respectively. If you dontt have Table B.1 (or a calculator that converts hex numbers to decimal), you can use the following shortcut to convert a hex integer to decimal. To convert the hexaclesimal number A7|6 to decimal, multiply A x 16 and add 7. For longer hexadecimal numbers, start with the leftmost digit (the most significant), multiply it 16, and add the next hex digit. Multiply this result by 16 and add the next hex digit. Continue this process until you have added the rightmost digit. For example, to convert 87C94g 0 decimal, you can do this 6 18 128 2 735 118 2.180 —s2 air 8 782 3. i761 ‘Therefore, 87096 = 34,7610, This technique will work for any base. You just multiply by the current base, rather than 16, in each step of the process Binary <-> Hex Converting a binary number to hex is trivial. You simply partition the binary umber in groups of 4 bits, starting at the radix point, and read the hex digits by inspection using the hex digit definitions in Fig B.S. For example, the binary number 11010101000.1111010111 can be partitioned as follows: ‘Therefore, 11010101000.11110101119 = 6A8.FSCyg, Note that leading zeros can be added to the integer part of the binary number, and tailing zeros ean be added to the fractional part to produce a 4-bt hex dit. Going from hex to binary is just as easy. You just write down the 4 binary digits corresponding to each hex digit by inspection (using the table in Fig. B.S).Number Systems 161 Binary <~> Octal Converting a binary number to octal is just as easy as converting it to hex. In this ‘ase you just partition the binary number in groups of 3 bits rather than 4 and read the ‘octal digits (0 to 7) by inspection. Again the grouping is dane starting at the radix point. Using as an example, the same binary number 11010101000.11 11010111 that we just converted to hex we Would conver it to octal as follows: 233nesn ope. 33.3 3aon ‘Therefore, 11010101000.111 10101112 = 3250.7534. Note again that leading zeros must bbe added to the integer part ofthe binary number, and tailing 2eros must be added to the fractional part to produce 3-bit octal digits. You reverse the process to go from octal to binary. Just write down the 3 binary Aigitscomresponding to each octal digit by inspection. Hex <-> Octal ‘When converting from hex to octal or from octal to hex, it is easiest to go through. binary. Thus, for example, to convert GA8.FSCi¢ 10 octal, you would first convert it to the binary number 11010101000.111 10101112 by inspection, as shown in the example above. Then you would convert this binary number 1o 3250.7534g, as we just did in the previous example. Decimal to Hex Suppose you want to convert a decimal intoger 167 to its hexadecimal equivalent, ‘The easiest way to figure this out is to look at Table B.1. The elosest decimal value in this table that does not exceed 167 is 160 in the second column from the right. “This corresponds to the hexadecimal digit A asthe second digit from the right (A x 16! = 10 x 16 = 160), To find the hexadecimal digit to use in the rightmost postion, subtract 160 from 167. Thus the decimal number 16710 is equivalent to the hexadecimal number A716. What binary number is this? How ean you convert a decimal integer to hexadecimal if you don't have Table B.1 around? Here's a shortcut. Divide the decimal number by 16 and keep track of the remainder. Keep dividing the results by 16 and writing down the remainders at each step until the result is zero. The equivalent hexadecimal number is all the remainders read backward. For example, this is how to convert the decimal number 16710 to hexadecimal: 167/16 = Lowth remainder 7 10/15 = Owithremsinder 10 et vce —4162 Appendix 8 Here's the example we gave atthe beginning ofthis section. 34,762/26 = 2,172 with remainder 9 2/17/16 = 135 with remainder 12 = ¢ aas/ie = @ with remainder 7 sis © with remainder 3 cy —t ‘Therefore, 34,761y0= 87C9}s. Again, this technique will work for converting a decimal integer o any base. You just divide by the base, keep track of the remainders, and read op. ‘When converting a decimal number containing a fractional part, you divide the problem into two parts. First, convert the integer part using the technique just described. Then you can use the following rule to convert the fractional part: Multiply the fractional part by the base, keep track ofthe integer part, and read down. As an example, suppose {You Want to convert the decimal number 3901.781254q to its hexadecimal equivalent You would first convert the integer part by dividing by the base, keeping track of the remainder, and reading up 3901/16 = 242 with remainder 13 = 2aa/as = 15 withremainder 3 s/s = 9 withremainder 25 weaip —4 ‘Therefore, 3901p = F3Djg. To convert the fractional part, multiply by the base, keep track of the integer part and ead down: read down 7 12,5. integer part = 12 = © 8.0 integer part = © 0.7128 x 36 Therefore, 781759 = OCRie Combining the integer and fractional parts, we have found that 3901.78125i0 = F3D.C8), This rule for converting the fractional part of a decimal number will work for any base. Sometimes the remainder may never become zer0 and you will have a continuing fraction. This means that there is no exact conversion of the decimal fraction. For example, suppose you want to represent the decimal value 0.170 a8 binary number. Following our rule, we would writeNumbor Systems 163 o.2x2- 0.4 — inegerpart 0.4x 2+ 0.8 integer part o.8x2 = 1.6 integer part o.sx2 = 2.2 integer part o.2x2= 0.4 integer part o.4x2 = 0.8 integer part o-ax2= 2.6 integer part o-6x2 = 2.2. integer part It is clear that the remainder will never go to zero and that the pattern 0011 will go on forever, Thus, 0.119 ean only be approximated as ‘This means that 0.10 cannot be represented exactly ina computer as a binary number of any size! B.5 Negative Numbers An $-bit binary number ean represent one of 256 (28) possible values between 0 and 255, However, we also need to represent negative numbers. The leftmost bitin a binary number i the sign it. IF his bit is zero, the number is postive: if this bit is one, the number is negative. However, in the 8086, (and in most computers today), when the ‘most significant bit is one, the magnitude of the negative number is not given by the binary value of the remaining bits in the number. Rather & two's complement representation of negative numbers is used. The reason for this is thatthe same circuit, ‘an adder, can be used for both addition and subtraction, The idea of being able to subtract by adding can be soen by an example using decimal (base 10) numbers. Suppose you want to subtract 35 from 73, The answer is 38. You can obtain this result by taking the 10's complement of 35 (this is what you have to ‘add to 35 to get 100; that is, 65) and adding ito 73. The result is 138 as shown in Fig. B.7. If you ignore the leading 1 (the carry) then the remaining value, 38, is the correct n a =35 O's compament 965. 3a ine trove cary —4 Figure B.7 Decimal subtraction can be done by taking the 10's complement ofthe subtranend and acing164 ‘Appendic B In binary arithmetic, negative numbers are stored in their two's complement form, You can find the two's complement ofa binary number in several ways. Note that the 10 complement of 35 can be found by subtracting 35 from 99 (this gives the 9s complement) and then adding 1. That is, oe ‘The two's complement of the 8-bit binary number 01001101 is the 8-bit binary number you must add to this number to obtain 100000000, You can find it by subtracting the number from 11111111 and adding 1. Note that subtracting an 8-bit binary number fom 11111111 (called the one’s complement) is equivalent to complementing each bitin the byte; that is, each 1 is changed 10 a 0, and each 0 is changed to a 1. Therefore, the ‘one's complement of 01001101 is 10110010 and the two's complement of 01001101 is ‘one's complement = 10120010 ‘add a ‘wo's complement 70130082 ‘There isan easier way to take the two's complement ofa binary number. You just start at the rightmost bit and copy down all bits until you have copied down the first 1. ‘Then complement (that is, change from 1 to 0 or 0 to 1) all the remaining bits. For example, complement remaining bits 7 r copy this fist 1 o10 102 2 a o 2 two's complement ‘Asa second example, eres eee VP ees Re oe ase wou asa eeNumber Systems 185 Note that if you take the two's complement of a positive number between 0 and $7F the result will always have bit 7 (he most significant bit) set to 1 HE = GIOOTOGT Two's complement = -75,, = §85 = 10320102, Twoscomplementof $85 = gab = 01902012 Figure 5.8 The negate ofa binary number is founs by taking the twos complement Given a negative number (with bit 7 set), you ean always find the magnitude of this number by taking the 10's complement. For example, the two's complement of SBS (75a) is S4B (75a), as shown in Fig. B.S. Note that the two's complement of $01 is $FF and the two's complement of $80 is ‘880, as shown in Fig. B.9. This last example shows that signed 8-bit binary numbers “wrap around" at $80. That is, the largest positive number is SIF = 1279 and the smallest negative number (largest magnitude) is $80 = -128)o, This is shown in Table B2. Te = SOL = DOOUDOT Twos complement = iy. = SPF» 10221111 228,5 = $60 = 10000000 ‘Two's complem = 80 © 0000000 Figure 89 Negative 8. numbers can range between SFF (-1) and $80 (128), Table 8.2 Positive and Negative Binary Numbers TTT168 Appendix Table B.2 also shows that the hex values between $80 and SEF can be interpreted either as negative numbers between -128 and -1 or as positive numbers between 128 and 25. Sometimes you will treat them as negative numbers and sometimes you will teat them as positive Values. Its up to you to make sure you know whether a particular byte is being treated asa signed or as an unsigned number ‘Whereas bit 7 is the sign bitin an 8-bit byte, bit 15 s the sign bitin a 16-bit word. A 16-bit signed word can have values ranging from $8000 = -32,768)9 to S7FFF = +32,16719, Similarly, bit 31 isthe sign bitin a 32-bit double word. Such a douile word can have values ranging from $80000000 = -2,147,483,6480 to STFFFFFFF = 42,147 483.6470,Basic Logic Gates 17 Appendix C Basic Logic Gates All digital systems are made from a few basic digital circuits that we call logie ‘gates. These cireuits perform the basic logic functions that we will deseribe in this chapter. The physical realization of these logic gates has changed ever the years from mechanical relays to electronic vacuum tubes to transistors to integrated circuits containing thousands of transistors. In this chapter you will eam: ‘© Definitions ofthe basie gates in terms of truth tables and logie equations DeMorgan’s Theorem How gates defined related ‘© How to write a logic equation from a truth table using sum-of- products and praduct-of-sum designs n terms of positive and negative logic are C1 Truth Tables and Logic Equations All data ina computer ae stored as binary digits. These bits canbe thought ofa the logieal values O and 1, where aI is considered tobe arue and 0 i considered to be false, The actoal physical quantities associated with aO and a | might be alow (0 vos) ‘or high (5 volts) voltage. ‘A truth table il define the logical outputs (0 or 1) of the gate for all posible logical inputs. In this section we will define the thre basic gates, NOT, AND, and OR, by meant of thet ruth tables. We wil then use these baie ges to define some auiional gates. Using tah ables we will discover the important De Morgan's theorem. ‘We will hen consider the possibilty of considering Oto be fre and Ito be fase. This wil give us a eter nsight int the various gates ‘The Three Basic Gates NOT gate. The definition of the NOT gate, or hwerter, is shown in Fig. C. ‘The logie symbol forthe inverter has a single inptx and a single output y. The value of is the complement of the input. Thus, as oT. aaa fourteenth Chitsih bey Peltiectsetuaeemesct Pet To] 1 J sn ets og nace pe iio y Figure ©.1 The NOT gate or verter168 Appendix © ‘The equation forthe inverter in Fig. C.1 is given as y=~x. We read this as "y ‘equals NOT x." This is the symbol used for NOT in Verilog. VHDL uses the word not as the negation operator. Thus, in VHDL the logic equation y = ~x would be writen as, ¥ <= not x (the use of the assignment operator <= will be discussed later). Because ‘writing out the word not is more cumbersome, we will use the Verilog aperator ~ forthe NOT operation when writing logie equations in this book. ‘The prime, bar, exclamation point, slash, and ~ are sometimes used to indicate the NOT operation, a3 in yew oy yom yew AND Gate. The definition ofthe AND gates shown in Fig. C2. ‘The AND gate Jogie symbol has two inputs, x and y andthe single ouput z. From the wuth table in Fi (C2 we se that the output ofan AND gute is 1 (uve of high) only if oth inputs, x and y, are I (tue or AND. high). The output = will be zero if ether or y oF xyz both are zero B4B “The equation forthe AND gate in Fig. C2 is z tals given as z=. We read this as" equals x ANDY aa 32 This is the symbol used for AND in Verilog VHDL uses the word and as the AND operator. Thus, in VHDL the logic equation z=x & y would be Figure C2 The AND gate writen as z<=.x and y. Again, for convenience we will use the Verilog notation & for the AND operation when writing logic equations. Other common ways to indicate the AND operation are ay xay xty oy ‘The last form involving the juxtaposition of x and y limits you to logic variables containing a single letter. We will be using names for our logic variables in which case any could representa single logic variable. OR Gate, The definition ofthe OR gate is shown in Fig. C3. The OR gate log symbol has two inputs, x andy, and the single output z, From the tut table in Fig. C3 we see thatthe output: of an OR gate i 1 (rue ‘or high) iether input, ory, or both ate I (te _ OR ‘or igh). The output z will be zero only ifboth x and y are 2270. 2 “The equation for the OR gate in Fig. C3. isgiven as2=x|). We read tisas "s equals Sy OR 9." This is the symbol used for OR in Verilog. VHDL uses the word or as the OR FaweC.3 The OR gate ‘operator. Thus, in VHDL the logic equation === | y would be written as 2 _w omorn fate flowed Sy an inverter (NOT. | ot) o]t AND), ae shown bythe two truth . too|t fee in Fig C4. VHDL tses the WX i]s : paws ey) ° ‘work nand for the NAND operation, Figure .4 The NANO NOR Gate. The def ition of the NOR gate is shown in Fig. CS, The logic symbol fora NOR gate slike an OR gate with @ small eirele (or bubble) NoR xy|z on the output. From the tuth table a ott in Fig. C5 we see thatthe output oF 01/0 a NOR gate is 1 (high) only if both 4 o}o inputs are 0 (low). The NOR gate is 11}o0 ‘equivalent to an OR gate followed by an inverter (NOT-OR), as shown, by the two truth tables in Fig. CS xy|ulz VHDL uses the work mor for the Tet NOR operation. gales 1 o}ilo r1}it}o Figure C-§ The NOR gate, Exelusive-OR Gate. The definition of the Exclusive-OR, or XOR, gate is shown in Fig. €.6. The XOR gate logic symbol is ike an OR gate symbol with an extra curved vertical line on the input. From the truth table in Fig. C.6 we see thatthe output z of an170 ‘Appendhs © XOR gate is | (rue or high) either input, x ory; is | (true oF high), but nor both. The ‘output z will be zero ifboth x and y ae the same (either bath I or both 0). The equation for the XOR gate in Fig, C.6 is given as 2 =.x * y. This is the symbol used for XOR in Verilog. VHDL uses the word xor as the XOR operator. Thus, in VHDL the logie equation 2 ~ x * y would be writlen as = TET ‘Signals and [signal (isd t-conmectone logic Petoeal 7 st negTeveetorT7 EO Tr ‘arabes Types | cane ora) Tn le ed ate eae ‘variable (variables assigned values in hieier 7) proces) wassane bs tateges Tmeser (ust fr loop cot sar) Pagan] See a Rogen [Melek eriocrcaeeana, | woe We Stance a “[concurcent.seatevent}) | "process (clk, lz) BO er tae i cued ege(e enn Tage opens | BE120 Appendix E VHDL Quick Reference Guide (cont) Tamaki opera | > aon ‘count <> OE Ty + Gubrction) geend * ulation) Givison (ot yhesizable rem_(emaindr) Relational operators = Tea = b then ‘Shit operators | si arzsouny er seta 3T7 she (acount) es ohelad)7 Wes Tes] proces ena TAP] By {process desir} aaa beg we, com ineogrtat {lscquentia tenet] or a's te Posy nd proces [3] 4a Wstaionent Tepes mew FE ST ee statement} etoseiche'Ceene and clk = 02°) een {(esifexression2) then eect ein este lee statement) 1 cad if ‘ae HalaTen | ee ean ‘Conten cote = (sequent a stone} )) a oh et tre others sequal sta sate} cad exe Trio Tor ier ang Top {sequent sateen) xd 0 “asignment opertar | = Caviabe) = Giga). 2 count + 22 Poa men inane namie compuncn_rane part [OTE pore eT ap pot assoiation Hist,Index Absorption, 177, 181-82 ‘Active-HDL, 34 ‘Active-HDL tutorial, 123-53 Adder, 70-81 ‘Alldec, (see Active-HDL) AND gate, 1, 11-20, 168 ‘Arbitrary waveform, 107-8 ‘Assignment operator: nal, 9, 95.96 variable, 96 Associative law, 177-78 BASYS board, 2, 4-6, 10, 42 BDE, 3,8, 10 ‘examples, 8,11, 13, 17-20, 24, 21,29, 34, 37, 41-42, 46, S51, 55, 57,59, 64, 66, 70,73 75, 81, 83, 85, 87-92, 94.95, 100, 102, 106, 108, 122 Binary number system, 154-57 Block diagram editor, (see BDE) Boole, George, 176 Boolean algebra, 176-88 theorems, 176-82 Carry, 71-78 LB 12 Clock divider, 45-47, Clock pulse, 105-6 Common anode, 48 Common cathode, 48 (Commutative law, 17-78 Comparator, 82-83 ‘Acbit using relational operators, 82.83, Configurable logic block. (see CLB) Constant, 116-17, 121 Conversions: binary —hex, 160 binary ~ octal, 161 decimal to hex, 161-63 hex —octal, 161 hexadecimal to decimal, 137, number system, 159-63 Index 101 ‘Counters, 42-47 divide-by. Nebit, 42-44 | ring, 98-99 PLD, 1-2 88-89 D flip-top: cedge-triggered, 84-85 in VHDL, 86-87 De Morgan's theorem, 171-73 Debounee, 103-4 Design entry, 127-30, 136-41, 146-49 Digilent,2 Distributive laws, 177, 180-81 Duty eyele, 110 D flip-top) Exclusive-NOR gate, 170-71 Exclusive-OR gate, 169-70 Fibonacci sequence, 120-22 Field programmable gate array, (see FPGA) Flip-op, 2,47, (see also D fi FPGA, 1-4 program board, 134-35 Spartan-3E, 1-4 Vertex, 3 Fractional numbers, 159 Full adder, 70-75 Futaba, (see servo) flop) Gates, 167-75 2-input, 11-15 ‘muliple-input, 16-20 Half adder, 70 HDE,3,9 Hexadecimal, digit, 155-56 number, 157-59 Implementation, 130-34 Inverter, 167 Johnson counter, 101-2K-maps, (see Kamaugh maps) ‘Kamaugh maps, 23, 49-50, 108, 182-89 four-variable, 186-88 three-variable, 184-86 two-variable, 182-84 LED, 6-10, 48 Light emitting diode, (see LED) Logie equations, 37-38, 49-50, 107-8 Logie gates, (see gates) Logical operators, 82 Lookup table, (see LUT) LUT,2 Maxterm, 174-75 Minter, 173-74 Morse code, 107-8 Motor, 109-10 Multiple-input gates, (see gates) Multiplexer, 23-41 2eto-1, 23-26 410-1, 34-41 generic, 31-33 27-33 40-41, 54-58 NAND gate, I, 11-20, 84-85, 169, 17 Negative logic, 171-73 [Negative numbers, 163-66 Nexys-2 board, 2,46, 10,42 NOR gate, 11-20, 169, 172 NOT gate, 162-68, 172 ‘Number systems, 154-66 (Octal number, 158 OR gate, 1, 11-20, 168 Parameters, 31-33, 42-43, 82-83, 93, PLD, 1 Positional notation, 158-59 Positive logic, 171-73, Principle of duality, 177 Product of sums, 174-75 Programmable logic device (see PLD) Project setup, 123-26 Pulse-width modulation, (see PWM) PWM, 109-14 controlling postion of servo, 13-14 controlling speed of motor, 109-12 Radix, 159 Radix point, 159 RAM: block, 2 distributed, 2 Register, 90-94, 120 1-bit, 90-91 2-bit, 91-92 N-bit, 93-94 Relational operators, 82, Ring counter, 98-100 Seno, 113-14 Futaba $3004, 113 T-Segment decoder, 48-53 T-Segmentdspays, 4.63, ‘uiplexing, 54-56 seroling 115-19 Shit resister, 95-97 Simulation, 14245, 149-53 Spartan-3E, (ee FPGA) St of Products, 173-78 Switches, 6-10, Switching algebra (see Boolean algebra) Synthesis, 130-134 Truth table, 167-71 Tutorial, (see Active-HDL) Two's complement, 164-66 “4bit saturator, 64-69 Unity, 177, 181, Venn diagrams, 178-81 Verilog. 3,5 Vertex, (see FPGA) VHDL. 3.5 ‘axe Statement, 39-40, 51-52 ‘examples, 9,12, 14, 18-19, 22, 24, 26, 28-33, 35, 38-40, 43 45147, 50, 32°53, 35-56, 58-63, 65°71, 73-74, 76:80,Index 199 83, 86, 93, 96-97, 9, 102, 104, 106, 108, 111-12, 117-19, 121 -generie statement, 31~ 182-83, 93, 9, 102 statement, 30-31, 43, 46,62 67,83 quick reference guide, 189-90 42-43, xTsep, 54, 56-60 xTsee_ msg, 116-19 xT3exb, 54, 60-63 Xilinx, 4 XNOR gate, 11-20, 170-71 XOR gate, 11-19, 169-70,_— uy 19574000 1B1P 098011337