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Silicon On Insulator (SOI) Devices: Navakanta Bhat

This document summarizes silicon on insulator (SOI) device technology. It discusses how SOI devices are built on a thin silicon film on an insulator, offering benefits like reduced capacitance and improved radiation hardness compared to bulk devices. SOI can provide over 30% lower delay and 70% lower power for the same speed. The document also discusses applications of SOI technology for VLSI ICs, flat panel displays using polycrystalline silicon on glass, and 3D ICs. Methods for fabricating SOI structures like SIMOX and issues in poly-silicon thin film transistors are outlined.

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Virendra Mehta
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34 views

Silicon On Insulator (SOI) Devices: Navakanta Bhat

This document summarizes silicon on insulator (SOI) device technology. It discusses how SOI devices are built on a thin silicon film on an insulator, offering benefits like reduced capacitance and improved radiation hardness compared to bulk devices. SOI can provide over 30% lower delay and 70% lower power for the same speed. The document also discusses applications of SOI technology for VLSI ICs, flat panel displays using polycrystalline silicon on glass, and 3D ICs. Methods for fabricating SOI structures like SIMOX and issues in poly-silicon thin film transistors are outlined.

Uploaded by

Virendra Mehta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Silicon On Insulator (SOI) Devices

Navakanta Bhat

Associate Professor
ECE Department
IISc., Bangalore

Dr. Navakanta Bhat, IISc


Outline

SOI device technology for VLSI IC’s


Silicon on SiO2

SOI device technology for flat panel displays


Polycrystalline Silicon on glass/quartz

SOI device technology for 3-D IC’s


Single crystal like Silicon on inter-level deposited oxide

Dr. Navakanta Bhat, IISc


SOI versus Bulk Device
SOI Bulk
Si film
(100nm)

Insulator
500µm
Si wafer/
Insulator Si wafer

Devices are built on thin Si film (~100nm) on insulator


Handle Si wafer may be underneath the insulator (VLSI)
Insulator itself may form the rest of the substrate (Displays)
Dr. Navakanta Bhat, IISc
Radiation hardness
SOI Bulk
α- particle α - particle

Insulator + -
+ - + -
+ - + -
+ -
SOI concept is not new (Silicon On Saphire, 1978)
Restricted only to niche applications :
Charge collection is decreased significantly in SOI device
Ideal for space application
Dr. Navakanta Bhat, IISc
CMOS device technology
NMOSFET PMOSFET
n+poly p+poly
oxide oxide
n+ p n+ p+ n p+

Silicon Silicon

CMOS Inverter
Vdd
Vout
PMOS
IN OUT

NMOS
GND Vin
Dr. Navakanta Bhat, IISc
Power-Delay metric in CMOS device technology
Vdd

Ids

IN OUT
CL
Ids

P=CL*Vdd2*f D= CL*Vdd /Ids

CL , total capacitance at the switching node


Vdd , supply voltage
f , switching frequency
Ids , charging or discharging current

Dr. Navakanta Bhat, IISc


Components of node capacitance

CL=Cg + Cj + Ci
Cg = gate oxide capacitance Cj= εs∗A/Wd
Cj = junction capacitance εs , permittivity of Si
A , cross section area
Ci = interconnect capacitance Wd , depletion width

Dr. Navakanta Bhat, IISc


Other SOI specific effects
Drain current overshoot

Lower body effect

Better sub-threshold slope

Fewer processing steps

Better isolation resulting in dense circuits

Absence of latch-up problem

Threshold voltage (Vt) instability due to DC floating body effect

Dr. Navakanta Bhat, IISc


SOI device delay

SOI results in at least 30% lower delay compared to bulk


The improvement is more pronounced at lower voltages
due to non-scaling of threshold voltage (Vt) for bulk technology

Dr. Navakanta Bhat, IISc


SOI Power dissipation

SOI results in about 70% lower power for the same speed

Dr. Navakanta Bhat, IISc


Moore’s law

“Cramming more Components onto Integrated Circuits” “VLSI: some fundamental challenges”
Gordon E. Moore, Electronics 1965, p. 114. Moore, IEEE Spectrum 1970, p.30.
The bold extrapolation in 1965 by Moore was a challenge
to the industry to show the determination to lead a revolution
Moore proved his vision, by guiding INTEL
along his predicted trajectory
Moore who studied Chemistry in college is yet
another example to reiterate the fact that most
of the technological revolutions have their
origin in basic sciences

“Moore’s law governs the Silicon revolution” The components per chip is now doubling
Bandyopadhyay, Proc. of IEEE, 1998, p.78 once every two years instead of once a year
Dr. Navakanta Bhat, IISc
Scaling with SOI

SOI technology gives performance boost by at least


one generation, without going for new tool set and fab

Dr. Navakanta Bhat, IISc


SOI Cost

The cost of the SOI wafer is still about 5 to 10 times bulk wafer

Dr. Navakanta Bhat, IISc


SIMOX
Separation by the IMplantation of OXygen
O2 implant N2 anneal at 1350oC

Silicon
Silicon bulk wafer

High dose (1018 /cm2), high energy (> 150KeV) implant required

High temperature anneal to react Si and O and remove implant damage


Very low wafer throughput (20 to 40 wafers / day / implanter)

Dr. Navakanta Bhat, IISc


Active Matrix Liquid Crystal Display
(AMLCD)

Xerox, PARC
The substrate should be transparent : glass , quartz

Dr. Navakanta Bhat, IISc


Poly-Si Thin Film Transistor
gate electrode
deposited
gate oxide
poly-Si
grains n+
n+

Grain
boundary
Glass / SiO2

ISSUES
Deposited gate oxide quality and reliability
Grain boundary traps in the channel

Dr. Navakanta Bhat, IISc


Hydrogenation to passivate traps

Min Cao, Ph.D. thesis, Stanford


Hydrogen plasma or Hydrogen ion implantation can be used
Device trans-conductance and current improves significantly

Dr. Navakanta Bhat, IISc


Reliability issue with hydrogenation

N. Bhat, Ph.D. thesis, Stanford


Electrons can gain sufficient energy under moderate field
Energetic electrons break Si-H bonds, the atomic H results in
secondary damage by reacting with Si-H bonds
The long term reliabilty degrades with higher hydrogen content
Dr. Navakanta Bhat, IISc
Solid phase re-crystallization

Y. Uemoto, IEEE TED, 1992


CVD amorphous Si deposition at ~ 500oC
Re-crystallization anneal at 600oC for 20+ hours
Fewer nucleation sites and lower grain boundary traps
Dr. Navakanta Bhat, IISc
CMP of as deposited poly-Si

Surface roughness of as deposited poly-Si


CMP TFT results in performance
comparable to SPC TFT with
lower thermal budget

Min Cao, Ph.D. thesis, Stanford


Surface roughness after CMP process
Dr. Navakanta Bhat, IISc
Laser recrystallization

Min Cao, Ph.D. thesis,


Stanford
XeCl laser re-crystallization at low temperature
α -Si is melted using laser, and is re-grown into poly-Si
Low thermal budget, but low throughput

Dr. Navakanta Bhat, IISc


Metal Induced Lateral Crystallization (MILC)
W
n+ gate

Tox Oxide
n+ source n+ drain
L

p substrate

current flow from source to drain

Can we have a single grain from source drain?

Dr. Navakanta Bhat, IISc


Nickel mediated MILC

SiO2
α - Si deposition and island formation
Cap α - Si with deposited SiO2
α - Si

Open contact holes at the drain side Nickel


Sputter deposit Nickel in contact holes
MILC at 550oC for required time

Ni and Si form silicide mix (NiSi2)


NiSi2 lowers free energy for α-Si to c-Si c - Si
conversion at NiSi2:α -Si interface

Dr. Navakanta Bhat, IISc


MILC device performance - I

IEEE TED June 2001


Very good electron and hole mobility are obtained

Dr. Navakanta Bhat, IISc


MILC device performance - II

IEEE TED July 2001


MILC device (top) performance with post-MILC anneal
at 900oC is comparable to the c-Si SOI device (bottom)
Dr. Navakanta Bhat, IISc
3-D Integrated Circuits

SRAM cell with poly-Si pull up transistor

Repeaters for global interconnects using MILC devices

Complex logic blocks in 3-D using MILC devices

Dr. Navakanta Bhat, IISc


Interconnect delay in DSM technology
Intrinsic gate delay

Delay

Interconnect delay

0.18 0.25 0.35 0.5


Technology node (µm)
Gate delay decreases due to decrease in gate capacitance
Interconnect delay increases due to decreasing metal line width
and increasing intra-metal coupling capacitance
Interconnects are no longer afterthought in DSM technology
Dr. Navakanta Bhat, IISc
Repeaters on multiple layers
Interconnect delay = 0.35 * r * c * L2

r = Resistance per unit length of interconnect


c = Capacitance per unit length of interconnect
L = Length of the interconnect line

0.35 * r * c * L2

0.35 * r * c * L2/ 4 0.35 * r * c * L2 / 4

Repeater

Dr. Navakanta Bhat, IISc


Complex logic blocks in 3-D
Second layer
SiO2
First layer

SiO2

Silicon

Open issues
Process: Impact of thermal budget of higher layer device
processing on the devices underneath
Device: Layout strategy and interconnect routing
Circuit: Noise coupling through back gate effect

Dr. Navakanta Bhat, IISc


Conclusions
• SOI devices are desirable for mainstream VLSI applications
• SOI wafer cost needs to be decreased
• New device and circuit design strategies are required to
overcome DC floating body effects
• SOI devices are indispensable in display applications
• Low thermal budget processes are required to be able to
use low cost glass substrates (low strain point glass)
• Gate oxide and poly-Si substrate quality needs improvement

• MILC is a promising technique for single grain transistor


• 3-D VLSI circuits could become reality, provided the
process, device, and circuit issues are addressed
Dr. Navakanta Bhat, IISc

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