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Dokumen - Tips Full Adder Using 4x1 Mux

This document describes designing a full adder using a 4x1 multiplexer in Verilog HDL. It includes the logic diagram and source code for the full adder module and multiplexer module. The full adder module uses two 4x1 multiplexers - one for the sum output and one for the carry output. The inputs to the multiplexers are determined by the values of inputs A, B, and Cin. The output waveform is also shown verifying the design works as a full adder.

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Mr Miracle
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514 views3 pages

Dokumen - Tips Full Adder Using 4x1 Mux

This document describes designing a full adder using a 4x1 multiplexer in Verilog HDL. It includes the logic diagram and source code for the full adder module and multiplexer module. The full adder module uses two 4x1 multiplexers - one for the sum output and one for the carry output. The inputs to the multiplexers are determined by the values of inputs A, B, and Cin. The output waveform is also shown verifying the design works as a full adder.

Uploaded by

Mr Miracle
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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5/21/2018 Full Adde r Using 4x1 Mux - slide pdf.c om

FULL ADDER USING 4X1 MUX

Aim:

To design a full adder program using multiplexer by Verilog HDL program under Altera
 – 
 Quartus II 9.0 web Editor tool.
Tools required:

Altera  –  Quartus II 9.0

Design:

Sum Cout
A B Sum Cout
Cin=0 Cin=1 Cin=0 Cin=1
0 0 0 1 0 0 Cin 0
0 1 1 0 0 1    
 Cin
1 0 1 0 0 1 
    Cin
1 1 0 1 1 1 Cin 1

Logic Diagram:

Source Code:

module fa_mux(sum,cout,a,b,cin);
output cout,sum;
input a,b,cin;
wire cinb;

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5/21/2018 Full Adde r Using 4x1 Mux - slide pdf.c om

mux m1(.z(sum),.d0(cin),.d1(cinb),.d2(cinb),.d3(cin),.s0(a),.s1(b));
mux m2(.z(cout),.d0(0),.d1(cin),.d2(cin),.d3(1),.s0(a),.s1(b));
assign cinb=~cin;
endmodule

module mux(z,d0,d1,d2,d3,s0,s1);
input d0,d1,d2,d3,s0,s1;
output z;
reg z;
always @(d0 or d1 or d2 or d3 or s0 or s1)
 begin

case({s0,s1})
2'b00: z<=d0;
2'b01: z<=d1;
2'b10: z<=d2;
2'b11: z<=d3;
endcase
end

endmodule

OUTPUT WAVEFORM:

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5/21/2018 Full Adde r Using 4x1 Mux - slide pdf.c om

RESULT:
Thus we have designed a full adder using multiplexer by Verilog HDL program under
Altera  –  Quartus II 9.0 web Editor tool.  

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