OVONIC UNIFIED MEMORY

1. Introduction

2. An overview of emerging semiconductor memories

3. Ovonic unified memory

4. constructional details

5. Storage principle

6. Read /write principle

7. Basic circuit explanation of ovonic memory cells

8. Oum advantages

9. Oum disadvantages

10. About the future

 Introduction

A memory system is basically a datastorage system ,datas to be stored are 1’s and 0’s. these data stored can be read later.A 2D memory system is represented by
rows and columns sothat each row-column pair represents a particular memory cell.
Memory systems are classified basically into two types:
Volatile memory
1.
Nonvolatile memory
2.

Volatile memory

As the name suggests volatile memory does not retain its stored data after the power supply is switched off.The main representative of the type is the RAM.In
RAM the logic information is stored either by setting up the logic state of a bistable flipflop such as in SRAM or through charging of capacitor as in DRAM.In
both cases data is lost when the power is switched off.Besides in DRAM once the information is stored an additional process called refreshing is done to maintain
the stored information
DRAM has been the technology driver for very and ultra large scale integrated technology in the last century owing to its fast writing,fast reading,high packing
density,low cost per bit.Due to its high volatile nature it is not convenient in portable computation equipments approaches used to solve these are battry back up
and switching to non volatile memory when power is switched off.Battery back up is limited by its shelf life and is not reliable .The best choice to retain the data
without lose is Nonvolatile memory

Non volatile memory

Non volatile memory enables data to be stored even if power supply is switched off.The data storage mode is either permanent or reprogrammable depanding on
the technology and is normally referred to as Read Only Memory (ROM) that is fabricated on silicon.
Rom are of four groups:
1.Programmable ROM (PROM)
2.Erasable or ultraviolet erasable ROM(EPROM)
3.Electrically erasable ROM(EEPROM)
4.Flash EEPROM or Flash memory
PROM can be written only once and cannot be reprogrammed.Inorder to erase and reprogramme or modify the date two types of upgraded proms where invented
depending upon the erasing technique.EPROM stores its data by injecting and traping hot electrons into a floting poly silicon gate and data Is erased by UV light
Next comes the electrically erasable prom which needs high erasing time since erasure operation is done byte by byte .
Modern generation device is the flash EEPROM or flash memory it’s the cuurent most popular nonvolatile memory owing to the hybrid characteristics of flash
access of ram and of

nonvolatile characteristics of ROM.Used widely in PDA digital cameras and MP3 audio recorders
The demand for non volatile semiconductor memory is increasing mainly due togrowing number of portable(mobile),compact and light weight electronic
equipments,appliances such as mobile phones and laptops
Non volatile memory have the ability to retain store information for longer than 10 years at temperatures as high as 80 degree Celsius even without power supply.
Conventional silicon based non volatile memories can with stand only 10^6 discharging/charging cycles.

An over view of emerging semiconductor memory

MRAM​:

Magnetic RAM As its name suggests, it uses magnetism rather than elec-trical power to store data.
How MRAM works: MRAM technology is a non-volatile memory technology that uses magnetic, thin-film elements on a silicon substrate. (Non-volatility is
crucial for certain devices that benefit from a solidstate design requiring no periodic refreshing through electrical impulses). Pulsing wires, which are
perpendicular to each other, allow data to be written and read. The perpendicular wires are arranged with one set above and one below the magnetic bits. It stores
data through magnetic polarity held in a crosschecked set of magnetised switches. The .magnetic tunneling junctions. are tiny layers of two magnets and an
intervening tunneling barrier. The magnetic tunnel consists of two layers of ferromagnetic material separated by a non-magnetic barrier. When the spin
orientation of electrons in the two ferromagnetic layers is identical, a voltage is quite likely to pressure the electrons to tunnel through the barrier, resulting in high
current. But flipping the spins in one of the layers restricts the current flow. Tunnel junctions are the basis of the MRAMs developed by IBM and Motorola.
Advantages of spintronics are:
1.A fraction of the power will be used as compared to conventional electronics be
cause much less energy is used to flip spins as compared to push around charge.
2. Non-volatility.
3. Devices that could work directly with polarised light, and memory elements that could be in two different states at the same time.

One magnet can spin, so that the whole assembly can have the magnetic fields in align-ment (providing low resistance and a 0 bit), or have them in polar
opposition (giving high resistance and a 1 bit). Because it is written in magnetic fields, no external power is needed to store data. Because MRAM bits can be
stored on a standard chip, it allows the incorporation of both memory and processors on the same chip. This means that new computers could be built without
bulky hard drives, or the computing power of a PC can be installed into a PDA or cell phone!

MRAM vs FlashRAM: At some point, MRAM technology could be used to replace Flash memory. Write speeds faster than those possible with Flash technology
would be possible because MRAM eliminates the high-voltage tunneling re-quired by Flash. Unlike DRAM and SRAM, Flash can hold data without power by
using transistors separated by a tun-neling barrier. Flash chips, however, cannot be endlessly rewritten without loss of data, while the new MRAM will not have
that limitation.

FRAM​:
Short for Ferroelectric RAM, FRAM is a type of random-access storage that uses a special magnetic film. What makes FRAM promising is the ability to retain
the data when power is turned off as well as higher speeds than that of DRAM and SRAM. It writes faster than Flash and, unlike EEPROMS, virtually never
wears out. It is being targeted at data collection and logging, and configuration storage (re-placing CMOS). It.s also aimed at providing non-volatile buff-ers in
places like ATMs and banking systems to make them less vulnerable to power out-ages during transfers.
Conventional memories can read well, but write perfor-mance is less satisfactory. They either take too much time to write, or they have limitations to their writing
from ten thou-sand to one hundred thousand times. However, FRAM.s fast write/read operation signifi-cantly improves transaction time, whilst the method used
for programming FRAM makes it ideally suited for large memory arrays. FRAM memory has as fast operations as SRAM and has millions of times the written
capability of FLASH.
The physics of FRAM: Despite the name, FRAM contains no iron; the chips contain ceramic crystals like BaTiO3 that take on positive or negative polar-ity when
hit with an electronic charge. Every memory chip needs a .two-state. device to represent each stored 1 or 0. In a FRAM, the storage ele-ment is a crystal cell. In
the centre of the cell is an atom that can exist in either of two stable positions. The atom is shifted into one position or the other by the application of an external
electric field. Generally, ferroelectric thin film has alarger dielectric con-stant than a buffer layer insu-lator. For the more remnant polarisation in the ferroelec-tric
material, the lesser volt-age must be applied to the buffer layer insulator, at some given operation voltage. Once the atom has been moved, it will remain in
position with-out the external field and is thus .non-volatile.
FRAM can replace DRAM, SRAM, ROM and EEPROM chips with a single memory
type. FRAM combines high-performance and low-power operation, and is expected to revolutionise a variety of elec-tronic consumer and industrial products.
Current applications include:
Electronic power meters
Smart cards
Test instrumentation
Factory automation
Laser printers
Security systems

and other systems that require reliable storage of data with-out an external power source.
Because of its low power re-quirements, it could also be used in devices that only need to activate for brief periods (e.g., a subway pass that pow-ers up as you
pass through an electronic field, registers you passing through the gate, and then powers down).
Data is read by applying an electric field to the capacitor. If this switches the cell into the opposite state (flipping over the electrical dipoles in the ferroelectric
material) then more charge is moved than if the cell was not flipped. This can be detected and am-plified by sense amplifiers. Reading destroys the contents of a
cell which must therefore be written back after a read. This is similar to the PRECHARGE operation in DRAM, though it only needs to be done after a read rather
than periodically as with DRAM refresh.
FRAM can be divided as 1T/ 1C and 1T, by their structure and operation. The ferroelec-tric thin film is used as a nonlinear capacitor, and the memory content is
read destructively. One MFSFET (Metal-Ferroelectric material-Semiconductor Field Effect Transistor) transistor can be operated as one memory ele-ment. In this
structure, the cell size can be reduced 1.5 times less than in the 1T/1C struc-ture, and memory-reading op-eration is non-destructive, so the power consumption
could be reduced. The basic storage cell of a ferroelectric memory chip is made up of a transistor to switch the power on and off, and a capacitor to store a charge
representing one bit of stored information.
Like all memory devices, a FRAM.s capacitors can flip be-tween two different but rea-sonably stable states that rep-resent the two bits, 0 and 1.
In each cell, the bit-storing capacitor is coated with a thin film of a material that polarises (changes from posi-tive to negative charge or vice versa) when a
voltage is ap-plied to it.
Advantages and disadvantages of FRAM: FRAM gives a recipe for a perfect memory chip. The goal is to match the capacity, cost and speed of dynamic random
access memory chips (DRAM) in a nonvolatile memory. Major technical improvements have reduced its two-transistor/ two-capacitor design to a
one-transistor/one-capacitor de-sign, thereby cutting the cost of manufacturing.
But in FRAM, the chip.s two switching states are not very stable. For reasons of reliabil-ity, therefore, an extra tran-sistor and capacitor are added to each cell as a
back up. That takes up valuable storage space, making the chip bigger and costlier than it need be. Also, it still has a laughably small storage capacity com-pared
with even the ageing 64 MB DRAM used in today.s PCs. The biggest ferroelectric chips at the moment are 1 MB experimental devices. The chips. innards will
have to be shrunk dramatically, so that hundreds of times more data can be crammed in.
One of the reasons of instabil-ity in the ferroelectric proper-ties is that the thin films used are polycrystalline. On the other hand, a single crystal-line thin film has
Stable properties
Large remnant polarisation
Ideal isotropic property to investigate easily the mechanism of fatigue and phenomena

FRAM applications: The quick write capability and reliabil-ity of FRAM is particularly suitable for metering devices. Its low power requirements make it useful
in low power instrumentation, such as glucometers, which measure blood sugar levels for diabet-ics, GPS receivers, and cordless phones. It is expected to have
many applications in small consumer devices such as personal digital assistants (PDAs) and smart cards, and in security systems and can become a key
component in future wireless products.

Ovonic unified memory

Ovonic Unified Memory (OUM)or ChalcogenideRAM(CRAM) is an inexpen-sive, non-volatile memory device that is virtually impervious to radiation damage
or hostile electronic interrogation.The major factors aiding in the development of C-RAMs have been:
Alloys capable of rapid crystallisation have been de-veloped for use in the rewritable optical disks.
Lithographic scaling and processing improvements have reduced the program-ming requirements of new cell designs to realise minimum geometry for MOS
transistors.
All the signs are phase-change semiconductor memory de-vices. C-RAM with the capa-bility to replace Flash, DRAM, and SRAM chips will soon be in the
offing.
Ovonics is a new alloy layer on silicon to make faster non-volatile memory chips, which retain data when no electrical current is present.
Chalcogenide materials or amorphous semiconductor materials have the key char-acteristic of changing phase from the amorphous to crys-talline state when
subject to laser heating or electrical pulsing.
C-RAM is a device that is able to hold a high or low conduc-tion value, even in the absence of any type of current or volt-age, and therefore can be used to store a
set conduction level. The device consists of a bistable Chalcogenide alloy between two metallic elec-trodes. Thermal energy is supplied to the material in the form
of a current/voltage pulse through the electrodes. The transition of the material from a highly amorphous structure to a polycrystalline structure is accomplished
ac-cording to the prior section, by forming a crystalline fila-ment between the electrodes.
The filament is created to-wards the centre of the device where the energy is the great-est. Areas of the material out-side of the crystalline filament remain in an
amorphous state. A current pulse with a long duration is supplied to the bistable material to transition it to a polycrystalline state, while a pulse with a high
am-plitude and short duration is used to place the material back into an amorphous structure, removing the formed crystal-line filament. Phase change in that can
change from a disordered, or amorphous, atomic state to a crystalline state, with a highly ordered atomic structure can be used to generate the ones or zeros
needed for digital products. In a C-RAM cell, a tiny volume of the chalcogenide film is converted between the crystalline phase with low resistance and the
amorphous phase with high resistance by resistive heating from programmed current pulses. Conversion between the phases gives rise to change in resistivity on
several orders of magnitude. Changing the electrical pulse width or amplitude here can control state change. When a current pulse switches the device into a
con-ducting interim .dynamic. state between the amorphous and crystalline phase, the programming (change of phase) can occur. Then the data is read by
non-destructive de-tection of the cell.s resistance. This electronic solidstate memory stores data in a much smaller area and with higher speeds for both read and
write than its optical counterpart (see Figures 2 and 3).
Ovonic memory has some inherent benefits. It stores data in much smaller cells than in conventional chips and reliably stores about 4 million bits of data. The
cells can read and write data much faster than flash chips, and seem to store data virtually forever.
(The digital data of 1s and 0s are stored as amorphous (high resistance and non-reflective) or crystalline (low resistance and reflective) structures. OUM devices
store data in a similar manner but use electrical energy controlled by small transistors to electronically convert the material to crystalline or to amorphous (thus a
1 or a 0). This electronic solidstate memory stores data in a much smaller area and with higher speeds for both read and write than its optical counterpart.

Applications​: C-RAM technology uses a conventional CMOS process with the addition of a new additional layer to form the thin-film memory.
The C-RAM cell provides for excellent memory proper-ties. The memory storage is non-volatile. A computer using C-RAM could be turned off, then turned back
on immediately or 10 years later and start right up where one left off! This is one feature
that we have seen that is common to all upcoming memory systems. Unlike present day computers using DRAM or SRAM, C-RAM is not subject to critical data
loss when the system hangs up or when power is abruptly lost.Portable applications where battery size and operating time between charging are key competitive
metrics.
The flat topology, small size, and the low voltage operation make C-RAM technology highly scalable to smaller geometry. Cell performance improves with
shrinking, avoiding many of the scaling barriers arising in conventional charge-based DRAM and Flash technologies. Also enabling shrinking, the CRAM
provides higher speed active read current from its thin film memory media, avoiding the fixed charge read approach of a DRAM with related test, noise, and soft
error problem.

Prospects​: C-RAM is highly expected to replace current memory and storage solutions such as FLASH, Electrically Erasable Programmable Read-Only Memory
(EEPROM), DRAM and hard disk drive de-vices, thus opening a vista of new scenarios. C-RAM may one day sufficiently pervade commercial memory products
and revolutionise the entire computing industry, from smart appliances and desktop computers to new kinds of consumer products.

Constructional Details

The term “chalcogen” refers to the Group VI elements of the periodic table. “Chalcogenide” refers to alloys containing at least one of these elements such as the
alloy of germanium, antimony, and tellurium discussed here. Energy Conversion Devices, Inc., has used this particular alloy to develop a phase-change memory
technology used in commercially available rewriteable
This phase-change technology uses a thermally activated, rapid, reversible change in the structure of the alloy to store data. Since the binary information is
represented by two different phases of the material it is inherently non-volatile, requiring no energy to keep the material in either of its two stable structural states.

The two structural states of the chalcogenide alloy, as shown in Figure 1, are an amorphous state and a polycrystalline state.
The ground ovonic material is Ge​ Te​ S​ Sb​ .
15​ 81​ 2​ 2​
This is a memory material. It is analogous of Ge​ Te​ that represents an eutectic composition in the binary system Te-Ge (eutectic temp. 375 oC). Addition of S
15​ 85​
and Sb changes the crystallization speed when the material is heated in the glassy state. Starting from the glassy state, heating up to temperatures 140 <T< 240 oC
leads to the formation of Te and GeTe. Further heating leads to the dissolving of crystallites and formation of the liquid phase. When the liquid is slowly cooled,
polycrystalline low resistivity material is obtained. During cooling from the crystallization temperature (140<T<375 oC) down to room temperature all the
crystallites are maintained independently on the rate of cooling
Relative to the amorphous state, the polycrystalline state shows a dramatic increase in free electron density, similar to a metal. heat the material to change states.
Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is working with several commercial partners to develop a solid-state nonvolatilememory
technology using the chalcogenide phase change material15-18 . To implement a memory the device is incorporated as a two terminal resistor element with
standard CMOS processing. Resistive heating is used to change the phase of the chalcogenide material.

Low programming currents are very important in OUM. The size of a transistor capable of sourcing sufficient current to program an OUM device is
much larger than the device [21] Several clever techniques can be used to decrease the effective size of the OUM device. Further, heat can be generated not only
by the thermalization in the memory material itself, but by use of resistive contact materials. Fig. 7 shows a basic OUM cell structure. The region within the
chalcogenide film that is programmed is where the current is at its highest density, where the bottom contact forms the smallest area. The heater can be formed at
smaller dimensions than the current source transistor using the same lithographic techniques, and so the overall device area can be decreased.
 Fig. 7​. Basic OUM device structure​.

Device lifetimes have been shown to exceed 1013 cycles [22]. In principle, lifetime is infinite as it is when water is frozen and re-melted. Mechanical
limitations in actual device structures can limit lifetime, and they are being successfully addressed. The devices can be programmed to intermediate states
between the fully amorphous and the fully crystalline, and so multiple bits can be stored in each cell. Sixteen clearly distinguished levels have been demonstrated
[23] The device resistance can theoretically be programmed to all levels between the highest and lowest, and as the technology matures more levels will be used
to store larger numbers of bits per cell. OUM can be applied not only as leading memories as Flash, DRAM and SRAM, but also in a variety of other products
including FPLD, FPLA, embedded macros, SOC macros and more. Its ease of fabrication and compatibility with conventional silicon devices using minimal
added steps and excellent scaling position it as an ideal memory technology for generations of products to come.

Data storage mechanism

The amorphous semiconductor memory materials which form the basis of Ovonic memory devices store information through changes in their atomic structures
caused by application of an energy pulse. These materials, which are multi-element chalcogenide alloys, can exist in a stable fashion in amorphous and crystalline
structures, and also in a range of “intermediate” structural states.
These different atomic structures have different characteristic physical properties, including different values of electrical conductivity. The ability of a memory
device to be programmed to stable intermediate structures allows for storage of multiple bits of information in each memory cell location, to which we refer as the
multi-state programming mode. The memory cell in the Ovonic Universal Memory (OUM) is programmed by application of an electrical pulse. The most
important programming parameter is the current amplitude, although other characteristics, including pulse width and rise and fall tie, describe an “overall pulse
profile”, which affects the programming characteristics in a secondary fashion. OUM devices can be programmed to exhibit electrical resistance values that are
directly related to the magnitude of programming current passed through the device. The electrical characteristic of the device during the programming pulse are
essentially the same as those of a related thin film chalcogenide alloy device, the Ovonic threshold switch. Both the threshold switch and the memory device show
a non-ohmic, super-linear, low-field resistance, although a linear approximation is good at electrical fields below 104 V/cm.

Ovonic universal memory cell data.

Data Binary mode devices Multi-state devices

Programming Endurance 1013 cycles without 108 cycles without failure/test

failure/test discontinued discontinued
 Data retention 10 years at 100 oC Under test

Biased data stability Not affected by bias Not affected by bias voltage below
voltage below device device switching threshold
switching threshold

Programming voltages Less than 2 V Less than 5 V

Programming currents 0.2 mA 1 mA to 4 mA

Programming times 1 ns to 400 ns 1 ns to 400 ns

Low resistance state 5 k​W​ to 20 k​W 1 k​W​ to 20 k​W

High resistance state 20 k.​W​ to 1 M​W 20 k​W​ to 100 k​W

The Ovonic memory devices store the programmed information in a non-volatile manner using the high contrast between the high resistance, low optical
reflectivity amorphous state and the low resistivity , high reflectivity crystalline state. The phase change is initiated by short light or electrical pulses of different
intensity and time shape. High speed and low energy programming requires a material that undergoes the phase changes with minimum motion of the constituent
atoms.

How to read and write data

Data storage is accomplished in an OUM cell by a thermally induced phase change between amorphous and polycrystalline states in a thin film of chalcogenide
alloy similar to the materials used in rewriteable CD and DVD optical disks. This rapid, reversible structural change in the GexSbyTez alloy film results in a
change in material resistivity that is measured during the read operation. OUM technology uses a short electrical pulse to achieve the amorphous state (high
resistanceRESET state) and lower but a bit longer current pulse to convert to the polycrystalline state (lower resistance SET state). The portion of the alloy film
near a bottom resistive electrode changes state as a result of joule heating during the programming pulse [1]. Because of the small programmable volume of the
film, the programming energy is small – suitable for portable communication applications.
Figure 4 shows the temperature simulation of the device at the two types of voltage supply, short and high Fig 3. Direct overwriting method by optical mean only

RESET(10—20nsec) pulse and long SET(20 ---80nsec) pulse respectively Otherwise, Electronic device is static mode, the electrode is fixed and we can supply

different pulse width voltage pulse for RESET(amorphous) and SET(crystalline). Figure 5 shows multiple oscilloscope traces of the Electronic cycling operation

characteristics of the Phase Change-RAM(OUM) memory cell element. Each trace is a series of 4 sequential operations, write /read /erase /read, cycling at 5MHz.

An 8ns RESET pulse is applied with a ~5ns falling edge The subsequent read shows a programmed resistance of 85Kohms. Next application of a SET pulse of

85ns results in a resistance of 2Kohms. The beginning of the SET pulse shows the device threshold voltage, Vth to be approximately 0.6V. The Electronic

recording energy is calculated by the SET and or RESET pulse voltage (V), current (I) and the applied pulse width t. The current data is obtained from the (V-I)

curves of Fig. 6, in the SET state, V – I curve shows linear relation and RESET amorphous state shows non-linear relation. The RESET current becomes 500uA

at the RESET voltage is 0.6V and the RESET pulse with t is 85ns. The recording energy of the cell in this case the RESET energy is calculated as 2.5pJ/ cell. The

cell dimension of this 180nm design rule is almost the same dimension of the mark of Phase Change optical disk of 0.8nJ and the recording energy of Electronic

memory cell is remarkably smaller than optical memory. One of the reason of this small energy is related the programmable volume in Fig. 8.

Basic circuit explanation of ovonic memory system

 Referring now to the figures of the drawing in detail and first, particularly in fig 12.4.4 thereof, there is shown a section of a prior art non-volatile memory
cell. The non-volatile memory cell has a selection transistor formed from a emitter region, a base region, and a collector region. A resistance element is connected
to the emitter region. The element is operated as a heating resistor and it is surrounded by an insulation layer 6. Situated at that end of the resistance element
which is remote from the emitter of the bipolar transistor is a layer of an ovonic memory material , in which the information is to be stored. A contact-making
layer is connected to the memory material in order to make contact with the memory cell.The "ovonic" memory material is a material from the group of
chalcogenides, which are usually formed from alloys.
The memory cell shown therein has a heating device with a bipolar transistor and a heating resistor. The heating resistor is provided in
direct proximity to the memory material. The memory material and the heating resistor are connected in series with the emitter of the bipolar transistor.
Depending on whether reading or writing is to be effected, a specific voltage is present between that terminal of the memory material which is not connected to
the heating resistor and the collector of the bipolar transistor. The current through the memory material and the heating resistor can be controlled via the base
input of the switching transistor.When the memory cell thus formed is written to, a write voltage, lying above the read-out voltage required for the read-out, is
applied as the specific voltage. Through activation of the bipolar transistor with the aid of a control signal applied to the base input, current flows through the
memory element, the heating resistor and the bipolar transistor. The current heats the heating resistor and thus the memory material provided in direct proximity
to the heating resistor. The heating is controlled by the control signal at the base input and the memory material is heated in this way slowly or rapidly until it
melts. After cooling or resolidification, the memory material assumes a high-resistance amorphous or low-resistance polycrystalline state.

Advantages of Ovonic memory

 1.​Very low voltage programming.
The maximum programming voltage needed is just 2V thus is very much suited for hand held devices like mobile phones thus saving the battery power

2.​Radiation resistant.
Since chalcogenide materials are stable towards radiation since the material is stable in its crystalline or amorphous form, thus is very much suited for
memory systems space crafts and for all outer space researches

3.​Highly scalable.
The chalcogenide material is heated to achieve the phase change thus as the volume of it increases power requirement is higher,as a result researches are
towards scalability.At present it is possible to scale upto micrometer level of integration and the limitation for further scalability lies Photolithography

4.​Reduced cost per bit.

The materials required for the making up of the ovonic cells are only the Ge-Sb-Te alloy and a bi junction transistors which are cheaply available

5​.Data retention.
It means ability of a memory system to hold the information for time and temperature. It is calculated it can store data for more than 10 years without any
errors.Thus refreshing process is not required

6.​Endurance.

It gives an idea of how many times the memory cell can be programmed. It is estimated that the cells can undergo 10^12 set/resetcycles

7.​High speed read and write operation.

The average time for programming is found to be 400ns,which is fastest compared to existing flash memory.

8. ​Multi state storage.

It enables multiple bit storage by proper control of the write voltages,thus is very much efficient.

9.​Bit by bit data erasure.

In the existing flash memory the require for erasure of a cell is greater than 100ms,moreover bit by bit erasure is not possible where as in the case of
ovonic memory cell bit by bit erasure is possible thus programming a cell is needed if its existing state be changed.

10.​Easy data retrieval.

The logic information stored in cells can be easily retrieved since resistance variation (1kto100k) can be easily sensed.

Disadvantages of Ovonic Memory system

1. ​Bit change during programming.

Heat which is generated in a programming cell could spread to the adjacent cells and convert reset to set.

2. Leakage
​ in the switching transistor.
Even though the transistor remain off during the time of unprogrammed stage there exist leakage current which draws a slight amount of current thus causes
power wastage.
3.Limitations of photolithography
At present photolithography has scaled the cmos integration only up to micrometer range. In future the photolithography can be scaled to the nanometer
range to reduce the power requirement.
 About the future

Researches are going on all over the world for achieving following goals:

1.With the development of photolithographic process scaling is possible Recently it is possible to develop a 4Mb VLSI test memory at 0.18micrometer
lithography and the parameters obtained for this test memory are as follows:
Reset pulse with 8ns time period and amplitude of 0.8V.
Set pulse of 85ns time period and amplitude of 0.5V.
Reset resistance of 85Kohms.
Set resistance of 2Kohms.

2. In order to prevent the leakage current of the switching pnp transistor during the unprogrammed mode .Researches are continuing to integrate an FET along
with the transistor.

3.Researches are in developing photolithography to the nanometer scale,by achieving this the power requirement can be reduced effectively.

Bibilography

1. OUM: A 180 nm unified memory-A high performance non volatile memory technology for standalone and embedded applications by S.Lai and T.lowrey

2. Memory system-A byte of the future by Prof J.N.Rai,Siddarth Gaba and Prassana Santhanam

3. www.ovonyx.com

4. www.freepatentsonline.com

5. Non volatile memory Technologies-A look into the future by Stephan Lai,Vice President,TMG,Intel corporation