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    EC 14 603 VLSI Design, April 2017

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    anon_742948544
    This document outlines an examination for a VLSI Design course, including 8 questions worth 5 marks each (totaling 40 marks) and 4 questions worth 15 marks each (totaling 60 marks), for a total of 100 marks. The 5 mark questions cover topics like constant field scaling, CMOS ring oscillators, charge sharing, differential sense amplifiers, ROM logic, carry look ahead adders, molecular beam epitaxy, photoresists, multi-level metallization, and cell hierarchy layout. The 15 mark questions include more in-depth topics like pseudo NMOS inverter characteristics and power dissipation, factors affecting CMOS inverter robustness, carry select adder architecture

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    EC 14 603 VLSI Design, April 2017

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    anon_742948544
    41 views2 pages
    This document outlines an examination for a VLSI Design course, including 8 questions worth 5 marks each (totaling 40 marks) and 4 questions worth 15 marks each (totaling 60 marks), for a total of 100 marks. The 5 mark questions cover topics like constant field scaling, CMOS ring oscillators, charge sharing, differential sense amplifiers, ROM logic, carry look ahead adders, molecular beam epitaxy, photoresists, multi-level metallization, and cell hierarchy layout. The 15 mark questions include more in-depth topics like pseudo NMOS inverter characteristics and power dissipation, factors affecting CMOS inverter robustness, carry select adder architecture

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    vlsi design q paper

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    This document outlines an examination for a VLSI Design course, including 8 questions worth 5 marks each (totaling 40 marks) and 4 questions worth 15 marks each (totaling 60 marks), for a total of 100 marks. The 5 mark questions cover topics like constant field scaling, CMOS ring oscillators, charge sharing, differential sense amplifiers, ROM logic, carry look ahead adders, molecular beam epitaxy, photoresists, multi-level metallization, and cell hierarchy layout. The 15 mark questions include more in-depth topics like pseudo NMOS inverter characteristics and power dissipation, factors affecting CMOS inverter robustness, carry select adder architecture

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    41 views2 pages

    EC 14 603 VLSI Design, April 2017

    Uploaded by

    anon_742948544
    This document outlines an examination for a VLSI Design course, including 8 questions worth 5 marks each (totaling 40 marks) and 4 questions worth 15 marks each (totaling 60 marks), for a total of 100 marks. The 5 mark questions cover topics like constant field scaling, CMOS ring oscillators, charge sharing, differential sense amplifiers, ROM logic, carry look ahead adders, molecular beam epitaxy, photoresists, multi-level metallization, and cell hierarchy layout. The 15 mark questions include more in-depth topics like pseudo NMOS inverter characteristics and power dissipation, factors affecting CMOS inverter robustness, carry select adder architecture

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    c 22582 (Pages: 2)

    4R
    SD(TH SEMESTER B.TECH. (ENGINEERING) DEGRDE
    HGIVIINATION, APRIL 2OI7
    Electronics and Communieation Engineering
    EC 14 603_VLSI DESIGN
    Time: firree Hours Ma-imum: 100 Marks

    Answer any eight questinns.


    Each questipn canics 5 marks.
    1. (a) Give the principle of constant field scaling and its effect on device characteristics.
    (b) Discuss the operation of CMOS ring oscillator. Estimate its frequency.
    (c) Explain the problem of charge sharing and how it is overcome.
    (d) Discuss the operation of differential sense amplifier.
    (e) Explain the operation of ROM using pseudo NMOS logic.
    (f) Explain the logic behind carry look ahead adder.
    (S) Discuss the process of molecular beam epitaxy.
    (h) Outline the various types of photoresists.
    (i) Write short notes on multi-level metallization.
    0) Explain the layout process using cell hierarchy.
    (8x5=40marks)
    2. (a) (i) obtain the d.c. transfer characteristics of pseudo NMos inverter. (8 marks)
    (ii) Outline the reason for power dissipation andvarious sounces tha! lead to powerdissipation.
    (7 marks)
    Or
    (b) (i) Discuss the various factors that account to robustness of CMOS inverter. (8 marks)
    (ii) Explain channel length modulation and body effect. (T marks)
    3. (a) (i) Draw and explain the architecture of Carry Select Adder. Outline how it does increase
    the speed ofoperation.
    (10 marks)
    (ii) Explain the structure of 6T SRAM cell. (5 marks)
    Or

    Turn over
    c 2P6g2
    &) (i) Expla{n the architecturc of 4 x 4 aray multiplier with neat diagram. (10
    marks)
    (ii) Draw and explain the structure of 4 : l Multiplexer using transmission gate. (E
    marks)
    (a) (r) Erplain in detail the Deal - Gnove model of oxidation process. (10 marks)
    (ii) Writ€ short notes about ion implantation: (U ;;";;
    'Or
    (b) Define etching. Explain the principles of wet and ion etching. Differentiate
    the key points
    between them.

    (5 marks)
    (a) (i) Explain the steps involved in hrin tub process of CMOS fabrication. (10 marks)
    Iii) Discuss the lambda based desrsn nrles.
    (5 marks)
    Or
    (b) (i) Draw the stick diagram of NAITID gate. (6 marks)
    (ii) the principle of silicon on insulatorisolation. (10 marks)
    T*
    [4 x l5 = 60 marks]

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