International Journal of Current Engineering and Technology

ISSN 2277 - 4106

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Review Article
FPGA Implementation of 9 bit Universal Asynchronous Receiver Transmitter
Ashwini D. DhanadravyeȦ* and Samrat S. ThoratȦ
Ȧ
Department of Electronics and Telecommunication, Government College of Engineering Amravati, Maharashtra, India

Accepted 25 May 2014, Available online 01 June 2014, Vol.4, No.3 (June 2014)

Abstract

Universal Asynchronous Receiver Transmitter (UART) is widely used serial data transmission protocol to support full
duplex communication. This paper presents the design of 9 bit UART module based on VHDL. The design of 9 bit UART
specialized with automatic address and data differentiator in the character itself thus allowing the incoming data to be
transferred directly to the destination, in case address matches. UART design mainly consists of three important modules
which are receiver module, transmitter module and baud rate generator. The UART design with VHDL as design
language can be integrated into the Field Programmable Gate Array to achieve reliable, compact & stable data
transmission. It’s significant for the design of System on Chip. The whole design simulated using Active-HDL simulation
tool and implemented onto FPGA board using Quartus II software.

Keywords: Asynchronous serial communication, Quartus II, simulation, VHDL, UART

1. Introduction
1
UART is Universal Asynchronous Receiver Transmitter
used for serial communication over a computer or
peripheral device serial port. UART performs parallel-to- Fig.1 UART Transmission Protocol
serial conversion on data character received from the host
processor into serial data stream, and serial-to-parallel 2. The UART Module
conversion on serial data bits received from serial device
to the host processor. UARTs are commonly used in A 9-bit UART is modification to the normal UART which
conjunction with communication standards such as EIA, facilitate with ninth bit to be used either as parity identifier
RS-232, RS-422 or RS-485. The Universal Asynchronous or address/data differentiators. A 9 bit UART uses the
Receiver Transmitter (UART) is a popular and widely- ninth bit of character to differentiate between an address or
used device for data communication in the field of a data. Thus the 9 bit UART module is able to distinguish
telecommunication. It has many advantages such as simple between an address byte and data character resulting in
resources, reliable performance, strong anti-jamming saving a lot of processing time taken by slave devices.
capability, easy to operate and realize and so on. This Since in transmission the slave devices will search for
paper uses VHDL to implement the UART core functions every character transmitted for address byte and try to
and integrate them into a FPGA chip to achieve compact, match with its unique address.
stable and reliable data transmission The design of 9 bit UART proposed in this paper
A UART has standard transmission protocol which configures the ninth bit such that it is set to logic ‘1’ to
consists of a start bit ‘0’, 5-8 bits data, optional parity bit indicate an address character and set to logic ‘0’ to
and stop bit ‘1’. Fig. 1 shows the data frame format of a indicate the data character. Thus in a transmission,
UART. While in idle state, serial data line will be in logic processor will search for a parity bit and if it is found to be
‘1’ state. A start bit ‘0’ at the beginning of the data frame at logic ‘1’ then it will try to match the address with its
will cause a falling edge on the serial data line. This marks own unique address. If address matches, it receives the
the detection of a data character. The idea of start bit and data bytes followed by an address. If address matching
stop bit in UART is to achieve data synchronization. An failed, processor will ignore the following data bytes. Thus
optional parity bit can be in odd parity or even parity. Odd the proposed design helps in reducing the processing time
parity means that sum of all bits gives an odd number, required in searching for address of a particular slave
while even parity means sum of all bits gives an even device.
number. The serial data frame is shifted out with the least
significant bit (LSB) first. 3. Design of UART Submodules

The 9-bit UART module proposed in this paper consist of

*Corresponding author: Ashwini D. Dhanadravye

1889 | International Journal of Current Engineering and Technology, Vol.4, No.3 (June 2014)
Ashwini D. Dhanadravye FPGA Implementation of 9 bit Universal Asynchronous Receiver Transmitter

basic sub modules of UART which are receiver, It detects the start bit, when there is transition from logic 1
transmitter, and baud rate generator. Therefore, the to 0 on the serial data line. UART receiver module will
implementation of the UART communication module is receive data with parity bit followed by start bit.
actually the realization of the three sub-modules. Fig. 2 Depending upon the status of ninth bit, receiver module
below shows the complete block diagram of the 9 bit can differentiate whether the incoming data is data
UART. The baud rate generator is actually a frequency character or address byte. This proposed design used the
divider that can be calculated according to system clock finite state machine to implement the receiver module.
frequency and the desired baud rate. The function of baud This paper used finite state machine to implement
rate generator is to produce a local clock signal which is receiver module. The operation of receiver completes
much higher than the baud rate to control the UART using five states shown as below.
receive and transmit. The receiver performs serial-to- R_IDLE: When the UART receiver is reset, the
parallel conversion on the asynchronous data frame receiver state machine will be in this state. In this state,
received from the serial data input. The transmitter module state machine will wait for the start bit detection on the
converts the bytes into serial bits according to the basic serial input line. Start bit will be detected when RX pin
frame format received from the CPU. will transit from logic 1 to 0.
R_START: In this state, start bit will be detected as
soon as RX pin goes to logic 0 and will wait for 16 times
of baud rate clock before going to next state.
R_DATA: For asynchronous serial signal, most ideal
time for sampling is at the middle point of the bit. Hence
the task of this state is to read the middle point of each bit
so as to minimize the total error in the incoming data
detection. Each bit is then stored into an internal register
reg[7:0] to form a complete 8 bit data.
R_PARITY: In this state, state machine will sample
the ninth bit and determine whether the incoming data is
address character or data byte or even or odd parity
Fig.2 UART Module depending upon user requirement.
R_STOP: In this state, state machine will detect the
3.1 Baud Rate Generator stop bit with rxdata<=’1’, it means complete data has been
received by the receiver and waiting for the next frame to
The 9 bit UART module can be operate at any defined come.
clock frequency and at the same time follows desired baud
rate. The baud rate generator calculates the divide factor 3.3 Transmitter
with the help of system clock frequency and desired baud
rate. Thus the frequency clock produced by baud rate The function of the transmitter module is to convert the
generator is not the baud rate but 16 times of baud rate sending 8 bit parallel data into serial bits with the addition
clock. The purpose is to precisely sample the of start bit, stop bit and parity bit of ‘1’ for address
asynchronous serial data at the receiver because it is character, ‘0’ for data byte or shows even or odd parity
difficult to detect where to sample the input data. The status depending upon user requirement. In case ninth bit
calculation to get the divide factor is shown below. configured as address/data differentiator, address can be
broadcast address or unique address for specific slave
device. Once address has been successfully transferred,
UART transmit module will transmit the data bytes to the
addressed device.
3.2 Receiver

Receiver module receives the serial data through RX input

pin.

Fig.3 UART Receiver State Machine Fig.4 UART Transmitter State Machine

1890 | International Journal of Current Engineering and Technology, Vol.4, No.3 (June 2014)
Ashwini D. Dhanadravye FPGA Implementation of 9 bit Universal Asynchronous Receiver Transmitter

Transmitter module also implemented using internal finite

state machine to transmit the parallel bytes into serial bits.
TXRD and TX pins are the output signal of transmitter
module shown in the figure below. Similar to receiver,
transmitter completes its operation through five states
which are T_IDLE, T_START, T_DATA, T_PARITY,
T_STOP as shown in fig. 4.
Fig.6 Receiver Simulation Waveform
T_IDLE: Transmitter module will be in this state,
when UART is being reset. In this state, transmitter will
4.3 Transmitter Simulation
wait for transition of txrd signal from ‘1’ to ‘0’ indicates
that data is ready to transmit.
During transmitter simulation, the sending clock frequency
generated by the baud rate generator is set to 153600 Hz,
T_START: In this state, transmitter will add start bit on
and UART transmitting baud rate is set to 9600bps. Fig. 7
the serial line and will wait for 16 times of baud rate clock
shows the transmitter module simulation diagram. The
before going to the next state.
simulation report shows that this module uses 116 logic
T_DATA: In this state, state machine will loads the elements（<1%, 3 pins <1%), total 84 register and meets
internal register tx[7:0] with data to be transmitted starting timing requirement.
from the least significant bit tx[0] to most significant bit
tx[7].
T_PARITY: Depending upon the 8 bit data, this state
will add the parity bit of ‘1’ for address character and ‘0’
for data byte or may show the parity status based on
design configuration
T_STOP: When the complete frame of data has been
successfully transmitted, then transmitter module will Fig.7 Transmitter Simulation Waveform
undergo this state and will send stop bit of logic ‘1’. If
txrd=0, it means transmitter is ready to transmit next data Conclusion
frame and will switch back to T_START state and repeat
all steps until it goes to same state again. If there is no In this paper, UART has been modified with ninth bit
more data to be transferred it will go to T_IDLE state. facilitate to identify address character or data byte
automatically thereby reducing lot of processing time
4. Simulation of Modules required in searching the destined device. The 9 bit UART
design is implemented using VHDL language and
The simulation software is Quartus II. And selected device simulated to check the functionality of each sub modules.
is Altera’s Cyclone II FPGA: EP2C35F672C6 Using Quartus II software, Altera’s cyclone II FPGA chip
EP2C35F672C6 to complete simulation and test. Thus
4.1 Baud Rate Generator Simulation design shows greater flexibility, stability and reliability.

During simulation, the system clock frequency is set to References

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1891 | International Journal of Current Engineering and Technology, Vol.4, No.3 (June 2014)