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EE313 - VHDL Part III: GENERIC Parameters

The document discusses generic parameters, ranges, and type conversions in VHDL. It explains that generic parameters allow a value to be assigned and used as a constant throughout the code. Using generics and ranges makes code easier to change by avoiding having to modify multiple instances of a value if it needs to change. The document provides an example of a 3-bit address decoder that could easily be changed to 32-bits by modifying just the generic parameter. It also discusses using type conversions when different types are needed for intermediate calculations versus output display.

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Pedro Henrique de Souza
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49 views6 pages

EE313 - VHDL Part III: GENERIC Parameters

The document discusses generic parameters, ranges, and type conversions in VHDL. It explains that generic parameters allow a value to be assigned and used as a constant throughout the code. Using generics and ranges makes code easier to change by avoiding having to modify multiple instances of a value if it needs to change. The document provides an example of a 3-bit address decoder that could easily be changed to 32-bits by modifying just the generic parameter. It also discusses using type conversions when different types are needed for intermediate calculations versus output display.

Uploaded by

Pedro Henrique de Souza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE313 - VHDL Part III

GENERIC Parameters
We can declare a generic parameter in our entity or architecture VHDL sections. Recall our mux entity from
last lecture:
ENTITY mux IS
PORT(
x0, x1, x2, x3 : IN BIT_VECTOR ( 7 DOWNTO 0 );
sel : IN BIT_VECTOR ( 1 DOWNTO 0 );
y : OUT BIT_VECTOR ( 7 DOWNTO 0 )
);
END mux;

An alternative way to represent this same entity would be as:

ENTITY mux IS
GENERIC ( N : INTEGER := 8 );
PORT(
x0, x1, x2, x3 : IN BIT_VECTOR ( N-1 DOWNTO 0 );
sel : IN BIT_VECTOR ( 1 DOWNTO 0 );
y : OUT BIT_VECTOR ( N-1 DOWNTO 0 )
);
END mux;

Note the line:


GENERIC ( N : INTEGER := 8 );
This line declares a parameter named N and assigns it the value of 8. Notice that for a generic parameter (which
serves as a constant) a value is assigned using the symbol := (this is different for a signal, for which a value is
assigned using the symbol <= ).

What does this code do? Anywhere in the VHDL code that defines the entity mux, if N is encountered, it will
be immediately replaced with 8.

So, the line above that says:


x0, x1, x2, x3 : IN BIT_VECTOR ( N-1 DOWNTO 0 );
is treated as:
x0, x1, x2, x3 : IN BIT_VECTOR ( 7 DOWNTO 0 );
Why would we want to do this? ..How does the use of a generic parameter improve our code?
If properly implemented and we need to change our multiplexer from an 8 bit to a 32-bit multiplexer, we only
need to change the generic parameter from 8 to 32.

1
RANGE/REVERSE_RANGE
Once we declare a variable, say a, with a range, we can refer to its range as a’RANGE . For example, if we had
the declaration
a ,b, x : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);

and later had a generate statement such as:


fun: FOR i IN 0 TO 7 GENERATE
x(i) <= a(i) NOR b(i) ;
END fun;
we could instead use the following for the generate statement:
fun: FOR i IN a’RANGE GENERATE
x(i) <= a(i) NOR b(i) ;
END fun;
Again, as with generic parameters, the idea is to make code easier to change.

2
GENERIC/RANGE Example
Design a 3 bit address decoder that has the following truth table shown below:
enable address word_line
_____________________________________________________________________________________________________________________

0 XXX 11111111
1 000 11111110
1 001 11111101
1 010 11111011
1 011 11110111
1 100 11101111
1 101 11011111
1 110 10111111
1 111 01111111

Now, suppose instead of a 3bit address decoder, a 32-bit address decoder was needed. What would need to
change in the code above? Since the GENERIC and RANGE functions were used, the only required change is
the line declaring the value of N. Specifically, the number 3 would be replaced with 32.

3
SIGNED/UNSIGNED Numbers
We can declare values to be SIGNED or UNSIGNED. SIGNED numbers use the normal two’s complement
notation. For SIGNED numbers, we must include the library ieee.numeric_std.all . Signed and
Example: The program below implements a multiplier. If the decimal value of a is 13 and the decimal value of
b is 2, what will be the value of y (as 8 bits) after this section of code executes?

(13)(2) = 26, so y will be 00011010

If the decimal value of a is 13 and the decimal value of b is 2, what will be the value of y (as 8 bits) after this
section of code executes?

4
Now a has the value of -3. So y will have the value of -6.
In eight bits, -6 is 11111010

5
Type Conversion
Suppose you are working with a team of warfighters on a big design project. Eventually, all of your pieces of
VHDL must all come together without any hitches. All teams must use two inputs labeled a and b, where a and
b are defined as:
a, b : IN STD_LOGIC_VECTOR( 3 DOWNTO 0 );
The head warfighter (CAPT Kirk) has asked you to design an entity and architecture for a multiplier, that will
return the product of a and b. It is necessary that the product appear as:
prod : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );

CAPT Kirk said that he tried to use the multiply symbol ( prod <= a * b ; ), but his program crashed
with the error message:
INCOMPATIBLE TYPES CODE 1298 MULTIPLY UNRESOLVED 1A CANNOT MULTIPLY BIT
VECTORS SQUAWK SQWUAWK CODE 42 NITWIT ALERT
What do you do?
Convert the bit vectors to signed numbers, do the multiplication, and then convert back.
To convert from one type to another, we use the syntax:
newtype( identifier )
So, for example, to convert a to a signed number, we could use SIGNED( a ).

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