Introduction to

CMOS VLSI
Design

Logical Effort
 Outline
q  Introduction
q  Delay in a Logic Gate
q  Multistage Logic Networks
q  Choosing the Best Number of Stages
q  Example
q  Summary

Logical Effort CMOS VLSI Design Slide 2

 Introduction
q  Chip designers face a bewildering array of choices
–  What is the best circuit topology for a function?
–  How many stages of logic give least delay?
???
–  How wide should the transistors be?

q  Logical effort is a method to make these decisions

–  Uses a simple model of delay
–  Allows back-of-the-envelope calculations
–  Helps make rapid comparisons between alternatives
–  Emphasizes remarkable symmetries

Logical Effort CMOS VLSI Design Slide 3

 Example
q  Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]
32 bits

q  Decoder specifications:

4:16 Decoder

16 words
16
Register File
–  16 word register file
–  Each word is 32 bits wide
–  Each bit presents load of 3 unit-sized transistors
–  True and complementary address inputs A[3:0]
–  Each input may drive 10 unit-sized transistors
q  Ben needs to decide:
–  How many stages to use?
–  How large should each gate be?
–  How fast can decoder operate?
Logical Effort CMOS VLSI Design Slide 4
 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs τ =
3RC
d= ≈ 12 ps in 180 nm process
τ
40 ps in 0.6 µm process

Logical Effort CMOS VLSI Design Slide 5

 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs
d=
τ
q  Delay has two components
d= f +p

Logical Effort CMOS VLSI Design Slide 6

 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs
d=
τ
q  Delay has two components
d= f +p
q  Effort delay f = gh (a.k.a. stage effort)
–  Again has two components

Logical Effort CMOS VLSI Design Slide 7

 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs
d=
τ
q  Delay has two components
d= f +p
q  Effort delay f = gh (a.k.a. stage effort)
–  Again has two components
q  g: logical effort
–  Measures relative ability of gate to deliver current
–  g ≡ 1 for inverter
Logical Effort CMOS VLSI Design Slide 8
 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs
d=
τ
q  Delay has two components
d= f +p
q  Effort delay f = gh (a.k.a. stage effort)
–  Again has two components
q  h: electrical effort = Cout / Cin
–  Ratio of output to input capacitance
–  Sometimes called fanout
Logical Effort CMOS VLSI Design Slide 9
 Delay in a Logic Gate
q  Express delays in process-independent unit
d abs
d=
τ
q  Delay has two components
d= f +p
q  Parasitic delay p
–  Represents delay of gate driving no load
–  Set by internal parasitic capacitance

Logical Effort CMOS VLSI Design Slide 10

 Delay Plots
d =f+p 2-input
NAND Inverter
= gh + p 6
g=

NormalizedDelay:d
5 p=
d=
4 g=
p=
3 d=
2

0
0 1 2 3 4 5

ElectricalEffort:
h = Cout / Cin

Logical Effort CMOS VLSI Design Slide 11

 Delay Plots
d =f+p 2-input
NAND Inverter
= gh + p 6
g = 4/3

NormalizedDelay:d
5 p=2
d = (4/3)h + 2
q  What about 4 g=1
p=1
NOR2? 3 d = h +1
2 EffortDelay:f

1
Parasitic Delay: p
0
0 1 2 3 4 5

ElectricalEffort:
h = Cout / Cin

Logical Effort CMOS VLSI Design Slide 12

Computing Logical Effort
q  DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
q  Measure from delay vs. fanout plots
q  Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3

Logical Effort CMOS VLSI Design Slide 13

 Catalog of Gates
q  Logical effort of common gates

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

Logical Effort CMOS VLSI Design Slide 14

 Catalog of Gates
q  Parasitic delay of common gates
–  In multiples of pinv (≈1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8

Logical Effort CMOS VLSI Design Slide 15

Example: Ring Oscillator
q  Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=
Electrical Effort: h=
Parasitic Delay: p=
Stage Delay: d=
Frequency: fosc =

Logical Effort CMOS VLSI Design Slide 16

Example: Ring Oscillator
q  Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=1 31 stage ring oscillator in

0.6 µm process has
Electrical Effort: h=1 frequency of ~ 200 MHz
Parasitic Delay: p=1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N

Logical Effort CMOS VLSI Design Slide 17

 Example: FO4 Inverter
q  Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g=
Electrical Effort: h=
Parasitic Delay: p=
Stage Delay: d=

Logical Effort CMOS VLSI Design Slide 18

 Example: FO4 Inverter
q  Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g=1

Electrical Effort: h=4 The FO4 delay is about

Parasitic Delay: p=1 200 ps in 0.6 µm process

Stage Delay: d=5 60 ps in a 180 nm process

f/3 ns in an f µm process

Logical Effort CMOS VLSI Design Slide 19

Multistage Logic Networks
q  Logical effort generalizes to multistage networks
q  Path Logical Effort G= g ∏ i

q  Path Electrical Effort

Cout-path
H=
Cin-path
q  Path Effort F = ∏ fi = ∏ gi hi
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

Logical Effort CMOS VLSI Design Slide 20

Multistage Logic Networks
q  Logical effort generalizes to multistage networks
q  Path Logical Effort G= ∏g i

q  Path Electrical Effort

Cout − path
H=
Cin − path
q  Path Effort F = ∏ fi = ∏ gi hi
q  Can we write F = GH?

Logical Effort CMOS VLSI Design Slide 21

 Paths that Branch
q  No! Consider paths that branch:
15
G = 90
5
H =
GH = 15
90
h1 =
h2 =
F = GH?

Logical Effort CMOS VLSI Design Slide 22

 Paths that Branch
q  No! Consider paths that branch:
15
G =1 90
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH

Logical Effort CMOS VLSI Design Slide 23

 Branching Effort
q  Introduce branching effort
–  Accounts for branching between stages in path
Con path + Coff path
b=
Con path
Note:
B = ∏ bi
∏ h = BHi

q  Now we compute the path effort

–  F = GBH

Logical Effort CMOS VLSI Design Slide 24

 Multistage Delays
q  Path Effort Delay DF = ∑ f i

q  Path Parasitic Delay P = ∑ pi

q  Path Delay D = ∑ di = DF + P

Logical Effort CMOS VLSI Design Slide 25

 Designing Fast Circuits
D = ∑ di = DF + P
q  Delay is smallest when each stage bears same effort

fˆ = gi hi = F
1
N

q  Thus minimum delay of N stage path is

1
D = NF + P N

q  This is a key result of logical effort

–  Find fastest possible delay
–  Doesn’t require calculating gate sizes
Logical Effort CMOS VLSI Design Slide 26
 Gate Sizes
q  How wide should the gates be for least delay?

fˆ = gh = g CCoutin
gi Couti
⇒ Cini =
fˆ
q  Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
q  Check work by verifying input cap spec is met.

Logical Effort CMOS VLSI Design Slide 27

 Example: 3-stage path
q  Select gate sizes x and y for least delay from A to B

y
x
45
A 8
x
y B
45

Logical Effort CMOS VLSI Design Slide 28

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G=
Electrical Effort H=
Branching Effort B=
Path Effort F=
Best Stage Effort fˆ =
Parasitic Delay P=
Delay D=

Logical Effort CMOS VLSI Design Slide 29

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

Logical Effort CMOS VLSI Design Slide 30

 Example: 3-stage path
q  Work backward for sizes
y=
x=

y
x
45
A 8
x
y B
45

Logical Effort CMOS VLSI Design Slide 31

 Example: 3-stage path
q  Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3

Logical Effort CMOS VLSI Design Slide 32

 Best Number of Stages
q  How many stages should a path use?
–  Minimizing number of stages is not always fastest
q  Example: drive 64-bit datapath with unit inverter
InitialDriver 1 1 1 1

D =

DatapathLoad 64 64 64 64

N: 1 2 3 4
f:
D:

Logical Effort CMOS VLSI Design Slide 33

 Best Number of Stages
q  How many stages should a path use?
–  Minimizing number of stages is not always fastest
q  Example: drive 64-bit datapath with unit inverter
InitialDriver 1 1 1 1

8 4 2.8

D = NF1/N + P 16 8

= N(64)1/N + N
23

DatapathLoad 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

Logical Effort CMOS VLSI Design Slide 34

 Derivation
q  Consider adding inverters to end of path
–  How many give least delay? N - n1 ExtraInverters
Logic Block:
n1 n1Stages
1
D = NF + ∑ pi + ( N − n1 ) pinv
N Path Effort F

i =1
∂D 1 1 1
= − F N ln F N + F N + pinv = 0
∂N
1
q  Define best stage effort ρ=F N

pinv + ρ (1 − ln ρ ) = 0
Logical Effort CMOS VLSI Design Slide 35
 Best Stage Effort
q  pinv + ρ (1 − ln ρ ) = 0 has no closed-form solution

q  Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)

q  For pinv = 1, solve numerically for ρ = 3.59

Logical Effort CMOS VLSI Design Slide 36

 Sensitivity Analysis
q  How sensitive is delay to using exactly the best
number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15

1.0

(ρ=6) (ρ =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N

q  2.4 < ρ < 6 gives delay within 15% of optimal

–  We can be sloppy!
–  I like ρ = 4

Logical Effort CMOS VLSI Design Slide 37

 Example, Revisited
q  Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]
32 bits

q  Decoder specifications:

4:16 Decoder

16 words
16
Register File
–  16 word register file
–  Each word is 32 bits wide
–  Each bit presents load of 3 unit-sized transistors
–  True and complementary address inputs A[3:0]
–  Each input may drive 10 unit-sized transistors
q  Ben needs to decide:
–  How many stages to use?
–  How large should each gate be?
–  How fast can decoder operate?
Logical Effort CMOS VLSI Design Slide 38
 Number of Stages
q  Decoder effort is mainly electrical and branching
Electrical Effort: H=
Branching Effort: B=

q  If we neglect logical effort (assume G = 1)

Path Effort: F=

Number of Stages: N=

Logical Effort CMOS VLSI Design Slide 39

 Number of Stages
q  Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

q  If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8

Number of Stages: N = log4F = 3.1

q  Try a 3-stage design

Logical Effort CMOS VLSI Design Slide 40

 Gate Sizes & Delay
Logical Effort: G=
Path Effort: F=
Stage Effort: fˆ =
Path Delay: D=
Gate sizes: z= y=
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

y z word[0]

96 units of wordline capacitance

y z word[15]

Logical Effort CMOS VLSI Design Slide 41

 Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: fˆ = F 1/ 3 = 5.36
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

y z word[0]

96 units of wordline capacitance

y z word[15]

Logical Effort CMOS VLSI Design Slide 42

 Comparison
q  Compare many alternatives with a spreadsheet

Design N G P D
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

Logical Effort CMOS VLSI Design Slide 43

 Review of Definitions
Term Stage Path
number of stages 1 N
logical effort g G = ∏ gi
Cout-path
electrical effort h= Cout
Cin
H= Cin-path
Con-path +Coff-path
branching effort b= Con-path B = ∏ bi
effort f = gh F = GBH

effort delay f DF = ∑ fi

parasitic delay p P = ∑ pi
delay d= f +p D = ∑ d i = DF + P

Logical Effort CMOS VLSI Design Slide 44

 Method of Logical Effort
1)  Compute path effort F = GBH
2)  Estimate best number of stages N = log4 F
3)  Sketch path with N stages
1
4)  Estimate least delay D = NF + PN

5)  Determine best stage effort ˆf = F N1

gi Couti
6)  Find gate sizes Cini =
fˆ

Logical Effort CMOS VLSI Design Slide 45

 Limits of Logical Effort
q  Chicken and egg problem
–  Need path to compute G
–  But don’t know number of stages without G
q  Simplistic delay model
–  Neglects input rise time effects
q  Interconnect
–  Iteration required in designs with wire
q  Maximum speed only
–  Not minimum area/power for constrained delay

Logical Effort CMOS VLSI Design Slide 46

 Summary
q  Logical effort is useful for thinking of delay in circuits
–  Numeric logical effort characterizes gates
–  NANDs are faster than NORs in CMOS
–  Paths are fastest when effort delays are ~4
–  Path delay is weakly sensitive to stages, sizes
–  But using fewer stages doesn’t mean faster
paths
–  Delay of path is about log4F FO4 inverter delays
–  Inverters and NAND2 best for driving large caps
q  Provides language for discussing fast circuits
–  But requires practice to master
Logical Effort CMOS VLSI Design Slide 47