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VERILOG CODE - Single Page PDF

This Verilog code defines a JK master-slave flip-flop using two JK flip-flops connected back-to-back. The master flip-flop uses the JK and clock inputs and its output is connected to the slave flip-flop. The slave flip-flop uses the complement of the clock and the output of the master flip-flop to produce the final output. A test bench is also provided that applies different combinations of J and K inputs over time to test the functionality of the JK master-slave flip-flop.

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Anuj Patel
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0% found this document useful (0 votes)
229 views1 page

VERILOG CODE - Single Page PDF

This Verilog code defines a JK master-slave flip-flop using two JK flip-flops connected back-to-back. The master flip-flop uses the JK and clock inputs and its output is connected to the slave flip-flop. The slave flip-flop uses the complement of the clock and the output of the master flip-flop to produce the final output. A test bench is also provided that applies different combinations of J and K inputs over time to test the functionality of the JK master-slave flip-flop.

Uploaded by

Anuj Patel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VERILOG CODE:

JK Master Slave flip-flop


module jkff(input j,k,clk,output reg q);
always@(clk)
begin
case({j,k})
0:q<=q;
1:q<=0;
2:q<=1;
3:q<=~q;
endcase
end
endmodule
module jkms(input j,k,clk,output q);
wire t1;
jkff master(.j(j),.k(k),.clk(clk),.q(t1));
jkff slave(.j(t1),.k(~t1),.clk(~clk),.q(q));
endmodule

TEST BENCH:
JK Master Slave flip-flop
module bench;
reg j;
reg k;
reg clk;
wire q;
jkms uut (
.j(j),
.k(k),
.clk(clk),
.q(q)
);
initial begin
j = 0;k = 0; #100;
j = 0;k = 1; #100;
j = 1;k = 0; #100;
j = 1;k = 1; #100;
j = 1;k = 1; #100;

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