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Assignment CompArch

The document discusses associative memory, including its architecture, advancement, characteristics, and references. Associative or content addressable memories are crucial for high performance computing and applications requiring intensive data management or cognitive abilities. The architecture can be based on exact match or neural network models, and associative memories possess capabilities in retrieving patterns from noisy input data.

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24 views7 pages

Assignment CompArch

The document discusses associative memory, including its architecture, advancement, characteristics, and references. Associative or content addressable memories are crucial for high performance computing and applications requiring intensive data management or cognitive abilities. The architecture can be based on exact match or neural network models, and associative memories possess capabilities in retrieving patterns from noisy input data.

Uploaded by

Afzaal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ASSIGNMENT: 01

APRIL 5, 2018

COMPUTER
ARCHITECTURE

ASSOCIATIVE MEMORY

PRESENTED BY: MD AFZAAL


B.TECH (ELECTRICAL-VI)
ROLL: 15BEE0047
CONTENTS
 INTRODUCTION

 ARCHITECTURE & ADVANCEMENT

 CHARACTERISTIC

 REFERENCES

4/5/2018 CONTENTS 1
INTRODUCTION
The terms "associa ve" and "content addressable" have been
synonymously used to iden fy a class of memories in which data are
accessed on basis of content rather than data-loca on address.

Associa ve or content addressable memories (CAM) are crucial in the


implementa on of high performance compu ng architectures for
applica ons that require intensive data management or are cogni ve in
nature.

ARCHITECTURE & ADVANCEMENT


The basic architecture of associa ve memories can be based on either
the exact match or neural network models.

The primi ve opera on of the "exact match CAM" involves finding in


parallel all stored words that match an input. All words are compared
simultaneously, results are reached with no interac on between stored
words.

A "neural inspired CAM" opera on requires merely all the informa on in


the memory to interact and collec vely evolve to a decision (e.g. best
match).

4/5/2018 CONTENTS 2
Neural CAMs possess outstanding capabili es in retrieving pa erns
from noisy input data and give the best match in one memory cycle.
While an exact match CAM requires several memory cycles to achieve
the best match result.

This classifica on clearly iden fies the salient differences among exact
match associa ve systems at two levels of dis nc on. At the first level,
the basic memory architecture can be either hardware implemented in a
fully parallel fashion or emulated by RAM in a bit/word serial structure.
The second level of dis nc on further classifies associa ve architecture
according to their degree of func onality and data processing capability.
Even though the classifica on at this level is heavily dependent on the
applica on domain, the dis nc on is solely made on the basis of the
fundamental processing capability of the architecture.

4/5/2018 CONTENTS 3
FULLY PARALLEL ASSOCIATIVE MEMORY
Each bit loca on consists of a storage cell and a two-input Exclusive-OR.
The Exclusive-OR inputs are the stored bit and the corresponding bit of
the input word. Each row consists of a b-bit word and one match line.
The match line is connected to ground (logic zero) through a switch at
each bit loca on in the row. I f any switch in the row is turned on, then
the match line for that row is at logic zero. The switch at each bit loca on
is controlled by the output of the Exclusive-OR. Thus whenever any bit
in a word mismatches the corresponding input bit, the Exclusive-OR
output would be high (logic one). Consequently the switch at that bit
loca on turns on and the match line for that word is at logic zero. Thus
all the words that do not match the input word will have their match
line at logic zero.

The mask register provides the capability of having only selected bits
to par cipate in the match opera on.

4/5/2018 CONTENTS 4
Only the words that exactly match the input will have their match line
stay at logic high, otherwise the match line discharge to zero. This
informa on is sensed by the sense amplifiers and stored in the word
response registers.

EMULATION BY RAM
Two prac cal associa ve memory configura ons can be emulated using
a RAM which are bit-serial word-parallel (bit serial) and word-serial bit-
parallel (word serial) the bit cell area. Instead of having a comparison
logic for each bit as in the fully parallel case, a group of bits share a
common comparison logic. Bit serial associa ve memory includes
comparison logic for each bit column (bit slice) and thus each memory
column is processed at a me. In the word serial case, each memory
row or word has comparison logic which allows each word to be
processed at a me. A varia on of these two associa ve memory
configura ons is the block-parallel configura on. This entails dividing
the memory into blocks of words while bit/word serial processing is
performed within each block. For instance in a word-serial block-parallel
configura on, all blocks are processed concurrently while each block is
processed in a word-serial bit-parallel fashion.

4/5/2018 CONTENTS 5
CHARACTERISTICS
 Associa ve Memory are Highly Distributed in Nature.
 It is a content addressable memory.
 Searching is Very Fast.

REFERENCES
 Shankar, S'A Hierarchical Associa ve Memory Architecture for
Logic Programm1l1g Unifica on." Proc. 5th Interna onal
Conference and Symposium on Logic Programming, (Aug. 1988),
1428-1447
 Dou, C and Wu, S.M. "An Efficient Pa ern Match Architecture for
Produc on Systems Using Content addressable Memory." Proc.
1991 IEEE Interna onal Conference on Computer Design. VLSI in
Computer and Processors, Cambridge, MA, (Oct. 14-16, 1991),
374-378.

4/5/2018 CONTENTS 6

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