The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON)

Nov. 5-8, 2007, Taipei, Taiwan

Modeling and Control of Three-Phase Active

front-end Converters
Chung-Chuan Hou*,**, Po-Tai Cheng*, Subhashish Bhattacharya***, and Jarsun Lin****
* National
Tsing Hua University, Hsinchu, TAIWAN
** Chung Hua University, Hsinchu, TAIWAN
***
North Carolina State University, NC, USA
****
Rhymebus Corporation, Taichung, TAIWAN

Abstract- Insulated Gate Bipolar Transistor based active This study consists of the following subsections. Section
front-end converters are widely utilized by industries thanks to II presents the dynamic model and controller of the AFE
the advantages of bi-directional power flow, unity power factor, converter system in the synchronous reference frame. The
low harmonic distortion of the line current, and smaller filter
size. In this paper, the model and control of the active front- controller is designed with decoupling terms and considers the
end converter system are presented and the operation principles estimated value of line inductance. Section III describes the
are analyzed. Detailed discussions on controller designs aiming DC bus voltage control, the AFE converter maintains the DC
at enhancing the disturbance rejection capability and robustness bus voltage at the voltage command level by absorbing from
are presented, and the performance is validated by experimental or regenerating energy to the AC lines. The AFE converter
results.
system provides bi-directional power flow, unity power factor,
low total harmonic distortion of line current. The operation
princples of the AFE converter system are analyzed according
I. INTRODUCTION to the dynamic model. In section IV, DC bus voltage distur-
bance rejection is discussed. In Section V, experimental results
In variable speed drives, diode rectifiers or thyristor recti- are used to validate the performance of AFE converter system.
fiers are usually used as the AC/DC front-end. The advantages Finally, a summary of the paper is presented.
of the conventional rectifier include low cost, simplicity and
high reliability. However, these rectifiers draw significant
harmonic current from the utility grid and lack the regeneration II. DYNAMIC MODEL FOR THE ACTIVE FRONT-END
capability. Industry standards, such as IEEE-519 and IEC- CONVERTER
61000-3-2, are adopted to address these issues. Shunt active A. Converter modeling
filter and the series active filter have been proposed [1,2,3].
However, these active filters only suppress the harmonic Figure 2 shows the equivalent circuit of the AFE converter
current, the regeneration capability is still in lack. Recently, system where the switches are replaced by dependent voltage
Insulated Gate Bipolar Transistor (IGBT)-based active front- and current sources representing the switching behavior. The
end (AFE) converter systems, as shown in the Fig. 1, have
become more popular. Various model of the active front-
end converters have been presented in previous literature
[4,5,6,7,8]. This paper presents a synchronous reference frame
based model, and discusses in detail how the control design
affect the disturbance rejection capability and robustness.
(a) Equivalent circuit in an abc reference frame

AFE (b) Equivalent circuit in a synchronous reference frame

Fig. 1. The AFE converter system. Fig. 2. Equivalent circuit of the AFE converter system
1-4244-0783-4/07/$20.00 C 2007 IEEE 1449
 (a) Controller and AFE converter (b) Control block diagram
Fig. 3. The modeling and control of the AFE converter in the synchronous reference frame.

quantities Vsa, Vsb, and Vs, represent the phase voltages in the B. Controller design
abc reference frame. The quantities isa, isb, and 'sc represent
the line currents in the abc reference frame. The Ma, Mb, and For feedback control of DC bus voltage, a proportional-
MC are defined as the duty cycle of the upper switches for integral regulator (GpI = Kp + Kri/s) is utilized. By
phase a, b, and c. The DC bus capacitance is C. The following multiplying the regulator output and the phase voltages Vqe
assumptions are made in developing the model for the AFE and Vde in the synchronous reference frame, the current
converter system: 1) line inductance LS = Lsa = Lsb = commands iqec and idec can exchange power with the utility
LSC; 2) load of the DC side is represented as a dependent grid via a unity power factor. The load compensation gain
current source. Figure 2(a) is the equivalent circuit of the AFE Kload is utilized to suppress the disturbance of load. The Mq
converter in an abc reference frame. The equivalent equations and Md are the duty cycle in the synchronous reference frame
of the AFE converter are given in (1). as designed with decoupling terms (-WeLstde weLsiqe) in
equation (3) as follow:
VSa LSa djdt+MVd
+ MaVdcVnN
disb + Vqe -JeLsde (iqec iqe)Ki
Vsb Lsb dt
d MbVdc VnN Mq
-

Vdc
VSC scLSCLdisc
dt
+ McVdc VnN Vde + WeLsiqe (-dec -ide)Ki
Md
Vdc
(3)
+ Mb + Mc)Vdc
VnN 3 (Ma
Maisa + Mbisb + MCiSC = C dt + 19load (1) where LS is the estimated value of line inductance L. The Ki
is the current control gain for current loop errors (iqec -iqe)
The equivalent circuit of the AFE converter is transformed and (idec -ide). As indicated in equation (3), the controller
into the synchronous reference frame as shown in Fig. 2(b). of the AFE converter in the synchronous reference frame is
Therefore, equation (1) is transformed into the synchronous shown in the left side of Fig. 3(a).
reference frame as in equation (2). Applying equation (3) to equation (2), the state equation for
the synchronous reference frame model of the AFE converter
d system is obtained as in equation (4).
Ls (Vqe -MqVdc -eLsilde)
dtjjqe

[
dt I

dt-jjdee (Vde -MdVdc + weLsiqe) d [ 1qe

u"We(L - 1) 0
iqe
Ls
L

d
7Vdc
13
C[2 Mqiqe
+
+ Md'de) 'load] (2)
dt
tde
Vdc ]
We(1
VIq
2 C
_ s- ) Ki
MId
2C
0
F tde
Vdc
3 3

tqec 1 0
The frequency Woe is synchronized to the utility by a software
phase lock loop. The quantities Vqe and Vde represent the
+
L 07O
Ki

fO
0
F

C
1
tdec
tload J
(4) 1F
phase voltages in the synchronous reference frame. The quan-
tities iqe and ide represent the line currents in the synchronous
reference frame. As indicated in equation (2), the model of the The quantities iqe, ide, and Vdc represent the state variable in
AFE converter in the synchronous reference frame is shown the state equation. Solving the state equation (4), the transfer
in the right side of Fig. 3(a). function can be obtained as in equation (5).
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 3MqKi (S + Ki) + 3M2KC (1 -L)ei f70 Od)
n iki

Vdc (S)
sL,[(s + Ki)2 + (1 -)2w2]
3MdKi (S + Ki) 3M1K'Ki L)

sLs[(s + Ki)2 + ( 21
L)2 ds2] (a K1 X X cags fro 15 to 37, C
t;u
940 1I

(SC) load(S) bl-as1-l Pi me-n(,C1

sle4XS97 V'
P2: -.l(2)
371 ;5 V

sKi(s + e)
(a) Ki =LT il,ad changes from 1. 85A to 3.7A, C =940,uF.
Ki )2 + (;_Ls)2g,2]
sLs[(s +sKj(1 y)We, ()
.|>d

sLs [(S + LKi) 2 + ( -LI 2be2]

ide(s) = sK1(1 - L )WeL *iqec(S)

sLs [(S + LKi) 2 ++ ( -LI

+dssK(s ) 2ge2] tqeC(S) (5) s.' '''> .'.. ---------
,',

P2: -,a
.....,...t

.,)V:
_
................8 Tq
C2

tOn

In order to simplify the controller of the AFE converter

system, the estimate of line inductance is very important.

Assuming the estimated value L5 approximates to the line

(b) Ki =LT; iload changes from 1.85A to 3.7A, C = 940,uF.
inductance Ls, equation (5) can be reduced as in equation
(6). Fig. 4. The DC bus voltage under load variation; with different pole wi
(X-axis: 100,usldiv).
mq
Vdc(S) = (SC) (1 + --=) iqec(S) sC liload(s) the controller [4]. If the Ki = Lp, then i qe follows the current
3
md
command iqec in 8T when the iload is changed as shown in
+ ( C)-(1+
) * idec(S) Fig. 4(b). As indicated by equation (6), the pole wi is related
to current regulator for the current control.
Vdc(S) 2Mq
- (SC) (1 + S
Gq(s) iqec(s)
_ I III. DC Bus VOLTAGE CONTROL
Giq() iqe(s) i ) Figure 3(b) shows the control block diagram of AFE
iqec(s) I1+ s
converter system in synchronous reference frame. There are
G (Sde()
Gid(s)
tdec(s) (6) two major control loops in the system, one is the current
id 1+
control loop and the other is the DC bus voltage control loop.
The proportional-integral regulator (Gpl = KP + Kvi/s) is
where utilized for the compensation of the DC bus voltage The
wo(= Ki/Ls) is the pole related to the current control loc ; predicted current control gain is designed as Ki(= LT) or
Gid(s) is the transfer function between ide and idec;
Giq(s) is the transfer function between iqe and iqec; Ki (= 2L-s). The function of the current control loop is to
maintain the line currents tracking the current commands. As
Gq(s) is the transfer function between Vdc and iqec. indicated in equation (6), the DC bus voltage is affected by
load disturbance. Therefore, the load compensation gain Kload
The transfer functions have two poles as given in equaltion
is utilized to suppress the disturbance of load.
(6). The pole on the origin is related to the capacitor vailue The d-axis command
idec current is controlled to be of

for the DC bus voltage control, and the pole wo is relatecI to value for unity power factor. The pole of current regulator
the current regulator for the current control. The control bl ock wi is ten times larger than KVi/Kvp and 1.5MqKvp/C.
diagram of AFE converter system in synchronous refere nce Therefore, the close loop transfer function of the DC bus
frame is shown in Fig. 3(b). The DC bus voltage is affec,ted voltage controller is given in equation (7).
by the load and the current commands of q-axis and d-ax is.
Figure 4 shows the DC bus voltage under load varialtion Gpi PI)2(5Mq sKv,p+K, i 1. 5Mq
c
Vdc
with different pole wo, and the test parameters are giveri in wi
(7)
Appendix A. The current control gain is designed as Ki = T L, Vd c I + L"z
+ GPI82 ') (I + Wi)(I + )(I + vi )
w

then iqe follows the current command iqec in 5T when the ilload
is changed as shown in Fig. 4(a). T is the sampling time of where gop and wo, are defined as
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 ~~Ovp + /
(1 + 1 1.5Mq K2 1.5MqK),p
q40 K,j 20
-, (1 1 _ 4C Kvi 1.5MqKvp
AUvi V > 1.5Mq K2 2C
underdamped: Kvi/K2 > 1.5Mq/4C
critically damped: Kvi/K 2 = 1.5Mq/4C
overdamped: Kvi/K 2 < 1.5Mq/4C
The woi and gop are affected by DC bus voltage regulator
GPl and capacitance C. (a) AFE operates in the rectifier mode; iload 1.85A.
When the DC load consumes power, the current iqe draws
real power from the utility. The line current isa will be in phase
with the phase voltage Vsa after the AFE converter is on as
shown in Fig. 5(a). The power factor is r-1.0 and the total
harmonic distortion (THD) of isa is 3.6% at 1.9Arms. The
AFE converter operates as a unity power factor rectifier when
the DC load consumes power. When the DC load regenerates
power, the current iqe injects real power to the utility. The line
current isa will be opposite phase with the phase voltage Vsa (b) AFE operates in the regeneration mode
after the AFE converter is on as shown in Fig. 5(b). The THD
of isa is 2.9% at 2.53Arms . The AFE converter operates as a Fig. 5. Bidirectional power flow of the AFE converter (X-axis: 5ins/div).
voltage source inverter when the DC load regenerates power.
The AFE converter provides bi-directional power flow, unity
power factor, low THD of line current, and constant DC bus
voltage.
IV. DISCUSSIONS
The performance of AFE converter system is affected by I1vi
II rad/sec
load disturbance. Therefore, the DC bus voltage disturbance 374 A/V

20krad/sec
rejection of the AFE converter system is defined as the 150 rad sec 26.5 A/V

magnitude of iload needed to affect a unit deviation in the

DC bus voltage Vdc. The transfer function iload(s)lVdcQs) is
given in equation (8) according to Fig. 3(b). Frequency (rad/sec)

(a) GPI = 0. I + 1/s, Kj,ad = vX2Vd,/381, C = 940,u-F

1I+i + G Pi -l.5Mq
w
S2( 68 )
lload (S)
1. 5Mq
Vdc (S) sl (I + s ) + Kload . 2( C)l
(1 + 0i )(1 + vp )(1 + oi )
(8) stKv p
1. 5Mq
1 (1 + gi ) +
i
Figure 6(a) is the DC bus voltage disturbance rejection 683dsec
54.0 A/V
120 krad/sec
53.3 A/V

tload(S)lVdc(S) with regulator (GpI = 0.1 + 1/s). The DC

bus voltage disturbance rejection is increased respectively by
integral gain (Kvi T) in lower frequency domain (< ovi), by Frequency (rad/sec)
proportional gain (KVP T) in the frequency domain (< ovp). (b) GpI = 0.1 + 1/s, Kload = \v2dc/381, C 1880 ,uF
As shown in Fig. 6(b), when DC bus capacitance C increases
from 940,uF to 1880,uF, the DC bus voltage disturbance
rejection is increased in higher frequency domain (> ovp).
The pole ovp is affected by C and the pole ovi is lightly
affected by C. Figure 6(c) is the DC bus voltage disturbance
K l oad-
rejection with different load compensation gain Kload. When 381
the AFE converter operates with regulator (GpI = 0.1 + 1/s,
Kload = 0.0), the steady-state error of DC bus voltage
is almost zero. However, the performance of the transient- Kload 0.0

state for DC bus voltage is not very well without the load
compensation.
The AFE converter system exhibits a high DC bus voltage (c) GpI = 0.1 + 1 /s with different Kload, C 940 ,uF
disturbance rejection (> 101) in all of the frequency domains
(GpI = 0.1 + 1/s, Kload = 2vd,/381). Fig. 6. DC bus voltage disturbance rejection iload(s)1vd,(s) ( Y-axis )

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 V. EXPERIMENTAL RESULTS
The experimental parameters of the AFE converter system
are given as Appendix A. Figure 7 shows the DC bus voltage
under load disturbance with regulator GPl = 0.1 + 1/s. The
poles wo, wovp, and wov are 20krad/sec., 150rad/sec., and
llrad/sec. respectively. As shown in Fig. 7(a), when tload
changes from loadl (=3.7A) to load2 (=1.85A) without load
disturbance compensation, the voltage of DC bus oscillates
for 0.38 second and during which the voltage is temporarily
increased by 16.OV. As shown in Fig. 7(b), when iload changes
from loadl to load2 with load disturbance compensation,
the voltage of DC bus oscillates for 0.3 second and during
which the voltage is temporarily increased by 4.OV. The
load compensation gain Kload is utilized to suppress the
disturbance of load.
Figure 8 shows the DC bus voltage under load distur-
bance with regulator GPI = 0.01 + 1/s (Kvp {). The
underdamped poles wo, wovp, and wov are 20krad/sec. and
7.9 ± 39.2irad/sec. respectively. As shown in Fig. 8(a),
when iload changes from loadl (=3.7A) to load2 (=1.85A)
without load disturbance compensation, the voltage of DC
bus oscillates for 0.45 second and during which the voltage
&7

Me MM li
X~ ~ .VtF .
1? . .

Zt kl

(a) without load disturbance compensation (X-axis: 50ms/div)

_

NNEll

is temporarily increased by 26.OV. As shown in Fig. 8(b), A:~~~

~ ~ ~ ~

when iload changes from loadl to load2 with load disturbance

compensation, the voltage of DC bus oscillates for 0.4 second (b) with load disturbance compensation (X-axis: 50ms/div)
and during which the voltage is temporarily increased by 6.OV.
The decreased Kvp of regulator GP, causes heavily DC bus Fig. 7. The DC bus voltage under load disturbance; iload changes from
loadl (=3.7A) to load2 (=1.85A), GpI = 0.1 + 1ls, C = 940 uF.
voltage oscillation during load disturbance and reduces the
performance of the AFE converter.
Figure 9 shows the DC bus voltage under load disturbance
with regulator GPl = 0.1 + 0.1/s (Kvi {). The overdamped
poles wo, wovp, and wov are 20kradlsec., 160radlsec., and
1.Orad/sec. respectively. As shown in Fig. 9(a), when tload
changes from loadl (=3.7A) to load2 (=1.85A) without load I
disturbance compensation, the voltage of DC bus oscillates i :,
for 3.2 second and during which the voltage is temporarily
increased by 19.OV. As shown in Fig. 9(b), when iload changes f~9
from loadl to load2 with load disturbance compensation, the
voltage of DC bus oscillates for 2.0 second and during which
the voltage is temporarily increased by 5.OV. When the pole
wvi is near the origin, the settling time of DC bus voltage is (a) without load disturbance compensation (X-axis: 50ms/div)
increased during load disturbance.
Figure 10 shows the DC bus voltage under load disturbance
with regulator (Gpl = 0.1 + 1/s), when DC bus capacitance
C increases from 940 ,F to 1880 uF. The poles wo, w1vp,
and wov are 20krad/sec., 68.3rad/sec., and 11.7rad/sec.
respectively. The pole wvp is affected by capacitance C. As
t

shown in Fig. 10(a), when iload changes from loadl to load2

without load disturbance compensation, the voltage of DC
bus oscillates for 0.3 second and during which the voltage
is temporarily increased by 15.OV. As shown in Fig. 10(b),
when iload changes from loadl to load2 with load disturbance
compensation, the voltage of DC bus oscillates for 0.25 second
and during which the voltage is temporarily increased by 3.5V. (b) with load disturbance compensation (X-axis: 50ms/div)
The regulator GPl = 0.1 + 1/s is utilized to suppress the
variation of DC bus capacitance C. Therefore, the amplitude Fig. 8. The DC bus voltage under load disturbance; il,ad changes from

of DC bus voltage oscillation is lightly affected by varied C. loadl (=3.7A) to load2 (=1.85A), Gp = 0.01 + 1ls, C 940 uF.

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 VI. CONCLUSIONS
In this paper, the dynamic model of the AFE converter
system is presented in the synchronous reference frame. The
DC bus voltage control and the AC current control of the AFE
converter are integrated in this model. The performance of
AFE converter system is affected by the load disturbance. This
paper shows that the proportional gain and the integral gain of
the DC bus control affect the disturbance rejection in different
frequency range, and the resulting dynamic response also
reflect this distinction. The closed-loop control also exhibits
very good robustness against DC capacitor variation, the most
(a) without load disturbance compensation (X-axis: 200ms/div) significant parameter variation that could occur in this system.
The pole locations and the disturbance rejection characteristics
are slightly altered even if the DC capacitor varies by 100%.
The AFE converter system exhibits a high DC bus voltage
disturbance rejection across wide frequency range with the
load compensation gain Kload. The experimental results have
validated the AFE converter model presented in this paper.

ACKNOWLEDGMENT
This research is co-sponsored by Rhymebus Corporation,
Taiwan and the National Science Council, Taiwan under grant
NSC-94-2622-E-007-014-CC3. The authors would like to
thank Mr. Cheng-Ching Chang and several of their colleagues
(b) with load disturbance compensation (X-axis: 200ms/div) at Rhymebus for the support in the test facility.

Fig. 9. The DC bus voltage under load disturbance; iload changes from APPENDIX A
loadl (=3.7A) to load2 (=1.85A), GpI 0.1 + 0.1 s, C 940,uF. The simulation and experimental parameters of the AFE
converter system are given as follows:
. Utility: line-to-line 220 Vrms, 60Hz, the line inductance L, is
approximately 2.0 mH.
* AFE converter: switching frequency f5, = 1O.OkHz, sampling
time T= 2f
* DC side: Vd*C = 370V, C= 940 ,uF, loadl = 3.7A or load2
1.85A.
* Controller: current control gain Ki =L (wi = 20000), DC
11 I.10
1, 1 q_ 1_ 17 1g 1 bus voltage compensator Gpi = 0.1 + 1/s, load compensation
gain Kload= \/21d
381

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