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    Power Planning

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    neha
    Power planning involves distributing power uniformly to satisfy constraints. It helps reduce IR drop issues by increasing wire widths, adding power straps, and spreading cells. Factors like strap width and numbers, current densities, and metal layers used are considered. Avago uses a mesh-like grid structure with power stripes in most metal layers. Comparisons of 16nm and 28nm chips show the 16nm chip uses higher metal layers for power and has smaller widths and pitches.

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    Power Planning

    Uploaded by

    neha
    40 views7 pages
    Power planning involves distributing power uniformly to satisfy constraints. It helps reduce IR drop issues by increasing wire widths, adding power straps, and spreading cells. Factors like strap width and numbers, current densities, and metal layers used are considered. Avago uses a mesh-like grid structure with power stripes in most metal layers. Comparisons of 16nm and 28nm chips show the 16nm chip uses higher metal layers for power and has smaller widths and pitches.

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    VERY GOOD DOCUMENT OF POWER PLANNING

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    Power planning involves distributing power uniformly to satisfy constraints. It helps reduce IR drop issues by increasing wire widths, adding power straps, and spreading cells. Factors like strap width and numbers, current densities, and metal layers used are considered. Avago uses a mesh-like grid structure with power stripes in most metal layers. Comparisons of 16nm and 28nm chips show the 16nm chip uses higher metal layers for power and has smaller widths and pitches.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views7 pages

    Power Planning

    Uploaded by

    neha
    Power planning involves distributing power uniformly to satisfy constraints. It helps reduce IR drop issues by increasing wire widths, adding power straps, and spreading cells. Factors like strap width and numbers, current densities, and metal layers used are considered. Avago uses a mesh-like grid structure with power stripes in most metal layers. Comparisons of 16nm and 28nm chips show the 16nm chip uses higher metal layers for power and has smaller widths and pitches.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 7

    Power Planning

    By Pavan Vora
    Date: 12/22/2016

    “Power Planning is an art of planning and distributing power


    structure such that each cells in design get sufficient power satisfying
    applied constraints.”

    A good Power-Planning helps in:


     Distributing uniform power.
     Providing adequate power to all power sink points.
     Improving IR drop issues, EM issues and other power related
    issues.
     Avoiding iterations too.
    IR drop refers to
    Why we do power planning before placement..?
    variations in
    voltage caused by
    current flowing
    through a resistive
    IR DROP path network.

    Static IR drop
    --Power Net wire Resistance Dynamic IR drop
    (Metal have finite -Simultaneous switching of
    Resistance; standard cells
    Ohms Law V = IR)
    Power Supply Required
    Unacceptable
    voltage Power can’t be
    voltage drop
    decreases obtained

    Consequences of IR
    Drop

    affects Setup and hold Device functionality


    Cell delay increases
    timing violations failure

    Reducing Increase width of wire,


    IR drop:
    Increase the no. of power straps,

    Use of proper blockage,

    Use of DCAP cells,

    Spread cells
    Factors to be consider for Power planning:

     Power Strap width and numbers,


     Maximum current densities limits to avoid EM on power nets,
     Tradeoff between number of power straps and width
    o Congestion
     Metal Layers

    AVAGO’s Power Structure: Mesh type Grid

    Robust power structure: Power stripes in almost all metal layers


    Advantages..?
    Table 1: Comparison of Pitch, width, metal layers of Power nets for 16nm
    (Skybolt) chip and 28nm (Suru) chip
    Direction Width* Pitch* Object Type
    16 nm 28 nm 16nm 28nm 16nm 28nm 16nm 28nm
    Metal 1 V H – 0.150 – 1.100 – Stripe Route
    Metal 2 H V 0.076 – 0.576 – Stripe Route –
    Metal 3 V H – 0.250 – 1.100 – Stripe Route
    Metal 4 H V 0.076 0.490 0.576 2.200 Stripe Route Stripe Route
    Metal 5 V H 0.144 0.250 0.720 1.100 Stripe Route Stripe Route
    (Only
    Around
    Macros/IP)

    Metal 6 H V 0.254 0.490 1.152 1.100 Stripe Route Stripe Route


    (Only
    Around
    Macros/IP)

    Metal 7 V H 0.278 0.250 1.440 1.100 Stripe Route Stripe Route


    (Only
    Around
    Macros/IP)

    Metal 8 H V 0.484 0.800 2.304 2.200 Stripe Route Stripe Route


    Metal 9 V H 0.966 0.700 5.760 4.400 Stripe Route Stripe Route
    Metal 10 H V 1.350 3.700 4.608 13.200 Stripe Route Physical Pin
    Metal 11 V H 3.250 ** 11.520 ** Stripe Route **
    Metal 12 H NA 4.050 NA 13.824 NA Physical Pin NA
    Metal 13 V NA ** NA ** NA ** NA

    *Width and Pitch are in micron meter


    **Reserved For Top Layer Routing
    Figure 1: Power structure Metal4-Metal5 Snapshot (16nm)

    Figure 2: Standard Cells VDD and VSS Pins on Metal 1 and Metal 2 (16nm)
    Figure 3: Standard Cells VDD and VSS Pins Connected to Metal 2 Power Net
    (16nm)

    Figure 4: Power Stripe Routing around Macros on M5, M6 and M7 (28nm)


    Figure 5: Standard Cells VDD and VSS Pins connected to Power net on metal
    1 (28nm)

    Table 2: Summary

    Technology 16 nm - Skybolt 28 nm - Suru


    Command ag_add_power_grid ag_add_power_grid
    Min Layer M2 M1
    Max Layer M12 M10
    Standard Cells power Pins M2 M1
    Power Planning Tracking 2-12lm_enterprise 1-10lm_enterprise_fullgrid
    Config

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