STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify the truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate
has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function.
The output is high when both the inputs are high. The output is low level when any one of the
inputs is low.
OR GATE:

The OR gate performs a logical addition commonly known as OR function. The

output is high when any one of the inputs is high. The output is low level when both the
inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.

NAND GATE:

1
 The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both
the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
2
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :
3
SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

4
NOR GATE:

RESULT:
Thus the logic gates are studied and their truth tables are verified.
EX.NO: 1 VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES
5
DATE:

AIM:
To verify the Boolean theorems using logic gates.

APPARATUS REQUIRED:

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. AND GATE IC 7486 1
2. IC 7404 1
OR GATE
3. IC 7432 1
4. NOT GATE IC7408 1
5. IC TRAINER KIT - 1
6. CONNECTING Few
WIRES

THEORY:
Boolean algebra is used to simplify and rearrange Boolean equations to make
simple logic circuit. There are three basic laws of Boolean algebra. They are commutative
law, distributive law and associative law.

COMMUTATIVE LAW:
1. A+B = B+A

This law states that order in which variable makes no changes in output.The trth table
are identical.Therefore A OR B is same as B OR A

2. A.B=B.A
This law states thatorder in which variable and AND makes no difference in output
The truth table A AND B and B AND A are same.

Commutative Law:-
(i) A.B = B.A

IC7408 IC7408
A 1 B 1
C = A. B C = B .A
B 2 3 A 2 3

A B A=B A B B -A
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

6
 (ii) A+ B=B+A

IC7432 IC7432
A 1 B 2
A+B B+A
B 2 3 A 1 3

A B A+B A B B+A
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1

Associative law
(i) A(BC) = (AB)C
IC 7408

A 4 A(BC) A 1 3 4
6 B (AB) C
5 IC 7408
2 6

5
B 1 IC 7408

C 3 C
2 IC 7408
A B C BC A (BC) A B C AB (AB) C
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 0 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

(ii) A +(B + C) = (A+B) +C

IC7432
A 4 A + (B + C) A 1 A+B 4
6 3 6 (A+B)+C
B

B 1 5 IC7432 2 5 IC7432

C 3 B+C C
2
7
 A B C B+C A + (B+C) A B C A+B (A+B) + C
0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 0 1 0 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

Distributive law
IC7408

A 3 A(B+C)
4 6

B 1 C+B

C 2
IC7432

A 1 IC7408

AB
B 2 3
IC7432

1 AB + AC
3
2

4
AC
C 5 6 IC7408

A B C B+C A (B+C) A B C AB AC AB +A C
0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0
0 1 1 1 0 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 0 1
1 1 0 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1

8
DeMorgan’s Theorem

IC7408
A 1 A.B A.B
B 2 3
IC7404
IC7404

A
A 1 2
3
A+ B
IC7404

B 4 5
IC7432

B 3 4

A B A.B A.B A B A B A+B

0 0 0 1 0 0 1 1 1
0 1 0 1 0 1 1 0 1
1 0 0 1 1 0 0 1 1
1 1 1 0 1 1 0 0 0
IC7432
A 1 A+B A+B

B 2 3

IC7404

A 1 2 A
3

5
4 A B

3 4 IC7404
B IC7408
B

9
 A B A+B A+B A B A B A B
0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0

ASSOCIATIVE LAW:
1. A+(B+C) = (A+B)+C
This law states that in opening at several variables that reslts same regards at grouping
of variables A OR B with open with c is same as A opened with B OR C.

2. (AB)C = A(BC)

The associative law at multiplication states that if makes different is what order the
variable are grouped when AND use in several variable A and B AND with B AND A.

DISTRIBUTIVE LAW:

A (B+C) = AB + AC
This distributive law states that opening several variable using and adding the result with a
single variables is equivalent to A.It is important to note the distribution property. System
design used in reverse use to as expression out of (AB+AC)

DUALITY THEOREM:
By the duality theorem we can derive another Boolean equation by changing each OR sign
to an AND sign and changing each AND sign to an OR sign and complementing any 0 or 1
altering in the equation.

DEMORGAN’S THEOREM
DeMorgan’s suggested two Theorem that form an important part of Boolean algebra.
They are,
1. (AB) = A + B
The complement of the product is equal to the sum of the complements.
2. (A+B) = A B
The complement o sum is equal to the product of the complements.

10
Procedure:

1. The given AND gate and OR gate are placed in a given track in current position.

2. The pin number of AND and OR gate is shortened and then grounded.

3. The input and output is given to pin number as per the diagram.

4. The switches are on and the corresponding output is noted.

Result:
Thus the Boolean Theorems were verified using logic gates.

11
EXPT NO : 02) a) DESIGN OF ADDER AND SUBTRACTOR
DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:
HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

12
FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half subtractor
put together gives a full subtractor .The first half subtractor will be C and A B. The output
will be difference output of full subtractor. The expression AB assembles the borrow output
of the half subtractor and the second term is the inverted difference output of first X-OR.
LOGIC DIAGRAM:
HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:
13
FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

14
 CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

15
 BORROW = A’B

LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
16
 A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

17
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus half adder, full adder, half subtractor and full subtractor circuits was designed
using logic gates and their truth tables were verified.

EX NO: 2) b) DESIGN AND IMPLEMENTATION OF ARBITRARY FUNCTION

Date:
18
Aim:-

To simplify the Boolean function

F1 (A,B,C,D) =  (0,2,3,7,5,8,11,15)
F2 (A,B,C,D) =  (1,4,5,6,12,14,15)

Components required:-

SL.NO COMPONENTS SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. 3 Input AND gate IC 7411 1
3. OR gate IC 7432 1
4. AND gate IC7408 1
5. Patch cords - 1

Theory:-
The Boolean function can implemented using logic gates. The components of the logic
gates directly related to implicitly of algebra expression for which it is essential to simply the
expression
Algebra means of minimization because it tools specific process value product such step
in manipulation proves the other hand the map – method.

Function – 1
F1 (A,B,C,D) =  (0,2,3,7,5,8,11,15)
Procedure:-
The above expression is first simplify by K-map and given by
F1 (A, B, C, D) = (CD +B C D + A B C + ABD)
The implement function are need two input OR, AND, NOT Gates.
The connection is given as shown in connecting diagram ad the out is tabulated.

Function – 2
F2 (A, B, C, D) =  (1, 4, 5, 6, 12, 14, 15)
Procedure:-
The above expression is first simplify by K-map and given by
F1 (A, B, C, D) = ABC + A C D + B D
The implement function are need two input OR, AND, NOT Gates.
The connection is given as shown in connecting diagram ad the out is tabulated.
1

1
1 1

1
CD 00 01 11 10
19 1 1
 AB

00

01

11

10
Y = BD + ACD + ABC

Y = B D + A C D + ABC

Input Output

A B C D Y = CD + B C D + A B D + A B C Y= B D +A C D
20
 + ABC
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 1 1
0 1 0 1 0 1
0 1 1 0 1 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 0 0
1 1 1 0 0 1
1 1 1 1 1 1

Pin detail of IC7411 (3 Input AND gate)

VCC 2
1 13
2 12

3 I 1
4 C 10
5 7 9
4
1
6 1 8
7 GND

1 1 1

1 1
CD 00 01 11 10
1
21

1
1
 AB
00

01

11

10

Y = CD + B C D + A B D + A B C

Pin diagram for IC 74180

22
Function table:
inputs Active Outputs
Number at high data PE PO E )
inputs
Even 1 0 1 0
Odd 1 0 0 1
Eve 0 1 0 1
Odd 0 1 1 0
X 1 1 0 0
X 0 0 1 1

Result:
Thus the Boolean function was simplified and verified successfully

EXPT NO : 2) c) DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

DATE :

23
AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuit that makes the two systems compatible even though each
uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
24
K-Map for G3:

G 3 = B3
K-Map for G2:

K-Map for G1:

25
K-Map for G0:

TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

26
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3

27
K-Map for B2:

K-Map for B1:

K-Map for B0:

28
TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit Binary to Gray code Converter and Gray to Binary code Converter was
designed and implemented.

29
EXPT NO : 2) d) DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
DATE :

AIM:
To design and implement 4-bit
(i) BCD to excess-3 code converter
(ii) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuit that makes the two systems compatible even though each
uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.

30
LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

31
K-Map for E1:

K-Map for E0:

32
TRUTH TABLE:
| BCD input | Excess – 3 output |
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

33
K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

34
K-Map for D:

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit BCD to Excess-3 code Converter andExcess-3 code to BCD Converter
was designed and implemented.

35
EXPT NO: 3) a)
DATE :
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends bits
of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits. The carries are connected in chain through the
full adder. The input carry to the adder is C0 and it ripples through the full adder to the output
carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C 0 must be
equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot
be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits
must be represented in BCD and should appear in the form listed in the columns.

36
 ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

37
TRUTH TABLE

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

K MAP
38
 Y = S4S3+S4S2
S3 (S4 + S2)

LOGIC DIAGRAM:
BCD ADDER

39
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit adder/ subtractor and BCD adder using IC 7483 was designed and
implemented

40
EXPT NO : 3) b)
DATE :

16 BIT ODD/EVEN PARITY CHECKER /GENERATOR

AIM:
To design and implement 16 bit odd/even parity checker generator using IC 74180.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. NOT GATE IC 7404 1
1. IC 74180 IC 74180 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:

A parity bit is used for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number is either even or
odd. The message including the parity bit is transmitted and then checked at the receiver ends
for errors. An error is detected if the checked parity bit doesn’t correspond to the one
transmitted. The circuit that generates the parity bit in the transmitter is called a ‘parity
generator’ and the circuit that checks the parity in the receiver is called a ‘parity checker’.
In even parity, the added parity bit will make the total number is even amount. In odd
parity, the added parity bit will make the total number is odd amount. The parity checker
circuit checks for possible errors in the transmission. If the information is passed in even
parity, then the bits required must have an even number of 1’s. An error occur during
transmission, if the received bits have an odd number of 1’s indicating that one bit has
changed in value during transmission.

41
PIN DIAGRAM FOR IC 74180:

FUNCTION TABLE:
INPUTS OUTPUTS
Number of High Data PE PO ∑E ∑O
Inputs (I0 – I7)
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0

0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0

0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:
16 BIT ODD/EVEN PARITY GENERATOR

42
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the 16 bit odd /even parity checker generator was designed and implemented
using IC 74180.

EXPT NO: 3) c)
DATE :
43
 DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operator that determine one number is greater
than, less than (or) equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determine their relative magnitude. The
outcome of the comparator is specified by three binary variables that indicate whether A>B,
A=B (or) A<B.
A = A3 A2 A1 A0
B = B 3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit
designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of
significant digits starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,

44
 A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
   
x3 x2 x1 x0

LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

K MAP

45
TRUTH TABLE
46
 A1 A0 B1 B0 A> B A=B A< B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR

47
TRUTH TABLE:
A B A>B A=B A<B
0000 0 000 0000 0000 0 1 0
0001 1000 0000 0000 1 0 0
0000 0 000 0001 0001 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the 2-bit magnitude comparator was designed and implemented using logic
gates and 8-bit magnitude comparator using IC 7485.

EXPT NO : 3) d)
DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

48
AIM:
To design and implement multiplexer and demultiplexer using logic gates and study
of IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are
2n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

49
FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
50
 0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

51
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150:

52
PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer was designed and implemented using logic
gates and IC74150, IC74154 was studied.

EXPT NO : 4) a)
DATE :
53
 DESIGN AND IMPLEMENTATION OF SISO & SIPO SHIFT REGISTERS

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

54
TRUTH TABLE:
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD

55
 1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the design and implementation of
1. Serial in serial Out (SISO)
2. Serial in parallel Out (SIPO) were done successfully.

EXPT NO : 4) b)
DATE :
DESIGN AND IMPLEMENTATION OF PISO & PIPO SHIFT REGISTERS

AIM:
To design and implement
56
 (i) Parallel in serial out
(ii) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.
PIN DIAGRAM:

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

57
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT
DA DB DC DD QA QB QC QD
CLK
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

58
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus the design and implementation of
1. Parallel in serial Out (PISO)
2. Parallel in parallel Out (PIPO) were done successfully.

EXPT NO : 4) c) i)
DATE :
DESIGN AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12
RIPPLE COUNTER

AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

59
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time
all flip flops are not activated at same time which results in asynchronous operation.
PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

60
TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

61
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
62
 3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
Thus 4-bit ripple counter, MOD-10 and MOD-12 ripple counter was constructed and
verified successfully.

EXPT NO : 4) c) ii)
DATE :
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

63
 Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that
is capable of progressing in increasing order or decreasing order through a certain sequence.
An up/down counter is also called bidirectional counter. Usually up/down operation of the
counter is controlled by up/down signal. When this signal is high counter goes through up
sequence and when up/down signal is low counter follows reverse sequence.

K MAP

STATE DIAGRAM:

64
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:

65
 TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

66
RESULT:
Thus 3- bit synchronous up/down counter was designed and implemented
successfully.

Basic design process using ISE 9.1i

1. Starting the ISE Software
To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting:

67
Start → Programs → Xilinx ISE 9.1i → Project Navigator

2. Create a New Project

To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory
is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.

Figure 1: Create New Project

6. Fill in the properties in the table as shown below:

♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:

68
 Figure 2: Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project Wizard.

3. Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name adder.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:

Figure 3: Define Module

69
7. Click Next, then Finish in the New Source Information dialog box to complete the new
source file template.
8. Click Next, then Next, then Finish.

The source file containing the adder Module displays in the Workspace, and the adder
displays in the Sources tab, as shown below:

Figure 4: New Project in ISE

4. Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors.
1. Verify that Synthesis/Implementation is selected from the drop-down list in the
Sources window.

Figure 5: Synthesis/Implementation Selection

2. Select the adder design source in the Sources window to display the related
processes in the Processes window.
3. Click the “+” next to the Synthesize-XST process to expand the process group.

70
 Figure 6: Synthesize- XST Expansion

3. Double-click the Check Syntax process.

Figure 7: Double click to Check Syntax

Note: You must correct any errors found in your source files. You can check for errors in
the Console tab of the Transcript window. If you continue without valid syntax, you will not
be able to simulate or synthesize your design.

71
 Figure 8: After correcting errors

5. Close the HDL file.

5. Simulating Design Functionality

Verify that the adder design functions as you expect by performing behavior simulation as
follows:
1. Verify that Behavioral Simulation is selected in the Sources window.

Figure 9: Behavioral Simulation Selection

2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process
and double-click the Simulate Behavioral Model process.

Figure 10: Simulate Behavioral Model

The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the

72
transitions.
The simulation waveform results will look like the following:

Figure 11: Simulation waveform

73
EX NO : 5) a)
Date:
SIMULATION OF COMBINATIONAL CIRCUIT USING VERILOG HDL
AIM:
To design Adder/Subtractor using HDL software
FULL ADDER:

VERILOG CODE FOR FULLADDER

Module fulladder (a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry= a&b|b&c|a&c;
end Module
OUTPUT

HALF SUBTRACTOR:

74
VERILOG CODE FOR HALF SUBTRACTOR:
Module halfsubtractor (a,b,difference ,borrow);
input a,b;
output difference,borrow;
assign difference=a^b;
assign borrow = ~a&b;
end Module

4:1 MULTIPLEXER

VERILOG CODE FOR 4:1 MULTIPLEXER:

Module mux(s,d0,d1,d2,d3,y);
input d0,d1,d2,d3;
input[1:0]s;
output y;
assign y=((d0&~s[1]&~&s[0])|( d1&~s[1]&s[0])|( d2&s[1]&~s[0])|
(d3&s[1]&s[0]));
end Module

75
OUTPUT:

1:4 DEMULTIPLEXER:

VERILOG CODE FOR 1:4 DEMULTIPLEXER:

Module mux(s,a,d0,d1,d2,d3);
input a;
input[1:0]s;
output d0,d1,d2,d3;
assign d0=(~s[1]&~s[0]&a);
assign d1=(~s[1]&s[0]&a);
assign d2=(s[1]&~s[0]&a);
assign d3=(s[1]&s[0]&a);
end Module

76
OUTPUT:

PROCEDURE:
1. Draw the Digital logic circuits.
2. Write the Verilog code for above circuits.
3. Enter the Verilog code in ModelSim software.
4. Check the syntax and simulate the above verilog code using ModelSim and verify the
output waveform as obtained.

RESULT:

Thus the combinational logic circuits using Verilog HDL was simulated.

77
EX NO : 5) b)
Date:
SIMULATION OF SEQUENTIALCIRCUIT USING VERILOG HDL

AIM:
To design Shift Register using HDL software.

SERIAL IN SERIAL OUT

VERILOG CODE SERIAL IN SERIAL OUT REGISTER

Module siso (clk,si,s0);
input clk,si;
output s0;
reg[3:0]tmp;
always@(posedge clk)
begin
tmp=tmp<<1;
tmp[0]=si;
end
assign s0=tmp[3];
endmodule
OUTPUT:

78
SERIAL IN PARALLEL OUT

VERILOG PROGRAM FOR SIPO SHIFT REGISTER

Module sipo(clk,si,po);
input clk,si;
output[3:0]po;
reg [3:0]tmp;
always @(posedge clk)
begin
tmp<={tmp[2:0],si};
end
assign po=tmp;
endmodule
OUTPUT

PARALLEL IN PARALLEL OUT:

79
VERILOG PROGRAM FOR PIPO SHIFT REGISTER
Module pipo(pin,clk,clr,pout);
input [3:0] pin;
input clk,clr;
output [3:0] pout;
wire [3:0]pin;
wire clk,clr;
reg[3:0] pout;
always @(posedge clk or negedge clr)
begin
if(!clr)
begin
pout<=4’b0;
end
else
begin
pout<=pin;
end
end
endmodule

OUTPUT

D FLIP FLOP

80
VERILOG CODE FOR D FLIP FLOP
Module dff(data,clk,clr,q);
input data,clk,clr;
output q;
reg q;
always@(posedge clk or negedge clr)
if(~clr)
begin
q<=1’b0;
end
else
begin
q<=data;
end
end Module
OUTPUT

T FLIP FLOP

81
VERILOG CODE FOR T FLIP FLOP

Module tff(data,clk,clr,q);
input data,clk,clr;
output q;
reg q;
always@(posedge clk or negedge clr)
if(~clr)
begin
q<=1’b0;
end
else if(data)
begin
q<=!q;
end
end Module

OUTPUT

JK FLIP FLOP

VERILOG CODE FOR JK FLIP FLOP

Module jkff(clk,clr,j,k,q);
input clk,clr,j,k;
output q;
reg q;
always@(posedge clk,negedge clr)
if(~clr)q=0;
else
begin

82
case({j,k})
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=~q;
endcase
end
endmodule

OUTPUT

RESULT:

Thus the sequential logic circuit using verilog HDL was verified

EX NO : 6)
83
Date:
CLOCK -PULSE GENERATOR

Aim: To design and implement clock-pulse generator and study IC555 timer.
APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC Trainer kit - 1
2. Resistors - 2
3. IC 555 timer 1
4. Patch cords
5. Capacitors 2

THEORY:
IC TIMER:
IC type 555 is a precision timer circuit whose internal logic is shown in figure.The
resistors Ra and Rb and the two capacitors are not part of the IC.The circuit consists of two
voltage comparators,a flip-flop,and an internal transistor.The voltage division from vcc=5v
through the three internal resistors to ground produces 2/3 and 1/3 of vcc.(3.3v and 1.7v
respectively) into the fixed inputs of the comparators.When the threshold input at pin 6 goes
above 3.3v,the upper comparator resets the flip-flop and the output goes low to about
0v.When the trigger input at pin 2 goes below 1.7v,the lower comparator sets the flip-flop and
the output goes high to about 5v.When the output is low,Q’ is high and the base-emitter
junction of the transistor is forward biased.When the output is high,Q’ is low and the
transistor is cutoff.The timer circuit is capable of producing accurate time delays controlled
by an external RC circuit.In this experiment,the IC timer will be operated in the astable Mode
to produce clock pulses.
Circuit operation
The external connections for astable operation of the circuit is shown in
figure.Capacitor c charges through resistors Ra and Rb when the transistor is cut off and
discharges through Rb when the transistor is forward biased and conducting.When the
charging voltage across capacitor C reaches 3.3v ,the threshold input at pin 6 causes the flip-
flop to reset and the transistor turns on .When the discharging voltage reaches 1.7v,the trigger
input at pin 2 causes the flip-flop to set and the transistor turnsoff.Thus,the output continually
alternates between two voltage levels at the output of the flip-flop.theoutput remains high for
a duration equal to the charge time.This duration is determined from the equation
Td=0.693(Ra+Rb)C

The output remains low for a duration equal to the discharge time.This duration is
determined from the equation
84
 Tl=0.693RbC

Procedure:
Starting with a capacitor C of 0.001 µF,calculate values for Ra and Rb to produce
clock pulses as shown in figure.The pulse width is 1µs in the low level and repeats at a
frequency rate of 100kHz(every 10 µs).connect the circuit and check the output in the
oscilloscope.
Observe the output across the capacitor C,and records its two levels to verify that they
are between the trigger and threshold values.
Observe the waveform in the collector of the transistor at pin 7 and record all
pertinent information.Explain the waveform by analyzing the circuit’s action.
Connect a variable resistor in series with Ra to produce a variable-frequency pulse
generator.The low-level duration remains at 1 µs.The frequency should range from 2o to 100
kHz.
Change the low-level pulses to high level pulses with a 7404 inverter.This will
produce positive pulses of 1 µs with a variable –frequency range.

Result:

The clock generator with required frequency is designed using IC 555 timer.

EX NO: 7)
85
Date:
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
AIM:
To design and implement encoder and decoder using logic gates and study of IC 7445
and IC 74147.
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - 27

THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n
output values are from 0 through out 2n – 1.

PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

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PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
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 1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

88
RESULT:
Thus the design and implementation of encoder and decoder using logic gates and
study of IC 7445 and IC 74147 was done successfully.

EX NO : 8)
Date:
SIMULATION OF COUNTERS USING VERILOG HDL

AIM:
To design Counters using HDL software.

4-Bit Ripple Counter:

89
TRUTH TABLE:

COUNT A0 A1 A2 A3
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

//Structural description of Ripple Counter

Module ripplecounter(A0,A1,A2,A3,COUNT,RESET);
output A0,A1,A2,A3;
input COUNT,RESET;
//Instantiate Flip-Flop
FF F0(A0,COUNT,RESET);
FF F1(A1,A0,RESET);
FF F2(A2,A1,RESET);
FF F3(A3,A2,RESET);
endmodule

90
//Description of Flip-Flop
Module FF(Q,CLK,RESET);
output Q;
input CLK,RESET;
reg Q;
always @(negedge CLK or negedge RESET)
if(~RESET)
Q=1'b0;
else
Q=(~Q);
endmodule

//Stimulus for testing Ripple Counter

Module simulation;
reg COUNT;
reg RESET;
wire A0,A1,A2,A3;
//Instantiate Ripple Counter
ripplecounter rc_t(A0,A1,A2,A3,COUNT,RESET);
always
#5 COUNT=~COUNT;
initial
begin
COUNT=1'b0;
RESET=1'b0;
#10 RESET=1'b1;
end
endmodule

LOGIC DIAGRAM:
MOD-10 Ripple Counter:

91
TRUTH TABLE:

COUNT A0 A1 A2 A3
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

//Structural description of MOD10 Counter

Module MOD10(A0,A1,A2,A3,COUNT);
output A0,A1,A2,A3;
input COUNT;
wire RESET;
//Instantiate Flip-Flop
FF F0(A0,COUNT,RESET);
FF F1(A1,A0,RESET);
FF F2(A2,A1,RESET);
FF F3(A3,A2,RESET);
//Instantiate Primitive gate
nand (RESET,A1,A3);
endmodule
//Description of Flip-Flop
Module FF(Q,CLK,RESET);
output Q;
input CLK,RESET;
reg Q=1'b0;
always @(negedge CLK or negedge RESET)

92
if(~RESET)
Q=1'b0;
else
Q=(~Q);
endmodule

//Stimulus for testing MOD10 Counter

Module simulation;
reg COUNT;
wire A0,A1,A2,A3;
//Instantiate MOD10 Counter
MOD10 MOD10_TEST(A0,A1,A2,A3,COUNT);
always
#10 COUNT=~COUNT;
initial
begin
COUNT=1'b0;
end
endmodule

LOGIC DIAGRAM:
MOD-12 Ripple Counter:

TRUTH TABLE:

COUNT A0 A1 A2 A3
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
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9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
//Structural description of MOD12 Counter
Module MOD12(A0,A1,A2,A3,COUNT);
output A0,A1,A2,A3;
input COUNT;
wire RESET;
//Instantiate Flip-Flop
FF F0(A0,COUNT,RESET);
FF F1(A1,A0,RESET);
FF F2(A2,A1,RESET);
FF F3(A3,A2,RESET);
//Instantiate Primitive gates
nand (RESET,A2,A3);
endmodule

//Description of Flip-Flop
Module FF(Q,CLK,RESET);
output Q;
input CLK,RESET;
reg Q=1'b0;
always @(negedge CLK or negedge RESET)
if(~RESET)
Q=1'b0;
else
Q=(~Q);
endmodule
//Stimulus for testing MOD12 Counter
Module simulation;
reg COUNT;
wire A0,A1,A2,A3;
//Instantiate MOD12 Counter
MOD12 MOD12_TEST(A0,A1,A2,A3,COUNT);
always
#10 COUNT=~COUNT;
initial
begin
COUNT=1'b0;
end
endmodule

94
Result

Thus the 4 – Bit , MOD10 and MOD12 Ripple counter was verified Verilog HDL
software.

95