Design and simulation of 2:1 mux using multiple logic gates

CHAPTER 1

OVERVIEW OF THE PROJECT

This chapter include introduction about the project, problem statement,

motivation, objective, methodology adopted, tools required, organization of the
report.

1.1 INTRODUCTION
MUX is a data selector that selects one of several analog or digital input
signals and forwards the selected input into a single output line. A multiplexer of 2𝑛
inputs has n select lines, which are used to select which input line to send to the
output. 2:1 MUX is a basic block of the “switch logic” .It has two input lines D0 and
D1, one select line S and one output line. The truth table of 2:1 MUX is given in
Table I; the logic function is

Y=𝑆̅.𝐷0 + S. 𝐷1

Static CMOS circuit is used in various logic gates in integrated circuits. These
are designed with complementary nMOS Pull-Down network and pmos Pull Up
network. They have simple design; hence they are insensitive to variations, good
noise margins, fast operating speed and low power. Nevertheless, performance or area
constraints occasionally dictate the need for other circuit families and the most
important alternate is dynamic circuits.
Dynamic circuit uses simple sequential circuits along with memory functions.
It is dependent on temporary storage of charges in parasitic node capacitance.
Dynamic circuits require less over conventional Static Logic circuits. Thus these
circuits have gained a widespread use .It also uses a sequence of Precharge and
Evaluation Phases governed by the clock to recognize complex logic functions.
Complementary metal–oxide–semiconductor (CMOS) is a technology for
constructing integrated circuits, and is a form of MOSFET (metal–oxide–
semiconductor field-effect transistor) semiconductor. CMOS technology is used in
microprocessors, microcontrollers, static RAM, and other digital logic circuits.
CMOS technology is also used for several analog circuits such as image sensors
(CMOS sensor), data converters, and highly integrated transceivers for many types of
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Design and simulation of 2:1 mux using multiple logic gates

communication. CMOS was invented by Chih-Tang Sah and Frank Wanlass at

Fairchild Semiconductor in 1963, and is used in most modern LSI and VLSI devices.
CMOS is sometimes referred to as complementary-symmetry metal–oxide–
semiconductor (COS-MOS), but "COS-MOS" was an RCA trademark, which forced
other manufacturers to find another name. The words "complementary symmetry"
refer to the typical design style with CMOS using complementary and symmetrical
pairs of p-type and n-type metal–oxide–semiconductor field-effect transistors for
logicfunctions.
Two important characteristics of CMOS devices are high noise immunity and
low static power consumption. Since one transistor of the pair is always off, the series
combination draws significant power only momentarily during switching between on
and off states. Consequently, CMOS devices do not produce as much waste heat as
other forms of logic, for example transistor–transistor logic (TTL) or N-type metal–
oxide–semiconductor logic (NMOS) logic, which normally have some standing
current even when not changing state. CMOS also allows a high density of logic
functions on a chip. It was primarily for this reason that CMOS became the most used
technology to be implemented in very-large-scale integration (VLSI) chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical

structure of certain field-effect transistors, having a metal gate electrode placed on top
of an oxide insulator, which in turn is on top of a semiconductor material. Aluminium
was once used but now the material is polysilicon. Other metal gates have made a
comeback with the advent of high-κ dielectric materials in the CMOS process, as
announced by IBM and Intel for the 45 nanometer node and smaller sizes.

1.2 PROBLEM STATEMENT

Power and delay are the two parameters which are considered primarily.

1.3 MOTIVATION

The main motive of this research is to achieve less power dissipation and
better performance. The implementation of multiplexer by incorporating different
logic styles can analyse the power consumption and delay. This in turn will enhance
the performance of the multiplexer.

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Design and simulation of 2:1 mux using multiple logic gates

1.4 OBJECTIVE

The main objective of this project is to design 2:1 multiplexer using multiple
logic families using Mentor Graphics in 180nm technology.

1.5 METHODOLOGY ADOPTED

Power consumption and Propagation delay are the two important parameters.
So we need to have designs which take these two parameters into account. Static
cmos and domino logic techniques were used to compare the performance of cmos in
180nm technology.

1.6 TOOLS REQUIRED

“PYXIS” design suite is a software suite produced by “MENTOR GRAPHICS”

for schematic and layout design.

1.7 ORGANIZATION OF THE REPORT

Chapter 1 presents overview of project, motivation and objectives and goals

along with the specifications and applications. Chapter 2 presents literature survey
regarding the project have. This survey helped a lot in getting complete description of
the project. Chapter 3 presents CMOS circuit designs and basics related to the
circuits. Chapter 4 presents implementation of cmos based Static cmos, psuedo logic,
domino logic and dual rail domino logic. Chapter 5 presents the simulation results.
Chapter 6 presents the conclusion and future scope of the project.

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Design and simulation of 2:1 mux using multiple logic gates

CHAPTER 2
LITERATURE SURVEY
2.1 INTRODUCTION
In this chapter literature survey of the project is discussed.

2.2 GENESIS OF THE REPORT

A static CMOS gate has an nMOS pull-down network toconnect the output to
0 (GND) and pMOS pull-up network to connect the output to 1(VDD).The networks
are arranged such that one is ON and the other OFF for any input pattern.The pull-up
and pull-down networks in the inverter each consist of a single transistor. The NAND
gate uses a series pull-down network and a parallel pull-up network. More elaborate
networks are used for more complex gates. Two or more transistors in series are ON
only if all of the series transistors are ON. Two or more transistors in parallel are ON
if any of the parallel transistors are ON. By using combinations of these constructions,
CMOS combinational gates can be constructed. In general, when we join a pull-up
network to a pull-down network to form a logic gate they both will attempt to exert a
logic level at the output. The 1 and 0 levels have been encountered with the inverter
and NAND gates, where either the pull-up or pull-down is OFF and the other
structure is ON. When both pull-up and pull-down are OFF, the high-impedance or
floating Z output state results. This is of importance in multiplexers, memory
elements, and tristate bus drivers. The crowbarred (or contention) X level exists when
both pull-up and pull-down are simultaneously turned ON. Contention between the
two networks results in an indeterminate output level and dissipates static power. It is
usually an unwanted condition[1].
Since multiplexer (MUX) is one of the important components of
communication system, to increase the efficiency of data transmission, to utilize the
vast memory space of a computer in an effective way and to convert parallel form of
data into serial form in telecommunication networks an efficient design of low power-
delay MUX is required. Hence in this work, a basic 2:1 MUX is designed using
various CMOS logic families such as Static CMOS logic, Pseudo NMOS logic,
Domino logic and Dual-Rail Domino logic to identify the best logic family suitable
for the design of higher levels of MUX. The implementation is done in VLSI

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Design and simulation of 2:1 mux using multiple logic gates

technology as it has features like small size, low cost, high operating speed and low
power. The performance analysis of the MUX using various CMOS logic families are
conducted using VLSI back-hand tool: CADENCE VIRTUOSO SCHEMATIC
EDITOR 6.1 at 180nm. The results obtained show that, the Domino logic based 2:1
MUX is the most efficient design because the average power consumption is 20.06%
and PDP(Power Delay Product) is 20.1% lesser than that of other logic families. But
trade-offs are inferred between Domino logic and Static CMOS logic which can be
neglected on considering the overall performance. Since the Domino logic
outperforms the other logic families, this work suggests that any higher level MUX
with low power-delay and PDP can be achieved using Domino logic[2].
Dynamic gates are imperative for constructing wide high speed Processors,
DRAMs, SRAMs etc. But the design and operation are however, more engage and
prone to failure due to lack of design automation, a decreased tolerance to noise and
enhanced power dissipation. Thus domino logic circuit techniques are extensively
applied in high performance microprocessors due to superior speed and area
characteristics. Wide fan-in footless domino OR gate has been selected which controls
the degradation in speed for design and analysis work.
The name Domino comes from the behavior of a chain of the logic gates. It is
a non–inverting structure. It runs 1.5-2 times faster than static logic circuits. It is
simply a logic which permits high-speed operation and enables the implementation of
complex functions which otherwise is not achieved by Static and Dynamic circuits.
Domino logic offers a simple technique to eliminate the need of complex clocking
scheme by utilizing a single phase clock and have no static power consumption as it is
removed by clock input in the first stage. These logic circuits are glitch free, have fast
switching threshold and possibility to cascade. Domino circuits employ a dual-phase
dynamic logic style with each clock cycle divided into a Precharge and an Evaluation
phase[3].
Very-large-scale integration (VLSI) is the technology of an integrated circuit
(IC) by combining thousands of transistors into a single chip. It is the design of
extremely small, complex circuitry with the help of semiconductor material. It may
contain millions of transistors on a single chip is known as Integrated circuit (IC).
VLSI technology is based on Moore's law. According to the Moore’s law number of
transistors in a dense integrated circuit doubles approximately every eighteen months.

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Design and simulation of 2:1 mux using multiple logic gates

VLSI fabrication technology is still in the process of evolution which is

leading to smaller line widths and features size and to higher density of circuitry on a
chip. Scaling down of the feature size generally leads to improved performance.
Micro electronics technology may be characterized in terms of several figure of merit
.There are two types of MOS, i.e. the NMOS and the PMOS. Where NMOS transistor
can gives the “LOW” signal completely, but it has poor performance at “HIGH signal.
Same as in PMOS transistor which gives the “LOW” signal completely but poor
performance at “HIGH” signal. CMOS transistor is the combination of NMOS and
PMOS transistor which gives full output voltage swing. Power consumption is very
less in CMOS circuits compared to the NMOS design and bipolar transistors. There
are different design methodologies of designing of integrated circuit such as full
custom design, semi custom design and standard cell based design. In standard cell
design, a design is captured using the standard cells available in a library via
schematic or HDL. In the full custom design the function and layout of practically
every transistor is optimized. This paper is based on the area efficient design 2 to 1
multiplexer using microwind tool[4].
This presents the design and analysis of a 2:1 multiplexer. The conventional
circuit of 2:1 multiplexer(MUX) is used for the calculation of different parameters
like power consumption, noise, delay, leakage power, etc. The multiplexer designed
in this paper is suitable for low-power applications and works on very low supply
voltage. Multiplexer is a digital circuit, it consists of 2N input and has n select line
which are used to select the input line to transmit to the output. The multiplexer are
used to expand the measure of information that can be sent over the system of a sure
measure of time and bandwidth. Multiplexer comprises of multiple input signals and
gives a single output switch. In this paper, a novel FinFET technique is used for the
reduction of leakage power. The parameters of the conventional circuit and FinFET
are compared and the performance of the multiplexer circuit is increased. The
proposed multiplexer works on supply voltage of 0.7V. The design and simulation
of I Finfet based 2:1 multiplexer is done by using 45nm technology at cadence
virtuoso version 6.1 platform[5].
2.3 CONCLUSION
We have discussed about the static CMOS which is a combination of both
pMOS and nMOS and also about dynamic gates, domino logic, dual rail domino

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Design and simulation of 2:1 mux using multiple logic gates

logic. Various CMOS logics are considered to identity the best logic family suitable to
design higher level of MUX. In this chapter literature survey was discussed.

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Design and simulation of 2:1 mux using multiple logic gates

CHAPTER 3

COMPLEMENTARY METAL OXIDE

SEMICONDUCTOR (CMOS)

3.1 INTRODUCTION

In the previous chapter, literature survey of the project was discussed. In this
chapter, MULTIPLEXER, CMOS, PMOS, NMOS, characteristics of CMOS,
applications of CMOS, Types of CMOS and Inverter are discussed.
3.2 MULTIPLEXER
Multiplexer is a combinational circuit that has multiple inputs and a single line
output. The select lines determine which input is connected to the output, and also to
increase the amount of data that can be sent over a network within certain time. It is
also called a data selector. .
The single pole multi-position switch is a simple example of non-electronic
circuit of multiplexer, and it is widely used in many electronic circuits. The
multiplexer is used to perform high-speed switching and is constructed by electronic
components.
Multiplexers are capable of handling both analog and digital applications. In
analog applications, multiplexers are made up of relays and transistor switches,
whereas in digital applications, the multiplexers are built from standard logic gates.
When the multiplexer is used for digital applications, it is called a digital multiplexer.

3.3 MULTIPLEXER TYPES

Multiplexers are classified into four types:

a. 2-1 multiplexer (1 select line)

b. 4-1 multiplexer (2 select lines)

c. 8-1 multiplexer (3 select lines)

d. 16-1 multiplexer (4 select lines)

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Design and simulation of 2:1 mux using multiple logic gates

Figure: 3.1 MULTIPLEXER

Truth Table 3.1: 2:1 MUX

3.4 APPLICATIONS OF MULTIPLEXER

A Multiplexer is used in various applications wherein multiple data can be

transmitted using a single line.
a. Communication System – A Multiplexer is used in communication systems,
which has a transmission system and also a communication network. A Multiplexer
is used to increase the efficiency of the communication system by allowing the
transmission of data, such as audio & video data from different channels via cables
and single lines.
b. Computer Memory – A Multiplexer is used in computer memory to keep up
a vast amount of memory in the computers, and also to decrease the number of
copper lines necessary to connect the memory to other parts of the computer.
c. Telephone Network – A multiplexer is used in telephone networks to
integrate the multiple audio signals on a single line of transmission.
d. Transmission from the Computer System of a Satellite.
e. A Multiplexer is used to transmit the data signals from the computer system
of a satellite to the ground system by using a GSM communication.

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Design and simulation of 2:1 mux using multiple logic gates

3.5 CMOS
CMOS technology is one of the most popular technology in the computer chip
design industry and broadly used today to form integrated circuits in numerous and
varied applications. Today’s computer memories, CPUs and cell phones make use of
this technology due to several key advantages. This technology makes use of both P
channel and N channel semiconductor devices.
The main advantage of CMOS over NMOS and BIPOLAR technology is the
much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a
Complementary MOS circuit has almost no static power dissipation. Power is only
dissipated in case the circuit actually switches. This allows integrating more CMOS
gates on an IC than in NMOS or bipolar technology, resulting in much better
performance. Complementary Metal Oxide Semiconductor transistor consists of P-
channel MOS (PMOS) and N-channel MOS (NMOS). The CMOS transistor diagram
is shown in the figure 3.2.

Figure: 3.2 CMOS TRANSISTOR

3.6 NMOS

NMOS is built on a p-type substrate with n-type source and drain diffused on
it. In NMOS, the majority carriers are electrons. When a high voltage is applied to the
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Design and simulation of 2:1 mux using multiple logic gates

gate, the NMOS will conduct. Similarly, when a low voltage is applied to the gate,
NMOS will not conduct. NMOS are considered to be faster than PMOS, since the
carriers in NMOS, which are electrons, travel twice as fast as the holes. The NMOS
transistor is as shown in the figure 3.3.

Figure: 3.3 NMOS Transistor

3.7 PMOS

P- Channel MOSFET consists P-type Source and Drain diffused on an N-type

substrate. Majority carriers are holes. When a high voltage is applied to the gate, the
PMOS will not conduct. When a low voltage is applied to the gate, the PMOS will
conduct. The PMOS devices are more immune to noise than NMOS devices. The
PMOS transistor is as shown in the figure 3.4.

Figure: 3.4 PMOS transistor

3.8 CMOS Working Principle

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Design and simulation of 2:1 mux using multiple logic gates

In CMOS technology, both N-type and P-type transistors are used to design
logic functions. The same signal which turns ON a transistor of one type is used to
turn OFF a transistor of the other type. This characteristic allows the design of logic
devices using only simple switches, without the need for a pull-up resistor.
In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-
down network between the output and the low voltage power supply rail .Instead of
the load resistor of NMOS logic gates, CMOS logicgates have a collection of p-type
MOSFETs in a pull-up network between the output and the higher-voltage rail (often
named Vdd).
Thus, if both a p-type and n-type transistor have their gates connected to the
same input, the p-type MOSFET will be ON when the n-type MOSFET is OFF, and
vice-versa. The networks are arranged such that one is ON and the other OFF for any
input pattern as shown in the figure 3.5.

Figure: 3.5 CMOS Logic Gate using Pull-Up and Pull-Down Networks

CMOS offers relatively high speed, low power dissipation, high noise
margins in both states, and will operate over a wide range of source and input voltages
(provided the source voltage is fixed). Furthermore, for the better understanding of the

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Design and simulation of 2:1 mux using multiple logic gates

Complementary Metal Oxide Semiconductor working principle, we need to discuss in

brief about CMOS logic gates as explained below.

3.9 CMOS Inverter

The inverter circuit as shown in the figure 3.6. It consists of PMOS and
NMOS FET. The input A serves as the gate voltage for both transistors.

Figure: 3.6 CMOS inverter

The NMOS enhancement mode transistor has an input from Vss (ground) and
PMOS transistor has an input from Vdd. The terminal Y is output. When a high
voltage (~ Vdd) is given at input terminal (A) of the inverter, the PMOS becomes
open circuit and NMOS switched OFF so the output will be pulled down to Vss.
When a low-level voltage (<Vdd, ~0v) applied to the inverter, the NMOS
switched OFF and PMOS switched ON. So the output becomes Vdd or the circuit is
pulled up to Vdd. The truth table of CMOS inverter is as shown in the table 3.2.
Truth Table 3.2: CMOS inverter
INPUT LOGIC INPUT OUTPUT LOGIC OUTPUT

0v 0 Vdd 1

Vdd 1 0v 0

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Design and simulation of 2:1 mux using multiple logic gates

3.10 CHARACTERISTICS OF CMOS

The following are the characteristics of CMOS:
a. Dissipates low power: The power dissipation is dependent on the power
supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load,
the power dissipation is typically 10 nW per gate.
b. Short propagation delays: Depending on the power supply, the propagation
delays are usually around 25 nS to 50 nS.
c. Rise and fall times are controlled: The rise and falls are usually ramps
instead of step functions, and they are 20 - 40% longer than the propagation delays.
d. Noise immunity approaches 50% or 45% of the full logic swing.
e. Levels of the logic signal will be essentially equal to the power supplied
since the input impedance is so high.
f. Voltage levels range from 0 to VDD where VDD is the supply voltage. A
low level is anywhere between 0 and 1/3 VDD while a high level is between 2/3 VDD
and VDD.
3.11 APPLICATIONS OF CMOS
Complementary MOS processes were widely implemented and have
fundamentally replaced NMOS and bipolar processes for nearly all digital logic
applications. The CMOS Technology has been used for the following digital IC
designs.
a. Computer memories, CPUs
b. Microprocessor designs
c. Flash memory chip designing
d. Used to design application specific integrated circuits (ASICs)
3.12 TYPES OF CMOS
There are two types of CMOS logic families such as static and dynamic circuits.
3.12.1 STATIC CMOS
Static CMOS circuits are used in various logic gates in integrated circuits. These
are designed with complementary nMOS Pull-Down Network (PDN) and pMOS Pull-
Up Networks (PUN). They have simple design; hence they are insensitive to
variations, good noise margins, fast operating speed and low power. Nevertheless,
performance or area constraints occasionally dictate the need for other circuit families

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Design and simulation of 2:1 mux using multiple logic gates

and the most important alternative is dynamic circuits. The static is as shown in the
figure 3.7.

Figure: 3.7 Static CMOS

3.12.2 DYNAMIC CMOS
Dynamic circuit uses simple sequential circuits along with memory functions.
It is dependent on temporary storage of charges in parasitic node capacitance.
Dynamic circuits require less silicon area and have superior performance over
conventional Static Logic circuits. Thus these circuits have gained a widespread use
.It also uses a sequence of Precharge and Evaluation Phases governed by the clock to
recognize complex logic functions. The dynamic CMOS is as shown in the figure 3.8.

Figure: 3.8 Dynamic CMOS

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Design and simulation of 2:1 mux using multiple logic gates

a. recharge Phase
When clock signal (Φ) = 0, the output node Out is precharged to VDD by the
PMOS transistor Mp and the evaluate NMOS transistor remains off, so that the pull-
down path is disabled.
b. Evaluation Phase
In the PDN when clock signal (Φ) = 1, the pre-charge transistor Mp is OFF,
and the evaluation transistor Me is turned ON. Both the circuit families have different
types of logics. Considering the above mentioned features, static CMOS logic and
pseudo NMOS are chosen from static circuits and Domino and Dual Rail logic are
selected from dynamic circuits, for the implementation of a MUX. There is wide
scope for research in the field of CMOS logic families in spite of many designs
proposed till date .
Very-large-scale integration (VLSI) is the technology that provides a
platform in designing a complex circuitry even with millions of transistors in an
extremely small space on a single chip known as Integrated circuit (IC) . Reduced
size, fast operating speed, high reliability and reduced area are the advantages of
VLSI. Thus this entire work is implemented using a VLSI back-end tool, to
determine the performance metrics of various CMOS logic families.
3.13 CONCLUSION
In this chapter, MULTIPLEXER, CMOS, PMOS, NMOS, Inverter,
characteristics of CMOS, applications of CMOS and Types of CMOS and are
discussed.

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Design and simulation of 2:1 mux using multiple logic gates

CHAPTER 4
IMPLEMENATION OF 2:1 MULTIPLEXER USING
MULTIPLE LOGIC FAMILIES
4.1 INTRODUCTION
In the previous chapter topics like MULTIPLEXER, CMOS, PMOS, NMOS,
Inverter, characteristics of CMOS, applications of CMOS and Types of CMOS and
are discussed.
In this chapter topics like STATIC CMOS LOGIC, PSEUDO NMOS LOGIC,
DUAL RAIL DOMINO LOGIC, DOMINO LOGIC are discussed.
4.2 STATIC CMOS LOGIC
Static CMOS Logic is constructed with the help of a PUN and a PDN .The
function of the PUN is to provide a connection between the output and VDD when
the output of the logic gate is supposed to be 1. Similarly, the PDN connects the
output to ground when the output is expected to be 0. The PUN and PDN networks
are constructed in a mutually exclusive manner such that either PDN or PUN is
conducting in steady state. One of the major advantages of Static CMOS logic is that
they have zero quiescent power dissipation, where for any applied input state either
the PUN or the PDN remains off. The problem with this type of implementation is
that more area is required in implementing logics. This has an impact on the
capacitance and thus the speed of the gate. The Static CMOS Logic is as shown in the
figure 4.1.

Figure: 4.1 Static CMOS circuit

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Design and simulation of 2:1 mux using multiple logic gates

4.3 PSEUDO NMOS LOGIC

In Pseudo NMOS Logic the PDN is like that of an ordinary static gate, but the
PUN has been replaced with a single pMOS transistor that is grounded so it is always
ON. The pMOS transistor widths are selected to be about 1/4 the strength of the
NMOS PDN as a compromise between noise margin and speed; this best size is
process-dependent. In this way the area required to implement logics have been
reduced which in turn increases the speed. But these Pseudo NMOS logics have
various other drawbacks such as slow rising transitions, contention on the falling
transitions, static power dissipation. The Pseudo NMOS Logic is as shown in the
figure 4.2.

Figure: 4.2 Pseudo NMOS circuit

4.4 DOMINO LOGIC

Logics circumvent the drawbacks of Pseudo NMOS by using a clocked PUN

rather than a pMOS that is always ON. But the main issue in Dynamic logic compared
to Static CMOS logic, is the monotonicity requirement. During an evaluation phase of
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Design and simulation of 2:1 mux using multiple logic gates

dynamic gate the inputs must be monotonically raising for the dynamic gate to
compute the correct function .To overcome this monotonicity problem Domino logic
was used.

Domino Logic was introduced to overcome the monotonicity problem faced

the Dynamic logic circuits. The monotonicity problem can be solved by placing a
static CMOS inverter between dynamic gates. This converts the monotonically falling
output into a monotonically rising signal suitable for the next gate
The name Domino comes from the behavior of a chain of the logic gates. It
runs 1.5-2 times faster than static logic circuits. It is simply a logic which permits
high-speed operation and enables the implementation of complex functions which
otherwise is not achieved by Static and Dynamic circuits.
Domino logic offers a simple technique to eliminate the need of complex
clocking scheme by utilizing a single phase clock and have no static power
consumption as it is removed by clock input in the first stage. These logic circuits are
glitch free, have fast switching threshold and possibility to cascade. The domino
Logic is as shown in the figure 4.3.

Figure: 4.3 Domino logic circuit

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Design and simulation of 2:1 mux using multiple logic gates

4.5 DUAL RAIL DOMINO LOGIC

Dual-Rail Domino a complete logic family in that it can compute all inverting
and non-inverting logic function which is a drawback in Domino Logic as it can
implement only inverting logic. However, it requires more area, wiring, and power.
The Dual-Rail Domino Logic is as shown in the figure 4.4.

Figure: 4.4 Dual rail domino circuit

4.6 LAYOUT OF LOGIC FAMILIES

In VLSI design, as processes become more and more complex, need for the
designer to understand the intricacies of the fabrication process and interpret the
relations between the different photo masks is really troublesome. Therefore, a set of
layout rules, also called design rules, has been defined. They act as an interface or
communication link between the circuit designer and the process engineer during the
manufacturing phase. The objective associated with layout rules is to obtain a
circuit with optimum yield (functional circuits versus non-functional circuits) in
as small as area possible without compromising reliability of the circuit.
Layout design is a schematic of the Integrated Circuit which describes the
exact placement of the components for fabrication.

4.7 CONCLUSION
In this chapter topics like STATIC CMOS LOGIC, PSEUDO NMOS LOGIC,
DUAL RAIL DOMINO LOGIC, DOMINO LOGIC are discussed.

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Design and simulation of 2:1 mux using multiple logic gates

CHAPTER 5
RESULTS AND DISCUSSIONS
5.1 INTRODUCTION
In this chapter all the test bench circuits and output waveforms related to the
project are discussed.
5.2 MULTIPLEXER
Multiplexer can be designed by
a. Static CMOS
b. Pseudo NMOS
c. Domino logic
d. Dual rail domino
5.2.1 STATIC CMOS
The information shown in the Figure 5.1 gives the information about static
CMOS test bench waveform. In this V(A) represents input a, V(B) represents input b,
V(S) represents the selection line s, V (O) represents the output of multiplexer. Two
inputs a and b are provided and based upon the selection line s the output will be
obtained.

Figure: 5.1 Test Bench OF Static CMOS circuit

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Design and simulation of 2:1 mux using multiple logic gates

Three inputs D0, D1 and selection line S are provided. When clock is low,
circuit is in Pre-charge phase, during the precharge phase (when clock= 0), the output
node of the pMOS stage is Pre charged to a high logic level, and the output of the
nMOS stage becomes low. When clock is high, circuit enters into the evaluation
phase and corresponding logic Function is performed in this phase. During the
evaluation phase, depending on the select lines S0 and S1, any one of the specified
operation is selected and corresponding output is obtained. If we consider s=0 and the
inputs D0=0 and D1=1 then the output generated will be 1 and if we consider s=1 and
the inputs D0=1 and D1=0 then the output generated will be 0.

Figure: 5.2 Waveforms of Static CMOS circuit

Table 5.1: Static CMOS Operations

S A B O

0 0 0 0

0 0 1 1

1 1 0 1

1 1 1 1

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Design and simulation of 2:1 mux using multiple logic gates

5.2.2 PUESDO NMOS

The information shown in the Figure 5.4 gives the information about pseudo
NMOS test bench waveform. In this V(A) represents input a, V(C) represents input b,
V(B) represents the selection line s, V(O) represents the output of multiplexer. Two
inputs a and b are provided and based upon the selection line s the output will be
obtained.
Three inputs D0, D1 and selection line S are provided. When clock is low,
circuit is in Pre-charge phase, during the precharge phase (when clock= 0), the output
node of the pMOS stage is Pre charged to a high logic level, and the output of the
nMOS stage becomes low. When clock is high, circuit enters into the evaluation
phase and corresponding logic Function is performed in this phase. During the
evaluation phase, depending on the select lines S0 and S1, any one of the specified
operation is selected and corresponding output is obtained. If we consider s=0 and the
inputs D0=0 and D1=0 then the output generated will be 0.

Figure: 5.3 Test Bench of Pseudo NMOS circuit

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Figure: 5.4 Waveforms of Pseudo NMOS circuit

5.2.3 DOMINO CIRCUIT

The information shown in the Figure 5.6 gives the information about domino
circuit test bench waveform. In this V(D0) represents input a, V(D1) represents input
b, V(S) represents the selection line s, V(O) represents the output of multiplexer. Two
inputs a and b are provided and based upon the selection line s the output will be
obtained.
Three inputs D0,D1 and selection line S are provided.When clock is low,
circuit is in Pre-charge phase, during the precharge phase (when clock= 0), the output
node of the pMOS stage is Pre charged to a high logic level, and the output of the
nMOS stage becomes low. When clock is high, circuit enters into the evaluation
phase and corresponding logic Function is performed in this phase. During the
evaluation phase, depending on the select lines S0 and S1, any one of the specified
operation is selected and corresponding output is obtained.If we consider s=0 and the
inputs D0=1 and D1=1 then the output generated will be 1.

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Figure: 5.5 Test Bench of Domino circuit

Figure: 5.6 Waveform of Domino circuit

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5.2.4 DUAL RAIL DOMINO

The information shown in the Figure 5.8 gives the information about dual rail
domino circuit test bench waveform. In this V(D0) represents input a, V(D1)
represents input b, V(S) represents the selection line s, V(O) represents the output of
multiplexer. Two inputs a and b are provided and based upon the selection line s the
output will be obtained.
Three inputs D0, D1 and selection line S are provided. When clock is low,
circuit is in Pre-charge phase, during the precharge phase (when clock= 0), the output
node of the pMOS stage is Pre charged to a high logic level, and the output of the
nMOS stage becomes low. When clock is high, circuit enters into the evaluation
phase and corresponding logic Function is performed in this phase. During the
evaluation phase, depending on the select lines S0 and S1, any one of the specified
operation is selected and corresponding output is obtained. If we consider s=0 and the
inputs D0=1 and D1=0 then the output generated will be 0.

Figure: 5.7 Test Bench of Dual rail domino circuit

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Figure: 5.8 Waveform of Dual rail domino circuit

5.3 COMPARISION TABLE

It is observed that the power dissipation and delay of the Domino circuit has
less power dissipation from Table 5.2.

Table 5.2: Comparison of power dissipation and delay

PARAMETERS POWER DISSIPATION DELAY

STATIC CMOS 185.958PW 11.801ns

PSEUDO NMOS 3.6249MW 20.952ns

DUAL RAIL 158.9970PW 5.3364ns

DOMINO

DOMINO 27.7564PW 232.90ps

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5.4 CONCLUSION
In this chapter introduction, simulation of multiplexer of multiple logic
families using 180nm technology, comparison table were discussed briefly.

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CHAPTER 6
CONCLUSION AND FUTURE SCOPE

6.1 CONCLUSION
A 2:1 MUX is implemented using various CMOS logic families and it’s
performance metrics are analyzed. It is clearly inferred that, 2:1 MUX designed using
domino logic is the most efficient design because the reduction in average power
consumption and PDP compared to all the other logic families and the propagation
delay is also lesser, but there are trade-off between Domino logic and Static CMOS
logic which can be neglected on considering the overall performance. Thus the overall
analysis proves that power and delay efficient MUX can be designed using the
domino logic which out performs all the other logic families. The significance of a
Multiplexer is that it can be used in Parallel to Serial convertor to reduce wide parallel
busses to serial signals in the field of Telecommunication, Data communication,
Satellite and Military applications. Therefore, based on all the performance analysis
made in this work it is proved that MUX designed using Domino logic can be used in
various applications to obtain better performance.
6.2 FUTURE SCOPE
The design analysis of various CMOS logic families is observed. We used
180nm technology for reducing power dissipation and delay, which can further be
reduced by designing using 90nm and 45nm technology.

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REFERENCES
[1] Neil H. E. Weste and David Money Harris, “CMOS VLSI Design A Circuits
and System Perspective”, Pearson Education (Asia) Pvt. Ltd.2000.
[2] M. Padmaja, V.N.V. Satya Prakash, “Design of multiplexer in multiple logic
styles for low power VLSI”, International Journal of Computer Trends and
Technology – volume 3 Issue 3 – 2012.
[3] Gurjeet Kaur, Gurmohan Singh, “Analysis of low power CMOS current
comparison domino logic circuits in ultra deep submicron technologies,”
International Journal of Computer Applications (0975 – 8887), February 2014,
Volume 88 – No.7.
[4] Priti Gupta , Rajesh Mehra, “Layout design and simulation of CMOS
multiplexer,” International Journal of Scientific Research Engineering
&Technology(IJSRET),14-15 March,2015
[5] Mohit Vyas, Soumya Kanti Manna, Shyam Akashe, “Design of Power
efficient MUX using dual gate FinFET technology,” IEEE Conference, 2016.

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APPENDIX
PROCEDURE FOR MENTOR GRAPHICS

Introduction
This document gives a rough overview of how to design & simulate things with
Mentor graphics Tools. There are eight basic steps:
1. Invoking Mentor Graphics
2. Creating Library & Cell
3. Creating Schematic
4. Generating Symbol
5. Creating Test bench
6. Simulating the Schematic
7. Waveform Comparison

1. Invoking Mentor Graphics

First of all we will open the linex os then the view will be Right click in the
linex window Desktop and click on open in terminal

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Type csh and press enter.

Type source /home/Softwares/cshrc/ams_2009.cshrc and press enter

Type da_ic& and press enter then pyxis project manager window will be invoked

as shown below.

Where the project navigator window is shown then click on the file To create a new
project click on File → new project which invokes the new project window as shown

Browse on the folder and specify the project path and the file name is user defined
and click on OK
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After libraries have to be added to the project. In order to add the technology files
browse on the folder
Browse the folder to
home/softwares/FOUNDRY/GDK/PYSIS_SPT_HEP/ic_reflibs/tech_libs and
Select the generic13 file click on OK.

Again click on OK then manage external/logic libraries window will pop up as

Shown. Click on the Add Standard Libra

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Then the libraries will be added up as shown below and click on OK

Then the pyxis project manager window will be shown where the technology libraries
are added to the project and are placed below the project name

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2. Creating Library & Cell:

To create a library right click on the project name and select new library Or click on
the icon on the icon bar

Then a new library window will pop up asking for the library name. Then name the
Library and click on OK.

To create a cell right click on the library and select new cell Or click on the icon on
the icon bar

Then a new cell window will pop up asking for the cell name. Then name the
Cell and click on OK.

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To create a schematic right click on the and select new schematic or click on the icon
on the icon bar

Then a new schematic window will pop up asking for the schematic name. Then name
the schematic and click on OK

Now name the schematic and click on OK which in turn leads to the pyxis schematic
editor window as shown

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3.Creating Schematic:
In this section you will become familiar with placing primitive analog devices
for an inverter.
You’ll learn how to:
• Place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• Route devices
• edit device parameter values
• Name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using Eldo
• view results.

From the left icon bar press on add instance icon

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Then a file browser which contains entire libraries will pop up as shown

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Next click on the double click on generic13 in the library list

And then follow the path to select pmos from $generic13/symbols/pmos as shown

Select the pmos and click on OK to place the pmos on the workspace as shown

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Then change the width and length of the pmos device can change by using object
Editor.

Select the nmos and click on OK to place the nmos on the workspace as shown

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Then change the width and length of the nmos device

To select the VDD and ground from the generic lib or click on the library in the layer
palatte window then layer palatte will be shown as ic library window. Then select
generic library and place VDD and ground

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After selecting the generic lib we use the VDD and ground to pick and place in the
required locations

Give the connects in between the VDD to pmos and ground to nmos and both pmos &
nmos gates and, source and drain of p & nmos devices
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Place in IN and OUT ports in a similar way as above from the generic library or click
on the add ports icon in the left icon bar and connect the circuit.

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To change the name, enter the name in the field given for the net name and press
enter. Then the schematic will be as shown.

After completing the inverter we have to save and check it.

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4.
4.Generating Symbol:
To generate a symbol select Add in the menu bar and then select generate
Symbol from pull down menu bar
Add→ generate symbol

A generate symbol will pop up as shown

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Then activates symbol, replace existing and choose shape and click on the customize
pin list and click on OK symbol will be generate.

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After that click on to chick and save

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The chick and save is an impotence to shown the result to an window which shows
the error report where the errors and warnings in the symbol can be seen

5. Creating Test bench:

To create a test bench close the pyxis schematic and symbol windows and go back to
pyxis project manager window. In the project manger window to create new cell right
click on the manual library below the project name and select new cell or select the

library and click on the icon in the icon bar.

Then a new cell window will pop up asking for the cell name in which give the cell
name and click OK Here the test bench cell name has been specified as inv_tb.

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Right click on the test bench cell and select new schematic which in turn opens pyxis
Schematic editor window.

Now instantiate the new inverter symbol by selecting Add > Instance from
the Left icon Palette or pressing the hot key i. Select the Symbol view of the inverter
cell from the inv cell of the manual library
Place the symbol on the work space as shown

• Add the IN and OUT net as before by selecting the hot key i. Name the nets with
hot key “q”.

• Add a DC voltage source dc_v_ source, from the MGC_IC_SOURCES_LIB.

Change the value of the DC property to be 1.2V. Add PULSE voltage source
pulse_v_source and change the value of the pulse_value property to be 1.2V change
also the delay to be 0S.
• Add Ground ports in a similar fashion. Finally the circuit looks like the following

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Next click on check/save icon in the icon bar

This will result to an window which shows the error report where the errors and
warnings in the symbol can be seen.

6. Simulating the Schematic:

After chick and save the schematic test bench then run simulation from this icon

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Then entering simulation mode window will be popup in that select New
Configuration

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In the New Configuration select SPICE Netlister and type sim in the configuration
name and click on OK

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Go for selecting AC, DC, TRAN then setup simulation window will be open

After appearing setup window select To set up analysis select analysis in the
simulation panel and in the analysis set up select the required analysis and set the
values of the analysis in the beside window as shown above
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Here I have selected the DC analysis with the start time as 0ns,stop time=5 ns and
print time step=0.1ns as shown . After specifying the values click on apply

Here I have selected the transient analysis with the stop time=1000ns After specifying
the values click on apply

Select the Edit Probes in the setup simulation panel

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Go back to the inverter schematic test bench and select the IN, OUT and come back
to the setup simulation

In the setup simulation window, set the analysis to both DC and Tran, and Task to
plot and type to voltage, click Add button then the port will be added to the waveform
as shown
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After adding the analysis, eldo models and probing waveforms minimize the setup

Simulation window and run the simulator. To run the simulation select
from the left icon palette or select simulate-> run simulation

7. Waveform comparison

View the simulation results by selecting the plot results from latest run icon from the
left icon palatte. This will open EZ Wave for you with the output waveforms. This is
how the waveforms look like after zooming

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EZ wave 12.1 production window popup to the view of waveform for IN & OUT

Click on Measurement tool in the icon bar which opens up the

measurement tool window where we can measure the different properties of your
waveforms

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Save these waveforms as an idle.

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