Microprocessors and Microcontrollers/ Multiple Choice Questions

Architecture of Microprocessors

1. Which interrupt has the highest priority?

a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data
bus. c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trap b) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
a) Yes b) No c) sometimes yes, sometimes no
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set

M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1

Microprocessors and Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors

d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H

Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B
Microprocessors and Microcontrollers/Assembly language of 8086 Multiple Choice Questions

1. The contents of different registers are given below. Form Effective addresses for
different addressing modes are as follow :
Offset = 5000H
[AX]- 1000H, [BX]- 2000H, [SI]- 3000H, [DI]- 4000H, [BP]- 5000H,
[SP]- 6000H, [CS]- 0000H, [DS]- 1000H, [SS]- 2000H, [IP]- 7000H.
I. MOV AX, [5000H]
a) 5000Hb) 15000H c) 10500H
II. MOV AX, [BX] [SI]
a) 13000H b) 15000H c) 12000H
III. MOV AX, 5000H [BX] [SI]
a) 20000H b) 1A000H c) 1A00H
2. The conditional branch instruction JNS performs the operations when if __
a) ZF =0 b) SF=0 c) PF=0 d) CF=0
3. Vector address of TRAP
a) 24H b) 36H c) 24 d) 18H
4. SOD pin can drive a D flip-flop?
a) SOD cannot drive any flip-flops.
b) SOD cannot drive D flip-flop, but can drive any other flop-
flops. c) Yes, SOD can drive D flop-flop.
d) No, SOD cannot drive any other flop-flops except D flop-flop.
5. IDIV and DIV instructions perform the same operations for?
a) Unsigned number b) Signed number c) Signed number & Unsigned number d)
none of above.
6. What is the output of the following code
AL=88 BCD, CL=49 BCD
ADD AL, CL
DAA
a) D7, CF=1 b) 37, CF=1 c) 73, CF=1 d) 7D, CF=1
7. What is the output of the following code
AL= 49 BCD, BH= 72 BCD
SUB AL, BH
DAS
a) AL=D7, CF=1. b) AL=7D, CF=1. c) AL=77, CF=1 d) none of them.
8. What is the output of the following code
AL= -28 decimal, BL=59 decimal
IMUL BL
AX=? , MSB=?
a) AX= F98CH, MSB=1. b) AX= 1652, MSB=1. c) BX F9C8H, MSB=1. d)
BX= 1652, MSB=1.
9. What is the output of the following code
AL= 00110100 BL= 00111000
ADD AL, BL
AAA
a) AL = 6CH b) 12H c) 12 d) C6H
10. What is the output of the following
code AL=00110101 BL= 39H
Microprocessors and Microcontrollers/Assembly language of 8086 Multiple Choice Questions

SUB AL, BL
AAS
a) AL= 00000100, CF=1 b) BL=00000100, CF=0 c) AL=11111100 CF=1 d)
BL= 00000100, CF=1
11. What is the output of the following code
CF =0, BH = 179
RCL BH, 1
a) CF=0, OF= 1, BH= 01100101 b) CF=1, OF=1, BH=01100110
c) CF=1, OF =0, BH= 01001101 d) CF=0, OF=0, BH=00101100
12. What is the output of the following code
SI=10010011 10101101, CF=0
SHR SI, 1
a) 37805, CF=1, OF=1 b) 18902, CF=1, OF=1
c) 19820, CF=1, OF=1 c) 53708, CF=1, OF=1
13. What is the output of the following code
BX=23763CL=8
ROL BX, CL
a) 0101110011010011, CF=0 b) 1101001101011100, CF=0
c) 0110100010011101, CF=1 c) 1011100110001100, CF=1
14. What is the output of the following
code PUSH AL
a) Decrement SP by 2 & push a word to
stack b) Increment SP by 2 & push a
word to stack c) Decrement SP by 2 &
push a AL to stack d) Illegal
15. What is the output of the following code
AX = 37D7H, BH = 151 decimal
DIV BH
a) AL = 65H, AH= 94 decimal
b) AL= 5EH, AH= 101 decimal
c) AH= E5H, AL= 5EH
d) AL= 56H, AH= 5EH
16. In 8086 microprocessor one of the following instructions is executed
before an arithmetic operation
a) AAM b) AAD c) DAS d) DAA

Key:
2.1 (I) B (II) C (III) B 2.2 B 2.3 A 2.4 C 2.5 B
2.6 B 2.7 C 2.8 A 2.9 C 2.10 A 2.11 B
2.12 B 2.13 B 2.14 D 2.15 B 2.16 B
Microprocessors and Microcontrollers/Interfacing with 8086 Multiple Choice Questions

1. Access time is faster for

a) ROM b) SRAM c) DRAM
2. In 8279 Strobed input mode, the control line goes low. The data on return lines
is strobed in the ____.
a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte
d) LILO byte by byte.
3. ___ bit in ICW1 indicates whether the 8259A is cascade mode or not?
a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
4. In 8255, under the I/O mode of operation we have __ modes. Under which mode
will have the following features
i) A 5 bit control port is available.
ii) Three I/O lines are available at Port C.
a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
5. In ADC 0808 if _______ pin high enables output.
a) EOC b) I/P0-I/P7 c) SOC d) OE
6. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line
goes ____ to interrupt the CPU.
a) CS, high b) A0, high c) IRQ, high d) STB, high
7. In 8279 Status Word, data is read when ________ pins are low, and write to the
display RAM with ____________ are low.
a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD
c) A0, RD & WR, CS d) CS, RD & A0, CS.
8. In 8279, the keyboard entries are debounced and stored in an _________, that
is further accessed by the CPU to read the key codes.
a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
9. The 8279 normally provides a maximum of _____ seven segment
display interface with CPU.
a) 8 b) 16 c) 32 d) 18
10. For the most Static RAM the write pulse width should be at least
a) 10ns b) 60ns c) 300ns d) 1µs
11. BURST refresh in DRAM is also called as
a) Concentrated refresh b) distributed refresh c) Hidden refresh d) none
12. For the most Static RAM the maximum access time is about
a) 1ns b) 10ns c) 100ns d) 1µs
13. Which of the following statements on DRAM are correct?
i) Page mode read operation is faster than RAS read.
ii) RAS input remains active during column address strobe.
iii) The row and column addresses are strobed into the internal buffers using RAS
and CAS inputs respectively.
a) i & iii b) i & ii c) all d) iii
14. 8086 microprocessor is interfaced to 8253 a programmable interval timer. The
maximum number by which the clock frequency on one of the timers is
divided by
16 8 10 20
a) 2 b) 2 c) 2 d) 2
Microprocessors and Microcontrollers/Interfacing with 8086 Multiple Choice Questions

15. 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s

are in master slave configuration the number of interrupts available to the 8086
microprocessor is
a) 8 b) 16 c) 15 d) 64

Key:
3.1 B 3.2 A 3.3 C 3.4 B 3.5 D 3.6 C
3.7 A 3.8 B 3.9 B 3.10 B 3.11 A
3.12 C 3.13 C 3.14 A 3.15 D
Microprocessors and Microcontrollers/Coprocessor Multiple Choice Questions

1. The coprocessors operate in ______ with a processor on the same buses and with
the same instruction _______.
a) Parallel, byte stream. b) Series, byte stream.
c) Series, bite stream d) Parallel, bite stream.
2. Why 8087 is referred to as Coprocessor?
i) Because 8087 is used in parallel with main processor in a system, rather than
serving as a main processor itself.
ii) Because 8087 is used in serial with main processor in a system, rather than
serving as a main processor itself.
iii) Because main Microprocessor handles the general program execution and
the 8087 handles specialized math computations.
a) i & iii b) ii & iii c) iii only. d) i only.
3. 8087 connection to 8086, to enable the _________ bank of memory _______pins
are to be connected.
a) Lower, BHE b) Upper, BHE c) Lower, INT
d) Upper, INT.
4. ___ Connection and the _______ instruction will solve the problem
of synchronization between processor and coprocessor.
a) INT & NMI, WAIT b) RQ/GT0 & RQ/GT1, FWAIT
c) BUSY & TEST, FWAIT d) S0 & QS0, WAIT
5. _______ input is available, so that another coprocessor can be connected and
function in _________ with the 8087. .
a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel
d) S0 & S1, parallel.
6. In 8087, _______ many register stack are there? And of _____ registers.
These registers are used as _________ stack.
a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.
7. If ______ and ________ connections are made so that an error condition in
8087 can interrupt to the processor.
a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1
8. In 8087, which instruction is used for division real reversed______.
a) FDIV b) FIDIVR c) FDIVR d) FDIVRP
9. Which of the following is of compare instruction in 8087?
a) FTST b) FPREM c) FPATAN d) FLDI
10. In 8087 coprocessor one of the following instructions is not valid
a. FSIN
b. FPTAN
c. FIDIV
d. FSQRT
11. One of the following signals belongs to the 8087 coprocessor is
a. HOLD
b. BUSY
c. TEST
d. NMI
Key:
4.1 A 4.2 A 4.3 B 4.4 A 4.5 B 4.6 C
4.7 C 4.8 C 4.9 A 4.10 A 4.11 C