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VLSI Verification Engineer Resume

Jeffrey has over 2 years of experience in ASIC verification. He has expertise in protocols like Ethernet and SATA and skills in Verilog, SystemVerilog, and the UVM methodology. He has experience building verification environments from scratch and writing test cases. Some of his projects include verifying SATA PHY, Ethernet 400G PCS, and Ethernet 10G PCS. He developed verification plans, testbenches, and coded test cases to verify various functionalities.

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4K views2 pages

VLSI Verification Engineer Resume

Jeffrey has over 2 years of experience in ASIC verification. He has expertise in protocols like Ethernet and SATA and skills in Verilog, SystemVerilog, and the UVM methodology. He has experience building verification environments from scratch and writing test cases. Some of his projects include verifying SATA PHY, Ethernet 400G PCS, and Ethernet 10G PCS. He developed verification plans, testbenches, and coded test cases to verify various functionalities.

Uploaded by

vjemman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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J JEFFREY

+91 7022250032
[email protected]

PROFESSIONAL SUMMARY:

• 2.10 Years of experience in ASIC Verification.


• Good knowledge on protocols such as SATA, Ethernet.
• Experience in building verification environment from scratch using Verilog, System Verilog and
UVM methodology.
• Hands-on experience in Test Plan & Test Bench development in UVM environment.
• Proficient in writing test cases, simulation and debugging.

TECHNICAL SKILLS:

• Protocol : Ethernet, SATA, SPI


• HDL : Verilog, System Verilog
• Tools : VCS, Questa-sim, Nc-Verilog
• Methodology : UVM

PROFESSIONAL EXPERIENCE:

• Working as ASIC Verification Engineer with Moschip Semiconductors from May 2017 to
present.
• Worked as ASIC Verification Engineer with Orange Semiconductors Pvt.Ltd from Aug 2016 to
April 2017.

PROJECTS:

1.SATA PHY:

Verified SATA PHY by developing and implementing Verification IP in UVM environment and testing
various functionality of SATA using Nc-Verilog.
• Developed Verification plan including test plan and coverage plan.
• Prepared and executed verification test plans for different Pipe Widths and different Gen
speeds.
• Developed clocking component to generate all clock rates required by SATA PHY.
• Assisted in development of constraint random verification environment with functional
coverage.
• Coded testcases using UVM methodology to test various functionality and scenarios of SATA
PHY.
• Filed bug reports and verified RTL fixes, analysed regression results and performed coverage
analysis using IMC.
• Debugged RTL using simulators like Nc-Verilog, Simvision, IMC.
2.Thunderbird FM2 verification:

Verified various IP’s under SOC level and developed test patterns for IP level using Nc-Verilog and
SI_DEBUG.

• Development of UDS file as per the test plan.


• Generated test patterns from UDS and verified multiple IP’s within SOC.
• Filed bug reports and verified RTL fixes.
• To simulate and debug the testcases and stabilizing the RTL.

3.Ethernet 400G PCS:

Development of verification plan and testcases to verify various functionalities of Ethernet 400G PHY
PCS in UVM environment.

• Developed verification plan.


• Implemented and verified 64b/66b encoder.
• Coded testcases using UVM methodology to verify various functionality.
• Debugged the failed testcases and reported RTL bugs.

4.Ethernet 10G PCS:

Development of verification plan and UVM based testcases to verify various functionalities of Ethernet
10G PCS in UVM environment.

• Developed testcases and sequence collections in UVM environment.


• Responsible for regression and reporting bugs.

ACADEMIC QUALIFICATION:

• Master of Technology in VLSI Design from SRM University with 65% in 2015.
• Bachelor of Technology in Electronics & Communication from Sathyabama University with
67% in 2012.

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