Eel 4309

LABORATORY MANUAL
DEPARTMENT OF
ELECTRICAL & COMPUTER ENGINEERING
UNIVERSITY OF CENTRAL FLORIDA
EEL 4309
Electronics II
Revised
May 2018
Table of Contents
Safety: Safety Rules and Operating Procedures
Introduction: When in Doubt, Read This
Experiment #1: Linear Operational Amplifier Applications - 2.5 Wks
Experiment #2: More Linear Operational Amplifier Applications - 2.5Wks
Experiment #3: Linear Voltage Regulators - 1 Wk
Experiment #4: Switching Voltage Regulators - 1 Wk
Experiment #5: Precision Diodes and Applications - 1 Wk
Experiment #6: Active Filters - 2 Wks
Experiment #7: Voltage Comparators and Schmitt Triggers - 1 Wk
Experiment #8: Oscillators and Waveform Generators – 1 -Wk
Experiment #9: The 555 Timer 1 - Wk
Appendices
Appendix A: Available Resistors and Capacitors
ToC- 1
Safety Rules and Operating Procedures
1. Note the location of the Emergency Disconnect (red button near the door) to shut off power
in an emergency. Note the location of the nearest telephone (map on bulletin board).
2. Students are allowed in the laboratory only when the instructor is present.
3. Open drinks and food are not allowed near the lab benches.
4. Report any broken equipment or defective parts to the lab instructor. Do not open, remove
the cover, or attempt to repair any equipment.
5. When the lab exercise is over, all instruments, except computers, must be turned off.
Return substitution boxes to the designated location. Your lab grade will be affected if your
laboratory station is not tidy when you leave.
6. University property must not be taken from the laboratory.
7. Do not move instruments from one lab station to another lab station.
8. Do not tamper with or remove security straps, locks, or other security devices. Do not disable
or attempt to defeat the security camera.
9. When touching the FPGA development boards please do not touch the solid-state parts on the
board but handle the board from its edge.
10. ANYONE VIOLATING ANY RULES OR REGULATIONS MAY BE DENIED

ACCESS TO THESE FACILITIES.
I have read and understand these rules and procedures. I agree to abide by these rules and
procedures at all times while using these facilities. I understand that failure to follow these rules
and procedures will result in my immediate dismissal from the laboratory and additional
disciplinary action may be taken.
________________________________________ ________________
Signature Date Lab #
i
Laboratory Safety Information
Introduction
The danger of injury or death from electrical shock, fire, or explosion is present while
conducting experiments in this laboratory. To work safely, it is important that you understand the
prudent practices necessary to minimize the risks and what to do if there is an accident.
Electrical Shock
Avoid contact with conductors in energized electrical circuits. The typical cannot let-go (the
current in which a person cannot let go) current is about 6-30 ma (OSHA). Muscle contractions
can prevent the person from moving away the energized circuit. Possible death can occur as low
50 ma. For a person that is wet the body resistance can be as low as 1000 ohms. A voltage of 50
volts can result in death.
Do not touch someone who is being shocked while still in contact with the electrical conductor
or you may also be electrocuted. Instead, press the Emergency Disconnect (red button located
near the door to the laboratory). This shuts off all power, except the lights.
Make sure your hands are dry. The resistance of dry, unbroken skin is relatively high and thus
reduces the risk of shock. Skin that is broken, wet, or damp with sweat has a low resistance.
When working with an energized circuit, work with only your right hand, keeping your left hand
away from all conductive material. This reduces the likelihood of an accident that results in
current passing through your heart.
Be cautious of rings, watches, and necklaces (which increase the conductivity and contact area).
Skin beneath a ring or watch is damp, lowering the skin resistance. Shoes covering the feet are
much safer than sandals.
If the victim isn’t breathing, find someone certified in CPR. Be quick! Some of the staff in the
Department Office are certified in CPR. If the victim is unconscious or needs an ambulance, call
911. If able, the victim should go to the Student Health Services for examination and treatment.
Fire
Transistors and other components can become extremely hot and cause severe burns if touched.
If resistors or other components on your proto-board catch fire, turn off the power supply and
notify the instructor. If electronic instruments catch fire, press the Emergency Disconnect (red
button). These small electrical fires extinguish quickly after the power is shut off. Avoid using
fire extinguishers on electronic instruments.
Explosions
When using electrolytic / tantalum capacitors, be careful to observe proper polarity and do not
exceed the voltage rating. Electrolytic and tantalum capacitors can explode and cause injury. A
first aid kit is located on the wall near the door. Proceed to Student Health Services, if needed.
ii
Introduction
When in Doubt, Read This
Laboratory Requirements:
This laboratory requires that each student obtain a copy of this manual, a bound quad-
ruled engineering notebook and have access to a Spice simulation program such as
Multisim, Workbench or LTSpice.
The student is to prepare for each laboratory by reading the assigned topics. The
laboratory notebook should contain the necessary tables, graphs, logic and pin
assignment diagrams and identify the expected results from the laboratory exercise as
directed by the pre-laboratory preparation assignments or by the laboratory instructor.
Depending on the laboratory assignment, the pre-laboratory preparation may be due at
the beginning of the laboratory period or may be completed during the assigned
laboratory period. Be advised that during each laboratory period the instructor will grade
your laboratory notebook preparation.
During the laboratory period you are expected to construct and complete each laboratory
assignment, record data, and deviations from your expected results, equipment used,
laboratory partners, and design changes in your laboratory notebook. A laboratory
performance grade will be assigned by the laboratory instructor upon successful
completion of the above-described tasks for each experiment.
Each student will be assigned to a team and is expected to be a contributing member of

that team. It is expected that each member will alternate the lead of the laboratory
experiments. A Laboratory Report, following the guidelines presented in this handout is
due the laboratory period following the completion of the in-laboratory work or when the
instructor designates. A numeric grade will be assigned to each of the laboratory
experiments.
Laboratory reports will be due before the start of the following laboratory period. A
penalty of ten points will be charged for those late by up to one week (0-7 days). No
credit will be given for laboratory reports over-due by more than one week. However, a
student must complete each assigned experiment in order to complete the laboratory. By
not turning in a laboratory report, a student will receive a zero for that report, which
results in a zero for the laboratory grade.
For university approved activities, students who miss the laboratory lecture should make
arrangements to make up the laboratory at a later time. Otherwise there is no makeup
laboratory allowed. Students who are late to their laboratory section may not receive the
pre-laboratory points.
Intro- 1
Laboratory Points Breakdown
Pre-Laboratory Grade (20 points):

1. Pre-Laboratory Assignment.............................................................……..… 10 points
2. Circuit Design and Simulation ..................................................................… 10 points
Laboratory Performance (30 points):

3. Laboratory Notebook (accuracy, completeness, usefulness, etc., ability
to duplicate experiments from notes, etc.) ….……………………..………. 10 points
4. Lab comportment (professionalism, respect for others, timeliness,
safety, etc.) ………………………………………………………………… 10 points
5. Lab Participation (group effort and cooperation, time management,
planning, leadership, etc.) ………………………………………………..... 10 points
Laboratory Report Grade (50 points):

6. Problem or Objective Statement, Schematic, and Apparatus List.………… 7 points
7. Design / Procedural Steps......................….......….………………………… 12 points
8. Data Collected (Multimeter values Oscillocope values).......................…… 12 points
9. Plots Generated ………….………………………………………………… 6 points
10. Comparisons……………………………………………………………….. 6 points
11. Summary and Conclusions................................................................…….… 7 points
TOTAL.........................................................................................……….....…100 points
The final laboratory grade can be a percentage, or a failing grade. If the student receives a
failing grade for the laboratory, a failing grade may be assigned for the whole course.
Guidelines for Laboratory Reports:

The laboratory report is the record of all work pertaining to the experiment, which
includes any pre-laboratory assignments, schematic diagrams, and Xilinx's ISE printouts
when applicable. This record should be sufficiently complete so that you or anyone else
of similar technical background can duplicate the experiment by simply following your
laboratory report. Original work is required by all students (NO PHOTOCOPIES
OR DUPLICATE PRINTOUTS). Your laboratory report is a team effort and should be
unique. It is expected that each student contribute equally to the writing of the report.
The laboratory notebook must be used for recording data. Do not trust your memory to
fill in the details at a later time. An engineer will spend 75 percent of his/her time for
documentation.
Organization in your report is important. It should be presented in chronological order

with descriptive headings to separate and identify the various parts of the experiment. A
neat, organized and complete record of the experiment is just as important as the
experimental work.
Intro- 2
The following are general guidelines for your use. Use the standard paper prescribed by
your instructor. A cover page is required for each laboratory including your name, PID,
name and number of the experiment, date of the experiment and the date the report is
submitted. Complete the required information and attach to the front of each report. If a
cover page is not included with a report, then points may be taken off.
The report should contain the following (not segmented or necessarily in this order):
• Heading: The experiment number, your name, and date should be at the top right
hand side of each page.
• Objective: A brief but complete statement of what you intend to design or verify
in the experiment should be at the beginning of each experiment.
• Schematic: A schematic of the circuit under test and the test equipment should be
drawn and labeled so that the actual experiment circuitry could be easily
duplicated at any time in the future.
• Apparatus List: List the items of equipment, including IC devices, with
identification numbers using the UCF label tag, make, and model of the
equipment. It may be necessary later to locate specific items of equipment for
rechecks if discrepancies develop in the results. Also include the computer used
and the version number of any software used.
• Procedures and/or Design Methodology: In general, lengthy explanations are
unnecessary. Be brief. Keep in mind the fact that the experiment must be
reproducible from the information given in your report. Include the steps taken in
the design of the circuit: any equations used and any assumptions made.
• Data Collected: A detailed discussion of the data collected, how it was collected,
any issues with the data being collected and what equipment was used to collect
this data. Which data is to be collected will be given in the procedural steps of the
laboratory experiment. All oscilloscope patterns along with any values measured
with a multimeter should be included in the report. All oscilloscope images
should be limited in size to no wider than two inches, each. Only essential images
should be included, that mark the essence and success (or failure) of the
experiment. (Note that much of what comes in oscilloscope images can be
collected as data and put in graphs as required by many of the procedural steps in
the various laboratory experiments.)
• Plots Generated: All plots that are required for the experiment should be
included with the laboratory report. These plots should be computer generated
using a computer program that plots raw X, Y data. When comparing different
sets of data using graphical methods this should be done using the same plot not
several plots.
• Comparisons: Comparison means to compare two sets of data. For engineers
this means a quantitative value not a qualitative discussion. A simple percentage
Intro- 3
difference between two values is all that is needed. All comparisons should be
included in the report, both the equations used and the values calculated. The
results should be presented in a form that makes the interpretation easy. Large
amounts of numerical data are generally presented in a graphical form. Tables are
generally used for a small amount of data. Theoretical and experimental data
should be on the same graph or arranged in the same table for easy correlation.
• Conclusion: This is your interpretation of the objectives, procedures and results
of the experiment, which will be used as a statement of what you learned by
performing the experiment. This is not a summary. Be brief and specific, but
complete. Identify the advantages and/or disadvantages of your solution in
design-oriented experiments. The conclusion also includes the answers to the
questions presented in each experiment.
Intro- 4
EXPERIMENT #1
Linear Operational Amplifier Applications
Goals:
To introduce the concepts of an operational amplifier (op-amp) used as a non-inverting
amplifier, inverting amplifier, unity gain buffer and a summing amplifier. Data collected
during this laboratory experiment will be compared to the datasheet of the operational
amplifier used.
References:
The following two links are to the Tektronix website for the user manuals for the
DPO 4034B Mixed Signal oscilloscope and for the AFG3022B Arbitrary Function
generator:
Oscilloscope:
http://www.tek.com/search/apachesolr_search/DPO%204034B%20user%20manu
al
Arbitrary Function Generator:

http://www.tek.com/search/apachesolr_search/afg3022b?filters=tid%3A1016
Please note, to download the user manual, Tektronix requires that you fill out the
user information form before downloading can begin.
Equipment:
Oscilloscope: DPO 4034B Mixed Signal
Function Generator: AFG3022B
Triple Power supply
Breadboard
TL081-TL084 family of operational amplifiers
Capacitors available in the laboratory
Resistors available in the laboratory
Pre-laboratory:
Read this laboratory experiment carefully to become familiar with the background
procedural steps in this experiment. Download the two user manuals for the
Tektronix function generator and oscilloscope and become familiar with their use.
Using the simulation package of your choice in which you are the most familiar
with: Multisim, Workbench or LTSpice IV simulate the following circuits. If you
do not have access to Multisim or Workbench, LTSpice IV is a free to use spice
1- 1
program available from Linear Technology Inc. and can be downloaded from the
following site: http://www.linear.com/designtools/software/#LTspice
The only disadvantage is the part library is for only Linear Technology parts. They
do offer a universal operational amplifier (UniversalOpamp2) that can be used for
many of the simulations required for EEL4309 laboratory experiments.
The equations required for gain Av are given in the appropriate sections for the
non-inverting amplifier, inverting amplifier, unity gain buffer and the summing
amplifier.
a. Design a gain Av of 3 non-inverting amplifier using a minimum of 1k-ohm

resistors.
b. Simulate this non-inverting amplifier generating the time transient response for
a 1.0 volt, 200 Hz sine wave input. Plot the input as well as the output voltages
as a function of time.
c. Repeat steps a and b for a gain of 10.
d. Design a gain Av = -3 inverting amplifier using a minimum of 1k-ohm resistors.
e. Simulate this inverting amplifier generating the time transient response for a
1.0 volt 200 Hz sine wave input. Plot the input as well as the output voltages
f. Repeat step d and e for a gain of Av = -10.
g. Compare the results of steps b with e and c with f.
h. Simulate a unity gain buffer amplifier generating the time transient response for
a 1.0 volt 200 Hz sine wave input. Plot the input as well as the output voltages
i. Design a summing amplifier such that
Vout = -3V1 - 2V2 ,
where V1 and V2 are input sources and Vout is the output from the summing
amplifier.
j. Simulate this summing amplifier generating the time transient response for a
1.0 volt, 200 Hz sine wave input for V1 and a 2 volt DC input for V2 (V2 = a
constant value of 2 volts). Plot the input as well as the output voltages as a
function of time.
Discussion:
An operational amplifier (op-amp) is a multistage amplifier, where its output is
proportional to the difference between the two inputs:
Vout = Aod(V+ - V-) (1)
The schematic symbol for an op-amp is a triangle with the two inputs V+ and V-
and the one output Vout as shown in Figure 1. Most op-amps need two power
supplies; one with a positive voltage +Vcc and one with a negative voltage -Vcc.
1- 2
I - +Vcc
V+ Vout
V-
I+ -Vcc
Figure 1: A Schematic diagram of a typical op-amp.
There are several important facts about op-amps. First the output Vout is bounded
between the two powers supply voltages:
-Vcc ≤ Vout ≤ + Vcc (2)
If the output voltage is allowed to go to exactly -Vcc to +Vcc this op-amp is referred
to as an op-amp with a rail-to-rail output. Rewriting Equation (1) gives the
following:
Vout
(V+ - V-) = Aod (3)
For most common op-amps, the gain of the op-amp Aod is about 106. Since Vout
is bound by Equation (2) to be within the power supply values which is typically
less than +/- 15 volts, by Equation (3), (V+ - V-) is limited to about +/- 15
microvolts. Essentially, V+ = V-. Finally, the last import fact is the current flowing
into the positive V+ input and the negative V- input is very small and for most
applications can be considered zero (I+ = I- = 0). Since V+ = V- and I+ = I- = 0,
this condition is called a virtual short.
Inverting Amplifier:
Figure 2 gives the schematic diagram for an inverting amplifier. A close look at
Figure 2 shows that the op-amp power supply contains both +Vcc and -Vcc, which
have been set to +15 and -15 volts, respectively. Also each of the power supply
inputs has a capacitor. This capacitor can range in size from about 0.01 microfarad
to about 10 microfarad. For this lab and the other labs for this course, these two
capacitors should be 10 microfarad, 35 volts, available in the lab parts cabinet. In
addition, both of these capacitors should be placed as close as possible to the + and
- power supply pins of the op-amp (see data sheet for actual pin numbers). These
capacitors are used to prevent any noise from being coupled into the op-amp power
supply pins and to prevent any positive feedback that may make the op-amp
oscillate.
1- 3
IR2 IR1
Figure 2: The schematic for an inverting amplifier.
The voltage gain for an inverting amplifier is given as:
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 𝑅𝑅2
𝐴𝐴𝐴𝐴 = =− (4)
𝑉𝑉𝑉𝑉𝑉𝑉 𝑅𝑅1
Equation 4 includes a negative sign. This negative sign introduces a 180° phase
shift in the output voltage relative to the input voltage. Assuming R1 is a 5k ohm
resistor and R2 is a 1k ohm resistor, and Vin is +/- 1 volt triangle input, then Av
would be -5 and Vout would be +/- 5volts triangle wave that is 180° out of phase
compared to the input as shown in Figure 3. Note how the output signal is 5 times
larger than the input signal. For the special case, when R2 = R1 Vout =-Vin a 180°
phase shifted version of the input.
Vin
+1v
-1v time
+5v
Vout
time
-5v
Figure 3: The output for a -5 gain, inverting amplifier with a +/- 1 volt triangle
wave input.
1- 4
The interesting item about the inverting amplifier is that the gain is only a function
of the ratio of the two resistors of R1 and R2. Typical values of resistors used in
op-amp circuits usually are in the range of 1k ohms to 10 mega ohms.
Given that there is a virtual short between the two inputs of the op-amp V- = V+ =
0 volts and the current into both input terminals is zero, the current flowing in R1
is the same as the current flowing in R2:
Vin - 0v Vin 0v - Vout -Vout

IR1 = IR2 = R2 = R2 = R1 = R1 (5)
The bandwidth of an inverting amplifier depends on the size of the signal on Vout
and broken into two categories of small signal and large signal. The two equations
that give the -3dB frequency (the frequency in which the magnitude of the voltage
gain is reduced by 0.707 from its value given in Equation (4)) are
Gain-Bandwidth-Product
(small signal) f-3dB = R1 (6)
R2 + 1
Slew-Rate
(large signal) f-3dB = (7)
R1 
2πR2 + 1Vin(peak)
 
Vin
+1v
time
-1v
+5v
Vout
time
Slew-Rate
-5v Limit
Figure 4: Vout for a square wave input showing the affect of slew-rate limit.
Actual bandwidth of the inverting amplifier is then the smaller of Equations (6) and
(7). The Gain-Bandwidth-Product of an op-amp can be found in its datasheet and
it’s the frequency when Aod of the op-amp is equal to one. The slew-rate is the
maximum rate of change of the output Vout given in volts per second and is also
given in the op-amp data sheet. Figure 4 illustrates the effect of a finite slew- rate
1- 5
on a square wave input for an inverting amplifier with a gain of -5. Also in Equation
(7), Vin (peak) is the maximum peak input voltage.Equation (6) best describes the
bandwidth of the inverting amplifier when the output voltage swing is small and
Equation (7) best describes the bandwidth when the output voltage swing is large.
It should be noted that in the denominator of Equation (7) that
R1 
R2 + 1Vin(peak) (8)
 
is nothing more than the peak output voltage.
The last item of interest for the inverting amplifier is the maximum voltage swing
that can be achieved by the op-amp. For no load on the op-amp, the op-amp
maximum and minimum voltage swing is given by its datasheet. As mentioned
before, if the op-amp's maximum and minimum voltage swing are equal to +Vcc to
-Vcc then this op-amp is referred to as a rail-to-rail output op-amp. Another factor
that limits the maximum output voltage swing is the amount of current that the op-
amp output can deliver. Usually, as the load current increases, the maximum output
voltage swing decreases. This again is usually given in the op-amp's datasheet. In
fact, most op-amps have a maximum output current limit that is set so as to protect
the op-amp should its output be accidentally shorted to ground. Most op-amps have
internal projection. But what will destroy an op-amp is the accidentally applying
the wrong polarity power on +Vcc and -Vcc. Care must be taken to prevent
accidentally reversing the op-amp's power supply.
IR2 IR1
Figure 5: The schematic for a non-inverting amplifier.
Non-inverting Amplifier:
Figure 5 gives the schematic diagram for a non-inverting amplifier. Note how the
input is now on the V+ terminal of the op-amp where for the inverting amplifier the
1- 6
V+ was grounded. For the non-inverting amplifier is should be noted that ground
does not get directly tied to the op-amp but is tied to one side of R2.
The gain Av for a non-inverting amplifier is given by:
Vout R1
Av = Vin = R2 + 1 (9)
In comparing Equation (9) to Equation (4), there is no minus sign indicating that
the phase shift for a non-inverting amplifier is 0°. Setting R1 = 4 .R2, gives a gain
Av of 5 and is shown in Figure 6 for a triangle wave input.
Vin
+1v
-1v time
+5v
Vout
time
-5v
Figure 6: The output for a +5 gain non-inverting amplifier with a +/- 1 volt
triangle wave input.
Given that there is a virtual short between the two inputs of the op-amp V- = V+ =
Vin and the current into both input terminals is zero, the current flowing in R1 is
the same as the current flowing in R2:
Vin - 0v Vin Vout - Vin

IR1 = IR2 = R2 = R2 = R1 (10)
The bandwidth of a non-inverting amplifier depends on the size of the signal on

Vout, is broken into two categories of small signal and large signal, is the same as
for an inverting amplifier and is given by Equations (6) and (7). These are the two
equations that give the -3dB frequency (the frequency in which the magnitude of
the voltage gain is reduced by 0.707 from its value given in Equation (9)). The
actual bandwidth of a non-inverting amplifier is then the smaller of Equations (6)
and (7).
1- 7
Figure 7 illustrates the effect of a finite slew-rate on a square wave input for a non-
inverting amplifier with a gain of +5. Like the inverting amplifier, the maximum
voltage swing that can be achieved at the output depends on the maximum output
current that can be delivered by the op amp.
Vin
+1v
time
-1v
+5v
Vout
Slew-Rate time
Limit
-5v
Figure 7: Vout for a square wave input showing the affect of slew-rate limit for a
non-inverting amplifier with a gain of +5.
Figure 8: shows VOS place in series with the input signal Vin.
Consider the non-inverting amplifier of Figure 5. According to Equation (9), when

Vin =0 volts, Vout should also be zero volts. But for a real op-amp, this is not the
case; Vout is non-zero. This non-zero output voltage is the result of mis-matches
in the internal amplifiers of the op-amp. Given this non-zero output voltage Vx,
then it’s effectively a voltage source commonly called the offset voltage (VOS) at
the input given by
1- 8
Vx
VOS = R1 (11)
R2 +1
Figure 8 shows this voltage source VOS place in series with the input signal Vin.
Unity Gain Buffer or Voltage Follower
Equation (9) gives the voltage gain Av for the non-inverting amplifier. If R1 is set
to 0 and R2 is set to infinity then Av reduces to 1. But R1 = 0 is the same as a wire
and R2 equal to infinity is nothing more than an open. Figure 9 gives the schematic
for a unity gain buffer. For this circuit Vout = Vin. Care must be taken when
picking an op-amp for a unity gain buffer. Many op-amps are not stable for non-
inverting gains less than 3-5. These op-amps tend to oscillate. The datasheet for a
particular op-amp usually states if it's not unity gain stable.
Figure 9: The schematic for a unity gain buffer amplifier.
Voltage Source
Figure 10: A 12 volt light bulb connected to a 1000 ohm 12 voltage source.
One of the interesting facts about a unit gain buffer is that its input current Iin is
zero. Since the input impedance is defined as Zin = Vin / Iin and since Iin is zero
then Zin is equal to infinity or is very large. An example of where a unity gain
buffer is used is when a source has a high impedance value and it needs to drive a
1- 9
low impedance load. Consider the following circuit of Figure 10. The voltage
source has an internal resistance of 1000 ohms and is rated at 12 volts. It is desired
to use this voltage source to turn on a 12-volt light bulb with an internal resistance
of 1000 ohms. Using Ohm’s Law the current through the light bulb is 12 volts /
2000 ohms and the voltage across the light bulb is 6 volts not 12 volts as required
to light the light bulb (it’s a 12 volt light bulb).
Voltage Source
Figure 11: A 12 volt light bulb connected to a 1000 ohm 12 voltage source via a
unity gain buffer.
Figure 11 shows using a unity gain buffer to light the light bulb. With this circuit,
since the current into the op-amp is zero the voltage drop across the internal voltage
source resistor is 0 and 12 volts appears at the input of the V+ terminal of the op-
amp. Since this amplifier is a unity gain buffer Vout = Vin = 12 volts. The full 12
volts now appears across the 12 volt light bulb. As long as the maximum output
current of the op-amp is not exceeded the voltage across the light bulb will remain
at 12 volts. Unlike the circuit of Figure 10 where the voltage across light bulb
dropped to 6 volts, the unity gain buffer circuit was able to maintain 12 volts across
the light bulb.
Summing Amplifier
An application of the inverting amplifier is that of the summing amplifier shown in

Figure 12. Given that plus terminal of the op-amp is at ground and the current into
the op-amp terminal is zero the current flowing into R1 is equal to the sum of
current due to each input.
1- 10
V1
V2
V3
V4
Figure 12: A schematic for a summing amplifier.
Equation (12) gives that the current through RF is equal to the sum of all of the
current through R1, R2, R3, and R4.
IRF =IR1 + IR2 + IR3 + IR4 (12)
Solving for each of the currents in terms of the voltage across each Resistor and
substituting this into (12) gives:
0 - Vout V1-0 V2-0 V3-0 V4-0

RF = R1 + R2 + R3 + R4 (13)
and finally solving for Vout gives:
-RF -RF -RF -RF

Vout = R1 V1 + R2 V2 + R3 V3 + R4 V4 (14)
Equation (13) gives the output at op-amp as the weighted sum of the inputs V1, V2,
V3 and V4. The summing amplifier of Figure 12 can be easily expanded to
additional inputs by simply adding addition voltage source inputs and the
appropriate resistors. For example for a two input summing amplifier with RF =3k
ohms and R1 = 1K ohms and R2 = 3k ohms the following equation is implemented
Vout = -3 V1 - V2 (15)
Some comments about the schematic in Figure 12: This schematic skipped drawing
the op-amp power supply that was drawn in the previous schematics of this lab.
This does not mean for this circuit that the op-amp power supply is not needed. It
is common to not to draw the op-amp power supply in a schematic so as to make
the schematic simpler to read, but the power supply still needs to be implemented
1- 11
as shown in the previous schematics including the 2 bypass capacitors. Also, the
use of input voltage sources as shown in the previous schematics are drawn using
a simple reference as V1, V2 etc., instead of the total symbol for a voltage source.
Again this is done to make reading the schematic easier.
Op-amps driving capacitive loads
Op-amps do not like large capacitance load at the output Vout. This tends to make
them unstable and having the possibility of the amplifier circuit oscillating. This
typically occurs when an op-amp amplifier circuit tries to drive long cables (such
as shielded cables). These cables tend to have a large capacitance per foot, which
essentially connects a large capacitance directly to the output of the op-amp
amplifier circuit. Figure 13 shows a slight modification of the unity gain amplifier
circuit that allows this amplifier to drive a large capacitance load. The resistor R
place in series with the op-amp output Vout isolates the capacitance load of the
capacitor. This resistor does not affect the voltage gain of this circuit. Since V+ =
V-, the amplifier circuit will adjust its output so that the virtual short is maintained.
Typical values for this resistor is in the range of 50 to 1k ohms.
Figure 13: A schematic for a unity gain amplifier adding a series resistor at the
output of the op-amp to drive a capacitive load.
Procedure:
General Setup:
1. Record the model and serial number of the scope, power supply, multimeter and
function generator used in laboratory experiment.
2. Download the datasheet for the op-amp used. This will be needed to obtain its
pin-out. When comparing datasheet data values to experimental data, use the
typical values in the datasheet if given.
3. Make sure that the power supply to the op-amp is correctly wired as not to apply
the incorrect polarity to the op-amp.
4. Initially set +Vcc = 15 volts and -Vcc to -15 volts
1- 12
5. When measuring any values make sure to measure all inputs as well as the output
of the circuit. Do not rely on the values indicated on the instruments. Always
measure all signal values.
6. The output impedance of the signal generator should be set to high-z. If the
generator is not set to high-z impedance, the displayed Amplitude, Offset, and
High/Low values will be different than what is selected on the generator.
Usually a factor of 2 larger.
7. Before turning any power on, double check the wiring to make sure that it is
correct.
8. Measure all resistors that are used in the amplifier circuits using the multimeter
and record these values
9. Use all measured values to determine experimental results, such as gain and
current.
10. Comparing data means to calculate the percent difference between two values.
For example, theoretical values versus measured values.
11. Comparing data graphically means to plot the data on the same plot to see how
the data overlaps.
Inverting Amplifier:
1. Using the parts kit in the lab, build an inverting amplifier with a gain Av of -3.
Use resistor values as small as possible but greater than 1k ohms.
2. Set +Vcc =15 volts and -Vcc = -15 volts
3. Measure all resistor values
4. Apply a 1-volt DC input to this circuit and measure both the input and output
using the multimeter.
5. Compute the experimental gain Vout / Vin and compare it with the expected
theoretical Gain for Av = -R1 / R2 using the measured values for R1 and R2.
6. Compute the current through R1 and R2 from the measured resistances and the
measure voltages Vin, V-, V+ and Vout.
7. Compare the currents in R1 and R2 from step 5.
8. Repeat steps 4 and 5 for Vin = 0, 1, 2, 3, 4, and 5 volts and Vin = -1, -2, -3, -4
and -5 volts.
9. Generate a plot of Vout versus Vin from steps 4 and 8.
10. From the plot given in step 9 determine the maximum and minimum Vout
obtainable.
11. Compare these two values of Step 10 to the values given in the datasheet from
the Maximum Peak Output Voltage versus Supply Voltage.
12. Apply a 2-volt peak-to-peak, 200 hertz sine wave to the input and record from
the oscilloscope the input and output waveforms.
13. Compare the phase between the input and output waveforms.
14. Repeat steps 12-13 for a gain Av = -10 for the inverting amplifier. Use resistor
values as small as possible but greater than 1k ohms.
15. Using the same Av -10 inverting amplifier, apply a 0.05 volt peak sine wave.
For various frequencies between 1000 Hz and 1 MHz obtain Vout and Vin and
compute Av = Vout / Vin. Select frequencies with the value of 1X, 2X, and 5X
factors for each decade of frequency.
1- 13
16. Plot in dB Av (20 log(| Av | ) ) versus frequency.
17. Determine the frequency where the gain is down by -3dB.
18. Repeat steps 15 – 17 for a 2 volt peak-to-peak input.
19. Apply a 2-volt peak-to-peak square wave and measure the rise time of the output
to determine the slew-rate of the op-amp (∆Voltage / ∆ Time = slope of the
edge). Use the linear rising section to determine the slew rate. Zoom in on an
edge with the oscilloscope to accurately measure the rise time.
20. Compare the measured slew-rate from step 19 to the value given in the data
sheet.
21. Compare the measured value with Equations (6) and (7) for both 0.05 volt peak
sine wave input and the 1 volt peak sine wave input.
Non-Inverting Amplifier:
1. Repeat steps 12 - 21 for the inverting amplifier section for the non-inverting
amplifier except Av = +3 and Av = +10 instead of Av = -10.
2. Apply a 2 volt peak-to-peak, 200 Hz sine wave to the input of the, gain of 10,
non-inverting amplifier with +Vcc =15 v and -Vcc = -15
3. Add a load resistor from the op-amp output Vout to ground.
4. Measure the peak output voltage from the op-amp for load resistors in the range
of 100 ohms to 10k ohms. Use at least 5 different resistor values
5. Plot Vout peak-to-peak versus load resistance.
6. Compare this plot with the plot given in the data sheet (Maximum Peak Output
Voltage versus Load Resistance).
7. Design and build a non-inverting amplifier with a gain of 1000. Set +Vcc = 15
volts and -Vcc = -15 volts. Use resistor values as small as possible but greater
than 1k ohms.
8. Set Vin to 0 volts. The best way to do this is to disconnect Vin from the V+
terminal of the op-amp and tie the V+ terminal to ground.
9. Measure Vout. This value is the output due to VOS. Use Equation (11) to
calculate VOS.
10. Compare the VOS measured in Step 9 to the value given in the datasheet.
Summing Amplifier:
1. Design and build a summing amplifier to implement Vout = -5 V1 - 2 V2. Use
resistor values as small as possible but greater than 1k ohms.
2. Apply a 0.2-volt peak-to-peak, 200 Hz sine wave to V1 and a 1 volt DC input to
V2.
3. Using an oscilloscope measure and record the output at Vout.
4. Repeat steps 1-3 for a DC inputs of -1 and 2 volts.
Unity Gain buffer.

1. Implement the Circuit given in Figure 10 using 1000-ohm resistors. Measure all
resistors.
1- 14
2. Measure the voltage across each resistor and calculate the current in each
resistor.
3. What is the voltage across the 1k ohm resistor that represents the light bulb?
4. Build a unity gain buffer as given in Figure 11.
5. Measure the voltage across each resistor and calculate the current in each
resistor.
6. What is the voltage across the 1k ohm resistor that represents the light bulb?
7. Build the unity gain buffer circuit given in Figure 13 with R at the output initially
set to zero (a wire).
8. Connect a 0.001 microfarad capacitor to the output of the op-amp to ground.
9. Set Vin to 2.0-volt peak-to-peak, 1 KHz square wave. Using an oscilloscope
measure and record the output at Vout.
10. Add a 1k ohm resistor as shown in Figure 13 for the resistor labeled R. Using an
oscilloscope, measure and record the output at Vout. Record and note the change
in Vout from step 12.
11. Disconnect the load 0.001 microfarad capacitor and set R back to zero ohms.
Set +Vcc = +5 volts and -Vcc to -5 volts. Apply a DC input and measure the
output Vout as Vin is varied from -5 Volts to + 5volts. Make sure to obtain at
least 1 point at each integer voltage value. Use the signal generator as the input
for this step. Set the voltage peak-to-peak to its minimum value of 20 millivolts
and to change the DC value use different offset values on the generator.
12. Plot Vout versus Vin and discuss what is observed in the laboratory report.
13. Lookup the Common-Mode input Voltage range. If the inputs are allowed over
the range of -Vcc to +Vcc then this operational amplifier is also referred to as a
rail-to-rail input op-amp.
Report: Please follow the procedures in this laboratory manual for writing the report for this
experiment. Include in your report:
1. The equipment used model and serial number.

2. Laboratory partners
3. Date and time data were taken.
4. Your laboratory report should include the goal of the laboratory experiment.
5. The procedures.
6. All calculations for each step.
7. All plots generated for each step.
8. All comparisons calculations.
9. All waveforms obtained in each step
10. For each data collection step in the procedure, there should be either data collected, a
calculation performed or a waveform recorded. Please include these in the report.
11. Short summary discussing what is observed for each of the steps given in the laboratory
experiment.
12. Also include what you learned.
Note: All schematics / Circuit diagrams for this laboratory experiment were generated using
LTSpice IV.
1- 15
EXPERIMENT #2
More Linear Operational Amplifier Applications
Goals:
To introduce the concepts of an operational amplifier (op-amp) used as a difference
amplifier, an instrumentation amplifier, and a voltage-to-current converter. Data collected
during this laboratory experiment will be compared to the theoretical equations for the
appropriate circuits. Additionally an application for the difference amplifier will be
presented.
References:
Microelectronics-Circuit Analysis and Design, D. A. Neamen, McGraw-Hill, 4th
Edition, 2007, ISBN: 978-0-07-252362-1.
Equipment:
Oscilloscope: Tektronix DPO 4034B Mixed Signal
Triple Power supply
2N2222A NPN transistor
Pre-laboratory:
and the procedural steps in this experiment. Carefully read each section and become
familiar with the equations for each circuit.
with: Multisim, Workbench or LTSpice IV simulate the following circuits:
The equations required for gain Av are given in the appropriate sections for the
difference amplifier, instrumentation amplifier, and the voltage-to-current
converter.
a. Design a gain Ad = 2 difference amplifier using a minimum of 1k-ohm resistors

and the circuit diagram in Figure 3.
b. The difference amplifier needs two inputs V1 and V2. Simulate this difference
amplifier time transient response for an input for V1 equal to a 1.0 volt 200 Hz
sine wave and for V2 equal to a 1.0 volt 200 Hz sine wave but 180 degrees out
of phase with the V1.
2- 1
c. Plot the input voltages as well as the output voltage as a function of time.
d. Repeat steps b and c but this time set the phase difference between V1 and V2
to 0 degrees.
e. Repeat steps a, b, c, and d for a gain Ad = 4 difference amplifier.
f. Design a gain Ad = 2 instrumentation amplifier using a minimum of 1k-ohm
resistors and the circuit diagram in Figure 5.
g. The instrumentation amplifier needs two inputs V1 and V2. Simulate this
instrumentation amplifier time transient response for an input for V1 equal to a
1.0 volt 200 Hz sine wave and for V2 equal to a 1.0 volt 200 Hz sine wave but
180 degrees out of phase with the V1.
h. Plot the input voltages as well as the output voltage as a function of time.
i. Repeat steps g and h but this time set the phase difference between V1 and V2
to 0 degrees.
j. Repeat steps f, g, h, and i for a gain Ad = 4 instrumentation amplifier.
k. Design a voltage-to-current converter that produces an output of 1mA for every
volt of input using a minimum of 1k-ohm resistors and the circuit diagram in
Figure 6.
l. Simulate the voltage to converter designed in step k for V2 = 3 volts and Vin =
2 volts.
m. Vary V2 between 1 volt and 7 volts and plot IL versus V2.
Discussion:
Consider the following design problem as shown in Figure 1. A voltage source is
connected to a single ended amplifier in which a noise source is introduced onto
the wire between the voltage source and the amplifier.
Amplifier Vout
Voltage
Source V Av = A
Noise (N)
Figure 1: An example of a single ended amplifier with input noise and a gain of A.
The output voltage is then given by
Vout = (V + N) . A = V . A + N . A (1)
The design issue is that the noise is introduced only onto the signal wire. If the
layout of Figure 1 is modified, so that a second signal -V on a second wire is
transmitted along with the original V in which both wires are collocated. Then any
noise introduced on the wires is the same on both wires and the difference between
the two signal lines produces a noise free output. Figure 2 shows the block diagram
of this configuration. Since the noise is common to both wires, taking the
2- 2
difference results in cancellation of the noise. This common noise of both wires is
referred to as common mode noise.
V V1 Vout
Voltage Amplifier
Source Noise (N) Av = A
-V V2
Figure 2: An example of a differential amplifier with input noise.
The amplifier used in Figure 2 is a difference amplifier with Vout defined as
Vout = Ad . (V1 - V2) . (2)
But V1 and V2 can be written in terms of the differential voltage sources as
V1 = (V + N) (3)
And
V2 = (-V + N) . (4)
Substituting V1 and V2 into Equation 2 gives
Vout = Ad . [ (V + N ) - (-V + N) ] . (5)
Which reduces to
Vout = Ad . [ 2 . V + N - N ] = Ad . 2 . V (6)
Vout contains twice the signal and no common mode noise. An example, where a
difference amplifier is used is to remove 60 Hz noise for an audio system
transmitted over a long cable. It is not uncommon to transmit an audio signal
differentially and then use a difference amplifier at the receiving end to remove any
common mode 60 Hz noise that might be injected in the cable.
Figure 3 gives the schematic of using a single op-amp to implement a difference

amplifier. Vout depends on the four resistors R1 - R4:
R4 R1 + R2 R2
Vout = V1 R3 + R4 R1 - V2 R1 . (7)
If the sum R1 + R2 is set equal to R3 + R4, then Equation (7) reduces to
2- 3
R4 R2
Vout = V1 R1 - V2 R1 . (8)
Finally if R4 = R2, which implies R1 = R3, then equation simplifies to
R2
Vout = R1 [V1 - V2] . (9)
and Vout is equal to the difference of V1 and V2 with a differential gain
R2
Ad = R1 (10)
Figure 3: A single op-amp difference amplifier.
Ideally, if R1 perfectly matches R3 and R2 perfectly matches R4, when V1 equals

V2 then Vout should be equal to zero. Unfortunately, this cannot always be
achieved with the resistor values that are selected. All resistors used have a finite
tolerance value. This depends on the resistors used but the most common resistor
tolerances are 1%, 5% and 10%. To verify the performance of a difference
amplifier, V1 and V2 are set to a common voltage value of Vcm. The output is
then measured. From Equation (7), with V1 = V2 = Vcm, Vout becomes
 R4 R1 + R2 R2 
Vout = Vcm  R3 + R4 R1 - R1  . (11)

Dividing both sides of Equation (11) by Vcc gives the common mode gain Acm as
2- 4
Vout  R4 R1 + R2 R2 
Acm = Vcm =  R3 + R4 R1 - R1  . (12)

Ideally, Acm should be zero. To find the output when V1 is not equal to V2 then
V1 is set to Vd/2 and V2 is set to an equal and opposite value of -Vd/2. Substituting
these values into Equation (7) gives
Vd  R4 R1 + R2 R2 
Vout = 2  R3 + R4 + R1  . (13)
 R1
Dividing both sides by Vd, the difference mode gain Ad can be found
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 1 𝑅𝑅4 𝑅𝑅1+𝑅𝑅2 𝑅𝑅2

𝐴𝐴𝐴𝐴 = = �𝑅𝑅3+𝑅𝑅4 + � . (14)
𝑉𝑉𝑉𝑉 2 𝑅𝑅1 𝑅𝑅1
Setting R1 = R3 and R2 = R4 gives a common mode gain of zero and a difference

mode gain of Ad = R2 / R1. A measure of the performance of a difference amplifier
is the ratio of the absolute value of difference mode gain to the absolute value of
the common mode gain and commonly called the Common Mode Rejection Ratio
(CMRR):
 |Ad| 
CMRR = 20 log10 |Acm| . (15)
 
The CMRR is commonly given in Decibels and higher the value the better the
performance of the difference amplifier. Since operational amplifiers are
essentially difference amplifiers, the datasheet associated with the op-amp usually
specifies the op-amps CMRR. One important fact of the op-amps is that the CMRR
is a function of the frequency of operations and the CMRR tends to decrease in
value as the frequency of operation increases as shown in Figure 4.
The main limitations of the difference amplifier given in Figure 2 is that the input
impedance is not very high and the input impedance of the two inputs is not the
same. The input impedance for the V1 input is
Z(V1) = R3 + R4 (16)
and for the V2 is
Z(V2) = R1 . (17)
2- 5
CMRR
100 dB
60 dB
20 dB
100 1k 10k 100k Hz
Figure 4: A typical plot of the CMRR of an op-amp as a function of frequency.
Another version of a difference amplifier where both inputs have high impedance
is given in Figure (5). This amplifier is commonly referred to as an instrumentation
amplifier. This amplifier contains the difference amplifier of Figure 3 and two
additional op-amp stages. A closer look at the circuits shows that both V1 and V2
are tied directly to the non-inverting input of these two op-amps. Since the input
impedance is very high, the current into an op-amp is approximately zero.
Va
Vb
Figure 5: An instrumentation amplifier designed using three op-amps.
The voltage Va for this amplifier is given as
R5  R5
Va = V2 R7 + 1 - V1 R7 . (18)
 
and for Vb as
2- 6
R6  R6
Vb = V1 R7 + 1 - V2 R7 . (19)
 
Since the right most stage of Figure 5 is a difference amplifier, Vout is found by
substituting Va for V2 and Vb for V1 into Equation (7)
 R6  R6  R4 R1 + R2

Vout = V1 R7 + 1 - V2 R7 . R3 + R4 R1  -
    
 R5  R5 R2
V2 R7 +1 - V1 R7 R1 . (20)
   
Rearranging and combining V1 and V2 gives
 R6   R4 R1 + R2 R5 R2 
Vout = V1 R7 + 1 . R3 + R4 R1  + R7 R1  -
  
 R6  R4 R1 + R2 R2 R5  
V2  R7 R3 + R4  + R1 R7 + 1  . (21)
  R1 
Using a similar approach to find Equation (11), the common mode gain is given by
Vout R6   R4 R1 + R2 R5 R2

Acm = Vcm = R7 + 1 . R3 + R4  + R7 R1 -
   R1 
R6  R4 R1 + R2 R2 R5 
R3 + R4  + R1 R7 + 1 . (22)
R7  R1   
Ideally, Acm should be zero. To find the output when V1 is not equal to V2 then
V1 is set to Vd/2 and V2 is set to and equal and opposite value of -Vd/2.
Substituting these values into Equation (21) gives
Vout 1  R6   R4 R1 + R2 R5 R2 

Ad = Vd = 2  R7 + 1 . R3 + R4 R1  + R7 R1  +
  
1  R6  R4 R1 + R2 R2 R5 
 
2  R7 R3 + R4 R1   + R1 R7 + 1  . (23)
Once the common mode gain Acm and the difference mode gain are known, the
common mode rejection ratio becomes Common Mode Rejection Ratio is found
using the same equation that was used for the difference amplifier
2- 7
 |Ad| 
CMRR = 20 log10 |Acm| . (24)
 
For the special case when R6 = R5 and R1 = R3 and R2 = R4, Vout can then be
written from Equation (21) as
 R6  R2  R6 R2 
Vout = V1 R7 + 1 . R1  + R7 R1  -
    
 R6 R2 R2 R6  
V2  R7 R1 + R1 R7 + 1  . (25)
     
Combining terms gives
2 . R6  R2 2 . R6  R2
Vout = V1  R7 + 1 . R1 - V2  R7 + 1 . R1 (26)
   
or
R2 2 . R6 
Vout = R1  R7 + 1 . [V1 - V2] (27)
 
Equation (27) illustrates that Vout is simply the difference between V1 -V2 with a
difference gain of
R2 2 . R6 
Ad = R1  R7 + 1 (28)
 
The last linear op-amp circuit that will be discussed in this laboratory experiment
is that of the voltage- to-current converter. The input to this circuit is voltage and
the output is current. Figure 6 gives the schematic diagram for this circuit. Given
the fact that there is a virtual short between the plus and minus inputs of the op-
amp and with V+ = Vin, the voltage on across R2 is simply Vin (V+ = V- = Vin).
The current through R2 is then Vin / R2. The current, I2, through R2 is also the
emitter current flowing in the transistor. The relationship of the current flowing in
a transistor between the base, emitter, and collector are
Ic = β Ib (29)
Ie = Ic + Ib = (β + 1) Ib (30)
and
β
Ic = Ie , (31)
β+1
2- 8
where β is the current gain of the transistor.
IL
I2
Figure 6: The schematic diagram for a voltage to current converter.
Since Ie = I2 in Figure 6, then Ic is given by
β
Ic = I2 , (32)
β+1
but I2 = Vin / R2
β Vin
Ic = , (33)
β+1 R2
The collector current is equal to the input voltage Vin divided by R2. If β is large,
on the order of 100, then
β
≈1 (34)
β+1
and Equation 33 then reduces to
Vin
Ic = R2 = IL . (35)
The output IL is simply Ic the collector current. The output current depends only
on the input voltage and R2 provided that the voltage across the resistor is less V2
- VCE(SAT)) (the saturation voltage VCE(SAT) is the minimum voltage that exist
2- 9
across the collector to the emitter). The second criteria is that voltage across R2
must be less than the maximum output voltage of the op-amp Vout(MAX) - Vbe -
Ib *100. Typically Ib (typically about 100x smaller than Ic) is very small and the
maximum voltage across R2 must be less than Vout(MAX)- Vbe. The 100 ohm
resistor R1 between the base and the output of the op-amp is used to isolate the base
to emitter capacitance from appear right at the output of the op-amp (See
Laboratory experiment #1).
Procedure:
General Setup:
2. Download the datasheet for the op-amp used. This will be needed to obtain the
pin-out of the op-amp used. When comparing datasheet data values to
experimental data use the typical values in the datasheet if given.
3. Make sure that the power supply to the op-amp is correctly wired as not to apply
the incorrect polarity to the op-amp.
4. Initially set +Vcc = 15 volts and -Vcc to -15 volts
6. The output impedance of the signal generator should be set to high-z. If the
generator is not set to high-z impedance, the displayed Amplitude, Offset, and
High/Low values will be different than what is selected on the generator.
Usually a factor of 2 larger.
7. Before turning any power on double check the wiring to make sure that it is
correct.
and record these values.
9. Use all measured values to determine experimental results such as gain and
current.
the data overlaps.
12. Obtain the pin out for the 2N2222 transistor
Difference Amplifier:
1. Using the parts kit in the lab, design the difference amplifier of Figure 3 with a
gain of Ad = 2 using 1k ohm resistors for R1 and R3.
2. Measure with the multimeter the actual resistance values.
3. Compute Acm and Ad using Equations (12) and (14).
4. Also calculate the CMRR using Equation (15).
5. Build the gain of Ad = 2 difference amplifier.
6. Setting V1 = V2 = 20 volt peak-to-peak 200 Hz sine wave measure Vout.
7. Calculate from step 6 Acm = Vout / V1.
2- 10
8. Varying the frequency of the function generator from 100 Hz to 100 kHz repeat
steps 6, and 7. Use measured values at frequencies of 1X, 2X and 5X for each
decade.
9. Setting V1 = 1 volt peak-to-peak 200 Hz sine wave and V2 = -V1. To generate
V2 = -V1, build an inverting amplifier 1 with a gain equal to –1. Apply the
function generator to V1 input to the difference amplifier and to the inverting
amplifier. The output of the inverter is now equal to -V1 and can be applied to
V2 input to the difference amplifier.
10. Measure Vout from step 9.
11. Calculate Ad from step 9 (Ad = Vout / (2 . V1).
12. Using Equation (15) calculate the CMRR from Acm from Step 7 and Ad from
Step 10.
13. Compare step 12 to step 4.
14. Discuss in the laboratory report the result of step 13.
steps 9, 10, and 11. Use measured values at frequencies of 1X, 2X and 5X for
each decade.
16. From steps 14, 15 calculate CMRR as a function of frequency.
17. From steps 14, 15 and 16 plot Acm, Ad, CMRR as a function of Frequency.
18. Decrease the value of R4 by 15 % to 20 %. Add a 10K ohm variable resistor in
series with this new value of R4. One side of the variable resistor to R4 and the
middle connection to ground. See Figure 7.
19. Setting V1 = V2 = 20 volt peak-to-peak 200 Hz sine wave measure Vout. Adjust
this variable resistor (potentiometer) to yield the smallest value for Vout. Adjust
R4 to best match R2 (This is the optimum setting).
20. Repeat steps 6,7, 9, 10, and 11 with this optimum setting for the potentiometer.
21. Build a gain of Ad = 4 difference amplifier.
22. Repeat steps 6, 7, 9, 10, and 11 for the difference amplifier of step 21.
23. Build the test circuit shown in Figure 8 with a gain of Ad = 4 for the difference
amplifier. This allows for two voltage sources to be applied to V1 and V2 of the
difference amplifier. The op-amp circuit of U2 inverts V1 adding 180 degree
phase shift. U1 and U3 are unity gain summers, summing V2 and V1 to produce
two signals into the difference amplifier:
Vout(U1) = - V1 - V2 (36)
Vout(U3) = +V1 - V2 (37)
24. Set V1 to a 0.5 volt peak-to-peak 200 Hz sine wave. Also set V2 to a 0.5 volt
peak-to-peak 20 Hz sine wave.
25. Measure and record with oscilloscope the outputs U1 and U2 op-amp stages.
26. Measure and record Vout with the Oscilloscope.
27. Discuss in the laboratory report the results of steps 25 and 26.
1
You can also use Channel B of the function generator and change the phase to 180°. Remember to phase-
lock (”track phase”) the two channels prior to setting the phase angle, otherwise, the two channels’ phases
won’t be aligned. Check with the o-scope.
2- 11
Figure 7. A difference amplifier with a variable resistor to optimize the resistors used.
Test Setup
Difference
Amplifier
Figure 8: The schematic diagram to test a one op-amp difference amplifier.
Instrumentation Amplifier:
1. Using the parts kit in the lab, build the instrumentation amplifier of Figure 5 with
a gain of Ad = 2 using 2k ohm resistors for R2, R3, and R7.
2. Measure with the multimeter the actual resistance values.
3. Compute Acm and Ad using Equations (22) and (23).
4. Also calculate the CMRR using Equation (15).
2- 12
5. Setting V1 = V2 = 20 volt peak-to-peak 200 Hz sine wave measure Vout.
6. Calculate from step 5 Acm = Vout / V1.
7. Setting V1 = 1 volt peak-to-peak 200 Hz sine wave and V2 = -V1. To generate
V2 = -V1, build an inverting amplifier 2 with a gain equal to -1. Apply the
function generator to V1 input to the difference amplifier and to the inverting
amplifier. The output of the inverter is now equal to -V1 and can be applied to
V2 input to the difference amplifier.
8. Measure Vout from step 7.
9. Calculate Ad from step 8 (Ad = Vout / (2 . V1).
10. Using Equation (24) calculate the CMRR from Acm from Step 6 and Ad from
Step 9.
11. Compare step 10 to step 4.
12. Discuss in the laboratory report the result of step 11.
steps 5, and 6. Use measured values at frequencies of 1X, 2X and 5X for each
decade.
steps 7, 8, and 9. Use measured values at frequencies of 1X, 2X and 5X for each
decade.
15. From steps 13 and 14 calculate CMRR as a function of frequency.
16. From steps 13, 14, and 15 plot Acm, Ad, CMRR as a function of Frequency.
Voltage to Current Converter:

1. Design and build the voltage to current converter given in Figure 6 for a
conversion factor of 1 milliamp of out for one volt of input.
2. Using a load resistance of RL = 1k ohms and V2 = 15 volts measure the voltage
across R2 and RL for Vin = 1 volt
3. Compute the current in RL and R2 from step 2.
4. Varying the input from 0 to 5 volts, repeat steps 2 and 3. Make sure there is at
least 5 points measured per integer voltage value.
5. Plot IL versus Vin from step 4. Is the curve linear?
6. Setting Vin to 2 volts measure IL as a function of V2 with V2 varying from 1
volt to 7 volts.
7. Plot IL versus V2.
8. Setting Vin to 2 volts and V2 to 5 volts measure IL with RL varying from 100
ohms to 2k ohms. Use at least 5 different resistor values for RL.
9. Plot IL versus RL.
experiment.

3. Date and time data was taken.
2
You can also use Channel B of the function generator to generate V2 – see Footnote 1.
2- 13
5. The procedures.
9. All waveforms obtained in each step
calculation performed, a waveform recorded. Please include these in the report.
experiment.
13. For the difference amplifier compare the theoretical CMRR versus the measured
CMRR.
14. Discuss the frequency plots of CMRR versus frequency for the difference amplifier.
15. Look up for the op-amp used in this laboratory experiment the CMRR.
16. Discuss in this laboratory report the results of steps 25 and 26 for the difference
amplifier.
17. For the instrumentation amplifier compare the theoretical CMRR versus the measured
CMRR
18. Discuss the frequency plots of CMRR versus frequency for the instrumentation
amplifier
19. Is the curve linear for IL versus Vin?
Note: All schematics / Circuit diagrams for this laboratory experiment was generated using
LTSpice IV.
2- 14
EXPERIMENT #3
Linear Voltage Regulators
Goals:
To introduce the concepts of a linear voltage regulator and their use to maintain a
regulated voltage output. Data collected during this laboratory experiment will be
compared to the datasheet for the parts used.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
Equipment:
Triple Power supply
2N2222A NPN transistor
Multimeter
7805 and 7812 linear three terminal regulators
Pre-laboratory:
and the procedural steps in this experiment. Carefully read each section and
become familiar with the equations for each circuit.
with: Mulitsim, Workbench or LTSpice IV simulate the linear regulator of Figure
2.
a. Pick R1 and R2 such that Vout is 3 volts. The minimum values for R1 and R2
should be 1000 ohms.
b. Set RL = 100 ohms and Vin = 6 volts. Measure with the simulator Vout.
c. Measure IL and Iin. Calculate Pin, Pout and Preg.
d. Calculate the Efficiency = Pout / Pin . 100%.
e. Vary RL from 50 to 10k ohms and measure Vout and IL.
f. Plot Vout versus IL
g. Setting RL to 1k ohms vary Vin from 0 to 6 volts.
h. Plot Vout versus Vin
i. What is the dropout voltage for this regulator.
j. Lookup the data sheet for the 7805 and 7812 (LM340) voltage regulators
3- 1
k. Find the typical output voltages.
l. Find the dropout voltage and calculate the minimum allowed input voltage
Vin for the 7805 and 7812 voltage regulators.
m. Find the peak output current.
n. Find the maximum allowed power dissipation of the regulator at room
temperature and with no heatsink (assume a TO220 case).
o. Find the load regulation.
p. Find the thermal resistance of the voltage regulator.
Discussion:
Consider the following circuit given in Figure 1. With R1 equal to 100 ohms
Vout is equal to 10.9 volts. If R1 is changed to 10 ohms, then Vout is equal to 6
volts. Vout depends on the load resistor R1. In other words, the output voltage
decreases as the load current (the current through R1) increases. In many
applications it is desirable to have a constant voltage source that is independent of
load current. For example, the +Vcc and -Vcc input to a typical op-amp circuit
should remain constant independent of the op-amp current.
Voltage Source
Figure 1: An example of a 12-volt voltage source with an internal resistance of 10 ohms.
A circuit that maintains a constant output voltage is called a regulator. There are
two types of voltage regulators that are available: those that work at a DC or
constant operation point (known as linear regulators) and those that are based
upon varying a duty cycle of a pulse (known as a switching regulator). This
laboratory experiment will focus on linear regulators. Switching regulators will
be discussed in a later laboratory experiment.
Figure 2 gives the circuit diagram for a linear regulator. This regulator uses a
2N2222 transistor and an op-amp to perform the output regulation. It is based
upon the requirement that the op-amp will try to adjust its output so as to keep its
inputs, V+ and V-, equal. The voltage at the V+ terminal is
R4
V+ = Vcc R3 + R4 (1)
3- 2
Assuming +Vcc =15v and -Vcc = -15v, then V+ = 1.485 volts. The op-amp will
adjusts its output voltage so that V- terminal is the same as V+. Since the output
from the regulator Vout is equal to voltage output of the opamp -Vbe, the output
of the regulator also changes. Given that the V- terminal is related to Vout as
R2
V- = Vout R1 + R2 (2)
then setting V+ = V- gives
R2 R4
V- = Vout R1 + R2 = Vcc R3 + R4 (3)
Solving for Vout
R1 +R2 R4
Vout = Vcc R2 R3 + R4 (4)
Iin
Iout
Figure 2: An example of a linear regulator.
Figure 2: An example of a linear regulator.
For +Vcc = 15 volts, R3 = 9.1K, and R4 = 1k Vout becomes
R1 + R2
Vout = 1.485v R2 (5)
From Equation (5) Vout does not depend on the load current, as was the case for
the circuit given in Figure 1.
Here's how the regulator in Figure 2 maintains a constant voltage at Vout.

Assume Vout drops below its regulated voltage given by Equation (4) or (5).
Then the V- terminal voltage will be less then the V+. Since the voltage output of
the op-amp is Aod (V+ - V-), the voltage output from the op-amp will increase in
3- 3
the positive direction (V+ > V-). This increasing voltage will raise the voltage on
the base of the transistor. Since Vbe is a constant (about .7 volts), Vout will
increase. Vout increases until V+ = V-. Now consider that Vout increases in
voltage beyond regulated voltage given in Equation (4). For this case V+ will be
less than V-. Since the voltage output of the op-amp is Aod (V+ - V-), the voltage
output from the op-amp will tend to decrease in value. This lowers the voltage on
the base of the transistor, which lowers the transistor's emitter voltage and lowers
Vout.
As a final note, R5 is used to limit the current out of the op-amp and capacitors
C1 and C2 are bypass capacitors used to maintain low AC impedance path to
ground from Vin and Vout. These capacitors are used to eliminate any AC
signals from appearing on Vin and Vout so the output of the regulator is a
constant DC value.
The regulator of Figure 2 is a simple regulator with no short circuit or thermal

protection. The linear regulator of Figure 2 is available in a three terminal part
with both thermal and short circuit protection. Figure 3 gives the circuit diagram
for this regulator. One set of linear regulators that are commonly used is the
78XX three terminal linear regulator family, where XX gives the output voltage
of the regulator. Both the input and output voltages of these regulators are
positive. For example, a 7805 voltage regulator produces an output voltage +5
volts. For negative output voltages, the 79XX regulators are available.
Iin IL
IL
IQ
Figure 3: An example of a three terminal linear voltage regulator.
There are several parameters that are important when dealing with a linear
regulator:
Iin = IL + IQ (6)
3- 4
IQ is the regulator quiescent current and typically is milliamps. If the load current
is much larger than IQ then Iin ≈ IL and IQ can be ignored in the following
equations.
Pin = Vin . Iin = Vin . (IL + IQ) (7)

Pout = Vout . IL (8)
Preg = Pin - Pout = (Vin - Vout) IL + IQ Vin (9)
Where Pin is the input power, Pout is the output power, and Preg is the power
dissipated in the regulator. The efficiency of a voltage regulator defines the
percentage of power that is delivered to the load and is given by
Pout
Efficiency = Pin 100% . (10)
The main objective of a voltage regulator is to maintain a constant voltage over

various load currents. One parameter of importance is the load regulation
parameter. This parameter gives the change in Vout as the regulator's output
current, IL, is varied from a minimum to a maximum current. From Equation (9),
the power dissipated in the regulator is proportional to the voltage across the
regulator. To minimize the power dissipated in the regulator, the goal is to use as
minimum a voltage across it as possible. Another parameter of importance is the
minimum allowable voltage across the regulator for the regulator to maintain a
constant output voltage. In other words the regulator is still in regulation. This
minimum voltage across the regulator is known as the dropout voltage Vdo.
As with any electronic parts, there are maximum ratings that must be adhered to,
such as the maximum input voltage, the maximum allowable load current, the
maximum power dissipation allowed and the maximum operating temperature.
Finally, since these parts are short circuit protected, the maximum short circuit
current is also given. As long as the maximum power dissipation and maximum
operating temperature are not exceeded the part will operate indefinitely with its
output shorted to ground.
There are several items that will destroy one of these three-terminal regulators
even if these parts are correctly installed in the circuit diagram of Figure 3 and the
maximum rating are adhere to. The first is applying the wrong polarity voltage at
the input. The second is having Vout be greater than Vin. This can occur if C1 >
C2 and the energy storage in the output is greater than the energy storage in the
input. This commonly occurs during power off if C1 > C2. The input to regulator
will discharge toward zero volts faster than the output. Figure 4 shows a solution
to protecting the regulator should Vout become greater than Vin. Under normal
use, Vin > Vout, and the diode is reversed biased. Should Vout become greater
than Vin, the diode is forward biased preventing any current flowing into the
regulators from its output.
3- 5
D1
Iin IL
IL
IQ
Figure 4: An example of a linear voltage regulator with protection.
The three terminal regulators can also be made to be adjustable so any desired
regulated output voltage can be obtained. The only requirement is that the
minimum voltage is that of the part itself. For example, a 7805 regulator can be
made adjustable, but its minimum output voltage is 5 volts. Figure 5 gives the
circuit required to make a three-terminal linear regulator adjustable. For this
discussion, assume the regulator output voltage is Vreg (the voltage between the
output and the ground pins of the regulator). Then IR1 is then given by
Vreg
IR1 = R1 . (11)
and the voltage across R2 (VR2) is

 Vreg
VR2 = R2 (IQ + IR1) = R2 IQ + R1  . (12)
 
The output voltage from the regulator Vout is the sum of VR1 + VR2. But VR1
is equal to Vreg
 Vreg
Vout = R2 IQ + R1  + Vreg . (13)
 
or
R2 
Vout = R2 . IQ + Vreg R1 + 1 . (14)
 
If the current IR1 >> IQ then the quiescent current IQ can be ignored in Equation
(14) and Vout is given by
3- 6
R2 
Vout = Vreg R1 + 1 . (15)
 
Since for the 78XX regulators, IQ is about 6 milliamps. IR1 should be about at
least 30 milliamps. The goal is not to make IR1 too large, as this will reduce the
efficiency of the regulator circuit.
Iin Iout
IL
IR1
IQ
IR2
Figure 5: A circuit diagram to make linear voltage regulator adjustable.
Procedure:
General Setup:
1. Record the model and serial number of the scope, power supply, multimeter
and function generator used in laboratory experiment.
2. Download the datasheet for the 78XX regulators. This will be needed to obtain
the pin-out of the regulator. When comparing datasheet data values to
3. Obtain the pin-out for the 2N2222 transistor
4. Make sure that the power supply to the op-amp is correctly wired so as not to
apply the incorrect polarity to the op-amp.
5. When measuring any values, make sure to measure all inputs as well as the
output of the circuit. Do not rely on the values indicated on the instruments.
Always measure all signal values.
correct.
current.
the data overlaps.
3- 7
Discrete linear regulator:
1. Build the linear regulator of Figure 2.
2. Calculate the resistors R1 and R2 required to produce an output voltage of 3
volts for the circuit of Part 1. The minimum values for R1 and R2 should be
1000 ohms.
3. Set +Vcc = 15 volts and -Vcc to -15 volts.
4. Build this linear circuit (Part 1) using a 1000 ohm resistor for RL. Take note of
the polarity of the two electrolytic capacitors. Double check your wiring.
5. Vary the input voltage Vin, between 0 and 6 volts and measure Vout, Iout and
Iin.
6. Plot the output voltage Vout as a function of Vin.
7. What is the dropout voltage for this regulator?
8. Plot the output current Iout as a function of Vin.
9. Plot the input current Iin as a function of Vin.
10. Calculate Pin and Pout from steps 6, 7, 8 and 9.
11. For step 5, plot the output efficiency Pout / Pin as a function of Vin once the
output voltage becomes constant.
12. Keeping Vin at 6 volts and varying the RL between 100 and 10000 ohms and
measure Vout, Iout, and Iin as a function of RL. Use 5 different load resistor
values.
13. Calculate the load regulation.
14. For step 12, plot the output efficiency Pout / Pin as a function of RL.
78XX Three terminal linear regulator

1. Build this linear regulator circuit of Figure 3 using the 7805 regulator and a
1000 ohm resistor for RL. Take note of the polarity of the two electrolytic
capacitors. Double check your wiring.
2. Vary the input voltage between 0 and 20 volts and measure Vout, Iout and Iin.
3. Plot Vout as a function of Vin.
4. What is the dropout voltage for this regulator and compare this measured value
to the value given in the datasheet.
5. Plot Iout and Iin as a function of Vin in Step 2.
6. Compute Pin and Pout as a function Vin.
7. From step 6, plot the output efficiency Pout / Pin as a function of Vin once the
8. Keeping Vin at 15 volts and varying the RL between 100 and 10000 ohms,
measure Vout, Iout and Iin as a function of RL. Use 5 different load resistor
values.
9. Compute Pin and Pout as a function RL
11. Repeat steps 1 – 7 for the 7812 voltage regulator.
78XX A three terminal linear regulator as an adjustable regulator

1. Calculate the resistors R1 and R2 required to produce an output voltage of 7
volts for the linear regulator circuit of Figure 5. The maximum values for R1
and R2 should be 150 ohms*.
3- 8
a. *Note: the resistors supplied in the lab are only quarter watt resistors. Do
not exceed this rated power level! Be sure to calculate the power through
both R1 and R2 and ensure it is not exceeding 0.25 W (P = I2R). Hint, if
R1 = 150 Ω then the power for both R1 and R2 will not exceed the limit.
Include these power calculations in your report.
2. Build the linear regulator circuit of Figure 5 using a 7805 regulator and a 1000
ohm resistor for RL. Take note of the polarity of the two electrolytic
capacitors. Double check your wiring.
3. Vary the input voltage between 0 volts and 15 volts and measure Vout, Iout
and Iin.
4. Plot Vout as a function of Vin.
5. Determine the dropout voltage for this regulator and compare this measured
value to the value given in the datasheet.
6. Plot Iout and Iin as a function of Vin in Step 3.
7. Compute Pin and Pout as a function Vin.
8. From step 7, plot the output efficiency Pout / Pin as a function of Vin once the

4. The goal of the laboratory experiment.
5. The procedures.
6. The pre-laboratory results.
calculation performed or a waveform recorded. Please include these in the report.
11. Short summary discussing what is observed for each of the steps given in the
laboratory experiment.
13. Make sure to include the measured dropout voltages as well as the dropout voltages
from the datasheet.
14. Discuss the efficiency of this linear regulator and why is efficiency an important
parameter.
15. Where does the regulator power go to?
3- 9
EXPERIMENT #4
Switching Voltage Regulators
Goals:
To introduce the concepts of using a switching regulator as a voltage regulator. The
theory of a switching regulator will be presented along with its design. Data collected
during this laboratory experiment will be compared to the datasheet for the switching
regulator used.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
The following two links are to the Tektronix website for the user manual for the
TDS2014B oscilloscope and for the AFG3022B Function generator:
Oscilloscope:
http://www2.tek.com/cmswpt/madetails.lotr?ct=MA&cs=mur&ci=16272&lc=EN
Equipment:
Oscilloscope: DPO 4034B
Triple Power supply
Multimeter
Inductor (100 µH)
Electrolytic Capacitors (470 µF at 15 volts)
LM 2576-ADJ switching regulator
Fast recovery diode MBR 1060
50 Ω, 50 W Power Resistor
Pre-laboratory:
with: Multisim, Workbench or LTSpice IV simulate the linear regulator of Figure
2.
a. Download the National Semiconductor LM 2576-ADJ Datasheet and become familiar

with this part.
b. Design a 5 volt DC output switching regulator with 10 volts DC of input.
4- 1
c. Pick the ratio for R1 and R2 that sets the output to 5 volts DC (Figure 2 of datasheet).
The minimum values for R1 and R2 should be 1000 ohms.
d. Compute E*T given on page 14 of datasheet.
e. Assuming a maximum current of 1 to 1.5 amps find the optimum inductance L given
in Figure 7 of datasheet.
f. Compute the minimum output capacitance (page 14 of datasheet).
g. Assuming a 3 amp maximum load, calculate the efficiency of the switching regulator
(Performance Figures).
h. Assuming a maximum load current of 3 amps, find the power dissipation of the
output and the regulator.
i. What is the expected dropout voltage at 3 amps (Vin - Vout)?
j. What is the expected current limit for the LM2576 regulator?
k. Approximately how much does the output voltage change if the input voltage goes
from 10 volts to 15 volts (assume a junction temperature of 25 degrees C)?
Discussion:
Switching regulators are based upon using a pulse where its duty cycle is varied to
maintain a constant voltage at its output. Consider the periodic pulse waveform
given in Figure 1. The average or DC for time varying signal is by
T
1
Vavg = T ⌠
⌡ v(t) dt . (1)
0
But for the periodic pulse signal v(t) is equal to zero for the time period of T - T1
and takes on a value of A from 0 to T. Substituting these values is Equation (1)
gives
T1
1
Vavg = T ⌠
⌡ A dt . (2)
0
Integration Equation yields an average voltage or DC voltage (Vavg) of
T1
Vavg = A T (3)
Volts
T
1
A
0
T Time
Figure 1: An example of a periodic pulse waveform.
4- 2
The average voltage Vavg depends on the ratio of T1 to T. As T1 decreases,
Vavg decreases, and as T1 increases, Vavg increases. The ratio of T1 to T is
nothing more than the duty-cycle, D, of the periodic waveform
Vavg = A . D . (4)
A circuit that produces a varying duty cycle periodic waveform is called a pulse
width modulator. Consider the block diagram shown in Figure 2. This circuit
uses a comparator and a sawtooth waveform to generate a varying duty cycle
periodic waveform. The output of the comparator is A volts if V1 > V2 otherwise
the output of the comparator is 0 volts. For a fixed input Vin, if Vin > V2, then
the output of the comparator is A volts. As the input V2 increases in value due to
the sawtooth waveform increasing in value, there is a point in time when V2
becomes greater than Vin and the output of the comparator goes to zero. Figure 1
gives the output of the pulse width modulator with T1 equal to Vin and T equal to
K.
V1
Vin Comparator
Vout
V1 > V2
V2 Vout = A
Sawtooth
Waveform
T
K
0 Time
Figure 2: A block diagram of a pulse width modulator.
The average voltage output from Figure 2 is then given by Equation (3) as
Vin
Vavg = A K , (5)
where T = K (the amplitude of the sawtooth wave at time T) and T1 = Vin (the
time when the sawtooth amplitude is equal to Vin). The pulse width modulator
4- 3
provides a means of varying the pulse width of a periodic pulse waveform, which
allows the average voltage to be varied.
Figure 3 gives a simple switching voltage regulator using an N-channel MOSFET

and a pulse width modulator. The input to the pulse width modulator is a sampled
version of Vout generated by the voltage divider composed of R1 and R2. The
capacitor C is used to filter the sampled output voltage to obtain its average or DC
value. As the output voltage increases, the pulse width modulator decreases its
pulse width and decreases the time that the MOSFET is on. This decreases the
time that Vin is connected to the output. As Vin decreases, the pulse width
modulator increases its pulse width. This increases the time that Vin is connected
to Vout.
The output waveform is the periodic pulse given in Figure 1 with A equal to Vin.
Typical switching regulators use periodic frequencies in the range of a few
kilohertz to a few megahertz (1 / T).
Vin Drain Source Vout
Gate
Pulse Width
Modulator
Figure 3: A simple switching regulator.
The main limitation of the simple regulator given in Figure 1 is that Vout is a
periodic pulse, not a constant DC voltage. The problem is that, when the
MOSFET turns off, Vout goes to zero and the current to the load, RL, goes to
zero. What needs to be added to this simple switching regulator is a means of
storing energy when the MOSFET is on and delivering this energy to the load,
RL, when the MOSFET is off. One device that stores energy in a magnetic field
is an inductor.
Figure 4 shows the modification of the simple switching regulator with the
addition of an inductor and a diode. This allows current to continue to follow in
RL when the MOSFET is OFF. When the MOSFET is on, Vin appears at the
source pin, the diode is reversed biased and off, and VL appears on the left side of
the inductor L1. Ignoring the current flowing in R1 and R2 since this current is
usually much smaller than current flowing in RL, the effective circuit, when the
MOSFET is on, is an RL circuit as shown in Figure 5. Since the current in an
4- 4
inductor cannot change instantaneously, the current through the inductor starts to
increase at rate of
Vin  t L
IL = RL 1 - e- R  (6)
 
and reaching a final value IL = Vin / RL. At the point that MOSFET turns off,
the diode becomes forward biased allowing current to continue to flow in the
inductor in the same direction as when the MOSFET was on. The model of the
switching regulator when the MOSFET is off is shown in Figure 6. The diode
turns on allowing current to flow through the inductor L1 and through the load
RL.
Vin Source Vout
IL
Gate
Pulse Width
Modulator
Figure 4: A switching regulator with energy storage.

Vin Vout
IL
Figure 5: The model of the switching regulator when the MOSFET is on.
Vout
IL
Figure 6: The model of the switching regulator when the MOSFET is off.
4- 5
Since there is no longer an applied source the current through the inductor L and
the load RL decreases at the rate of
tL
IL = K . e- R (7)
where K is the current flowing in the inductor and the load RL when the
MOSFET turns off. Figure 7 shows the current flowing in the load RL and the
inductor L1 as a function of time.
IL
MOSFET MOSFET MOSFET MOSFET

ON OFF ON OFF
Time
Figure 7: A plot of load current as a function of time.
Since the voltage across a resistor is equal to its current times its resistance, Vout
= IL . RL. Vout is simply the same waveform that is given in Figure 7, but scaled
by RL. The magnetic energy stored in the inductor when the MOSFET is on is
delivered to the load when the MOSFET is off essentially providing for
continuous current flow when the MOSFET is on and off. To maintain a constant
Vout, an additional energy storage element, a capacitor, is placed across the load
RL. The final switching regulator is given in Figure 8.
Vin Drain Source Vout
. IL
Gate CL
Pulse Width
Modulator
Figure 8: The final switching regulator circuit diagram.
When designing this regulator, several parameters must be adhered to. First, the
maximum currents for the MOSFET, the inductor and the diode must be
observed. The polarity and maximum voltage of the capacitors that are used must
4- 6
be followed. And finally the maximum power dissipation allowed for the
MOSFET and its maximum temperature rating must be included in the design.
The switching regulator presented here, as shown in Figure 8, is available from

many semiconductor manufacturers in a single integrated circuit (IC). Typically
the IC includes the MOSFET as well as the pulse width modulator. The external
parts that must be included are the inductor, diode, and the capacitor. R1 and R2
are usually also included in the IC. The switching regulator presented in Figure 8
is known as a BUCK regulator, since Vout < Vin. There are other switching
regulator topologies that allow for generating an output voltage that is greater than
the input voltage. These switching regulators are known as BOOST regulators.
Another common topology is the single-ended primary-inductor converter
(SEPIC) switching regulator. This regulator uses two inductors and allows for
both Vout < Vin and Vout > Vin conditions to be achieved in one design
topology.
The main advantage that a switching regulator has over a linear regulator is power
efficiency. From the linear regulator laboratory experiment, the power dissipation
across a linear regulator is
Preg = Iin * Vreg (8)
But
Iin = IL + IQ , (9)
where IQ is the quiescent current of the regulator. This is the current needed by
the regulator to power its internal electronics. Under most conditions, IQ << IL
and
Iin ≈ IL (10)
The power dissipated in the regulator is
Preg = Iin . Vreg (11)
and the total input power
Pin = Vin . Iin = Vin . IL (12)
Pout is simply
Pout = Vout . IL (13)
The efficiency is defined as
4- 7
Efficiency = Pout / Pin . 100% (14)
Substituting Equations (12) and (13) in Equation (14) gives
Efficiency = Vout / Vin . 100% (15)
Just having Vin > Vout, The efficiency of the linear regulator circuit is less than
100%. Typical efficiencies for linear regulator are bellow 50%. For switching
regulators, the main loss of power is the power dissipated in the MOSFET. But
the MOSFET is either full on or full off. When the MOSFET is off there is no
power dissipated in the MOSFET, but when the MOSFET is on the power
dissipated in the MOSFET is
PMOSFET = IL2 . Rds , (16)
where Rds is the drain to source on resistance of the MOSFET. For a power
MOSFET Rds on is on the order of a few milliohms. Such a small value produces
very small power dissipation in the MOSFET allowing for very high efficiencies
for the switching regulator. Efficiencies of 80% to 90% are very common in
switching regulators. To reiterate, the frequency of switching regulators runs
anywhere from a few kilohertz to a few megahertz. This allows for reasonably-
sized inductors and capacitors to be used.
Procedure:
General Setup:
2. Download the datasheet LM 2576-ADJ switching regulator. This will be
needed to obtain the pin-out of the regulator. When comparing datasheet data
values to experimental data use the typical values in the datasheet if given.
3. When measuring any values make sure to measure all inputs as well as the
correct.
current.
the data overlaps.
Switching Regulator:
1. Have the lab assistant approve your design using a 100 µH inductor and two
4- 8
470µF, 15 volts capacitors.
2. Build your design making sure to correctly wire the LM2576, the polarity of
the diode, and the electrolytic capacitors.
3. Triple check your wiring before applying any power.
4. Use the 50 Ω, 50W power resistor provided in the lab for RL.
5. Vary the input voltage Vin between 0 and 15 volts and measure Vout, Iout and
Iin.
6. Plot the output voltage Vout as a function of Vin.
7. What is the dropout voltage for this regulator?
8. Compare the dropout value in step 7 to the expected value from the datasheet.
9. Plot the output current Iout as a function of Vin.
10. Plot the input current Iin as a function of Vin.
11. Calculate Pin and Pout from steps 6, 9, and 10.
12. For step 11, plot the output efficiency Pout / Pin as a function of Vin once the
output voltage becomes constant. How does this value compare to the
expected value.
13. Setting Vin to 10 volts and varying the RL between 100 and 10000 ohms
measure Vout, Iout, and Iin as a function of RL. Use at least 5 different
resistor values. Do not forget to measure the actual resistance of these
resistors.
14. Plot Vout as a function of RL.
15. Plot the output current Iout as a function of RL.
16. Plot the input current Iin as a function of RL.
17. Calculate Pin and Pout from steps 14, 15, and 16.
19. For step 14 calculate the load regulation.
20. Measure with a scope the voltage on both sides of the inductor for Vin = 10v
and RL = 50 Ω, 50 W. Discuss your findings in the lab report.
5. The procedures.
4- 9
13. Make sure to include the measured dropout voltage as well as the dropout voltage
from the datasheet.
14. Discuss the efficiency of this switching regulator and why is efficiency an important
parameter.
16. Where does the power dissipated in the regulator go?
4-10
EXPERIMENT #5
Precision Diodes and Applications
Goals:
To introduce the concepts of using diodes as rectifiers and limiters. The concepts of the
ideal diode designed from diodes and op-amps circuits will also be discussed. Finally,
diode limiter circuits will be presented. Data collected during this laboratory experiment
will be compared to the theoretical equations presented in this laboratory experiment.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
The following link is to the Tektronix website for the user manual for the DPO
4034B oscilloscope and for the AFG3022B Function generator:
Oscilloscope:
Equipment:
Triple Power supply
Multimeter
1N4148 diodes
Electrolytic Capacitors (10 µF at 15 volts)
LM 285 precision voltage reference.
Pre-laboratory:
Use the simulation package of your choice in which you are the most familiar
with: Mulitsim, Workbench or LTSpice IV.
a. Download the National Semiconductor LM285 Datasheet and become familiar with
this part.
b. Simulate the half wave rectifier circuit given in Figure 3 with R = 10K and the diodes
equal to 1N4148s. Set Vin equal to a 200 Hz +5 volt peak sine wave with no DC
offset. Obtain a plot of Vin and Vout versus time.
c. Repeat Step b for Vin equal to a 200 Hz +10 volt peak sine wave with no DC offset.
5- 1
d. Simulate the full wave rectifier circuit given in Figure 5 with R = 1K and the diodes
equal to 1N4148s. Set Vin to a 200 Hz +5 volt peak sine wave with no DC offset.
Obtain a plot of Vin and Vout versus time.
e. Repeat Step d for Vin equal to a 200 Hz +10 volt peak sine wave with no DC offset.
f. Repeat Step b for Figure 7a for R =10K and C = 10 µf. Obtain the peak-to-peak
ripple voltage. How does this value compare to Equation (11)? What is the DC
voltage at the output Vout? How does this value compare to Equation (13).
g. Repeat Step d for Figure 7b for R =10K and C = 10 µf. Obtain the peak-to-peak
ripple voltage. How does this value compare to Equation (12)? What is the DC
voltage at the output Vout? How does this value compare to Equation (14).
h. Simulate the ideal half wave rectifier given in Figure 9 for R = 10k. Set Vin to a 200
Hz +5 volt peak sine wave with no DC offset. Also set +Vcc = 15 volts and -Vcc = -
15 volts. Use this same value for all steps unless otherwise directed. Obtain a plot of
Vin and Vout versus time.
i. Change the diode orientation in Figure 9 and repeat Step h.
j. Change the diode orientation back and change the input frequency of the sine wave to
2000 Hz, 20kHz and 200 kHz and repeat Step h.
k. Simulate the ideal half wave rectifier given in Figure 11 for R = 10k. Set Vin to a 200
Hz +5 volt peak sine wave with no DC offset. Obtain a plot of Vin and Vout versus
time.
l. Change the diode orientations in Figure 11 and repeat Step k.
m. Simulate the ideal full wave rectifier given in Figure 13 for R1 and R2 = 1k. Set Vin
to a 200 Hz +5 volt peak sine wave with no DC offset. Obtain a plot of Vin, V2 and
Vout versus time.
n. Change the diode orientations in Figure 13 and repeat Step m.
o. Simulate the limiter circuit given in Figure 18a for RF = RA = 100k, R1 = 20k, R2 =
15k, R3 = 10K, and R4 = 20K. Set VR1 = +Vcc and VR2= -Vcc . Vary Vin from -
Vcc to +Vcc and obtain Vout. Compare this result to the plot given in Figure 17.
Use at least 10 points to perform the comparison.
p. Repeat Step o but remove RF.
Discussion:
Diode Model
The diode model used in the laboratory experiment is shown in Figures 1 and 2.
When the diode is forward biased so that Vd > Vx, (the forward turn on voltage)
the diode is on and the current Id flowing in the diode is non-zero (Figure 2b).
When Vd < Vx, the diode current Id is zero and the diode is reversed biased
(Figure 2c). Under this condition no current is flowing in the diode and the diode
can be considered an open circuit. Figure 1 gives a plot of the diode current as a
function of the diode voltage showing the forward biased and reverse biased
region. Typical values of the forward biased voltage Vx depends on the
semiconductor material used for the diode but typically is in the range of 0.2 volts
to 0.7 volts.
5- 2
Half Wave Rectifier
Diodes can be used to convert an average voltage AC signal to a DC voltage

using the process of rectification. Figure 3(a) shows a diode connected to a
resistor R with a Vin of
Id
Reverse Forward
Bias Bias
0 Vx Vd
Figure 1: Id versus Vd for the simplified diode model.
Id
+ -
Vd
(a)
Id ≠ 0
Vx Id = 0
- +
+ - + -
Vd Vd
Vd > Vx Vd < Vx
(b) (c)
Figure 2: The simplified model for the diode. (a) Its symbol, (b) the
forward biased model, and (c) the reversed biased model.
Vin(t) = A . sin(ωt) , (1)
where ω is the frequency in rad/sec and ω = 2πf (f is the frequency in hertz). This
circuit is commonly called a half wave rectifier.
When Vin < Vx the diode is off (reversed bias) and the diode model of Figure
2(c) applies, the diode current Id = 0 and Vout = 0 (Vout = R . Id). Under the
condition Vin > Vx, the diode is on (forward bias) and the model of Figure 2(b)
applies and current Id flows through the diode and the resistor R. Vout is then
given by
5- 3
Vout = Vin - Vx . (2)
Vin
A 1
(a) (b)
+
0
Id
- -A 1
0 time
Figure 3: (a) Half wave rectifier circuit diagram and (b) Vin as a function
of time.
The output is the same as the input Vin but smaller in voltage by Vx (Assuming
Vin peak >> Vx). Figure 4 gives Vout as a function time.
Vout
A - Vx 1
1
0 time
Figure 4: Vout as a function of time for the half wave rectifier circuit.
As shown in Figure 4, half of the sine wave waveform has been set to zero. The
average or DC value for Vout is now non-zero. The average is defined
T
1
⌠ v(t) dt .
Vavg = T ⌡ (3)
0
Substituting Vin(t) = A . sin(ωt) for v(t)
T
1
Vavg = T ⌠
⌡ A . sin(ωt ) dt . (4)
0
5- 4
and integrating over its period T = 1 / f produces a zero average value. Repeating
the process for Vout gives
T
2
1
Vavg = T ⌠
⌡ (A - Vx) . sin(ωt ) dt . (5)
0
The integration is now over half the period since Vout is zero for half the period.
Performing the integration in given in Equation (5) yields
A- Vx
Vavg = . (6)
π
Full Wave Rectifier
The main limitation of the half wave rectifier is that its output is zero for half of
the period. Figures 5(a) and (b) give circuit diagram of a full wave rectifier using
a bridge configuration. A full wave rectifier allows current to flow during both
parts of the input sine wave input.
A
+ D1 D2
Vin
I
- D4 D3
B
(a)
A
- D1 D2
Vin
I
+ D4 D3
B
(b)
Figure 5: A full wave rectifier circuit diagram (a) For Vin > 2 . Vx and
(b) Vin < - 2 . Vx..
5- 5
Assuming Vx is the same for all of the diodes, when Vin > 2 . Vx, D2 and D4 are
forward biased and D1 and D3 are reverse biased. Current then flows from Vin
(A) through D2 through R and then through D4 and back to Vin (B) (Figure 5(a)).
Again, when Vin < -2 . Vx, but in the opposite polarity, D1 and D3 are forward
biased and D2 and D4 are reverse biased. Under this condition, current flows
from Vin (B) through D3 and then through R and D1 and back to Vin (A) (Figure
5(b)).
Under both conditions for Vin > 2 . Vx and Vin < - 2 . Vx, the current flowing
through the resistor R is in the same direction. Even though Vin changes polarity,
the voltage across R (Vout = I . R) remained the same. Figure 6 gives Vin and
Vout as a function of time. Vout is the same as Vin when Vin > 2 . Vx except it
has been reduced in amplitude by 2 two diode drops of Vx (Vout = Vin - 2 . Vx
and assuming Vin peak >> 2 .Vx). When Vin < -2 . Vx, then Vout is the inverted
version of Vin Vx except it also has been reduced in amplitude by two diode
drops of Vx (Vout = 2 . Vx - Vin). In other words
Vout = | Vin - 2 . Vx) | , (7)
where | | is the absolute value.
Vin Vout
A 1 A-2Vx
0 0
1
0 time 0 time
Figure 6: Vin and Vout as a function of time for a full wave rectifier.
The average or DC value for Vout is also non-zero. For the full wave rectifier,
the average is given by
T
1
Vavg = T ⌠
⌡ | (A - 2 . Vx) . sin(ωt ) | dt . (8)
0
5- 6
Since Vout is the same for 0 ≤ t < T/2 and T/2 ≤ t < T, the integral is twice the
integral over 0 ≤ t < T/2
T/2
2
Vavg = T ⌠⌡ | (A - 2 . Vx) . sin(ωt ) | dt (9)
0
Performing the integration gives
2 . (A - 2 . Vx)
Vavg = (10)
π
The average or DC value is twice the average value of the half wave rectifier
given in Equation (6).
Rectifier Filtering
In many applications, it is desired to convert the output of rectification (either half

or full wave) to a constant DC output. This can be accomplished by adding a
capacitor C in parallel with the resistor R in Figures 3(a) and 5 as shown in Figure
7.
Figure 8 shows the output of the filtered half wave rectifier circuit. The curve
highlighted in X is when the diode is delivering power to the load R and charging
the capacitor C. Once the peak is reached, the capacitor is charged to its
maximum value of A - Vx. As Vin decreases below its peak value of A the diode
turns off. At this point the energy stored in the capacitor C is delivered to the
resistor R and the capacitor starts to discharge as highlighted in the curve Y. The
voltage difference between the peak value of A - Vx and the minimum voltage is
known as the ripple voltage, Vr, and is given by
A - Vx
Vr = f R C , (11)
where f is the frequency in Hertz of Vin as defined in Equation (1). For a full
wave rectifier, the period is half that of a half wave rectifier or the frequency is
twice that of a half wave rectifier
A - Vx
Vr = 2 f R C , (12)
The average output voltage Vout for the half wave rectifier is the given as
 1 2 Vr 
Vout(average) = (A - Vx) . 1 +  (13)
 π A - Vx 
5- 7
+
C
-
A (a)
+ D1 D2
Vin
I
- D4 D3 C
B
(b)
Figure 7: Filtering the output of a (a) half-wave and (b) full-wave rectifier circuit.
Vout
2
A-Vx Y Y
Vr
X X
0
2
0 time
Figure 8: Filtered half wave rectifier output using a capacitor of Value C.
and for a full wave rectifier
 1 2 Vr 
Vout(average) = (A - 2 .Vx) . 1 +  (14)
 π A - 2 .Vx 
5- 8
with Vr defined by Equations (11) and (12), respectively. For Vr << A - Vx or Vr
<< A - 2 . Vx, the average voltage output reduces to Vout(average) = A - Vx for
the half wave rectifier and Vout(average) = A - 2 . Vx for the full wave rectifier.
The Ideal Half Wave Rectifier
The major limitation with the full wave and half wave rectifiers presented above
is the forward biased voltage drop of the diodes that must be achieved before the
diodes conduct. For the half wave rectifier Vin must exceed Vx and for the full
wave rectifier must exceed 2 . Vx before the diodes start conducting. The ideal
rectifier circuits use the open loop gain of the op-amp to remove the effects of the
forward biased voltage diode Vx. Consider the ideal half wave rectifier shown in
Figure 9. Assuming initially Vin = 0, and op-amp output is zero. Then since
op-amp output = Ad (V+ - V-) = Ad (Vin - V-) , (15)
(where Ad is the open loop gain of the op-amp) V- must also be initially zero.
Since V- and op-amp's output are both zero, the voltage across the diode Vd = op-
amp output - V- is zero and the diode is off. If Vin is now allowed to go negative
(Vin < 0) then by Equation (15), the op-amp's output goes negative and the diode
voltage Vd becomes negative and remains off. Since the diode is off and no
current flows through the diode, the current flowing in the resistor I = 0. This
results in zero voltage across the resistor and Vout = 0. Under this condition the
feedback loop is open and the output of the op-amp is at maximum allowed
negative voltage (negative rail). Next, consider Vin positive (Vin > 0). Under
this condition, from Equation (15) the op-amp's output heads toward a positive
voltage turning on the diode. The current flowing through the diode also flows
through the resistor producing a non zero voltage at Vout. The op-amp will try to
make V+ = V- (virtual short) maintaining a closed loop configuration. Since V+
= Vin and V+ = V-, V- = Vout = Vin. The output Vout is nothing more than the
input for Vin > 0. Equation 16 give the output Vout
Vout = Vin for Vin > 0 (16)

Vout = 0 for Vin < 0
If Vin is a sine wave as given by Equation (1), then Vout is the same as Figure 6
except the peak output voltage is equal to A not A - Vx. The forward bias diode
voltage has been eliminated. To maintain a closed loop condition and to maintain
that the diode is on, the op-amp's output = V- + Vx or the op-amp's output = Vin
+ Vx.
Changing the diode direction changes the polarity of the output producing an
output when Vin is negative
5- 9
Vout = 0 for Vin > 0 (17)
Vout = Vin for Vin < 0
Figure 10 gives an inverting ideal half wave rectifier configuration. To maintain

V- = V+ = 0, the diode must be forward-biased, and this occurs when the op-
amp's output is greater than zero. For the op-amp's output to be greater than zero,
Vin must be less than zero. If the feedback loop is closed since the diode is on,
the Vout is
- R2
Vout = R1 Vin for Vin < 0 . (18)
Equation (18) is nothing more than the output equation for an inverting amplifier
given an input Vin. For Vin > 0, the op-amp's output is negative (at its most
negative value) and the diode is reversed biased and off. Since the diode is off (I2
= 0) and since no current flows into the V- terminal of the op-amp, then the
current I1 flowing in the resistor R1 is zero. Since I2 = 0 then
Figure 9: The ideal half wave rectifier.
Vout = 0 for Vin > 0 (19).
Equations (18) and (19) describe an inverting half wave rectifier output as
described by Figure 6 without the effects of Vx. Changing the direction changes
the polarity of Equation (18) and (19) and inverts the output polarity of the half
wave rectifier of Figure 10.
5-10
Figure 10: Inverting configuration ideal half wave rectifier.
.
The main limitation of the half wave rectifier circuits presented in Figures 9 and
10 is that for half the time period the output of the op-amp is in saturation either
near the positive or negative rails. Care must be taken when an op-amp's output is
at its rails and if the input common mode voltage is exceeded. When the op-amp
is running open loop with no feedback (V+ ≠ V-), Vout will not be zero when the
diode D1 is off. In addition, for an op-amp to come out of saturation, it takes time
and slows the response of the half wave rectifier circuits given in Figures 9 and
10. Adding a diode D2 as shown in Figure 11 prevents the op-amp from going
into saturation and increases the overall response time of the half wave rectifier.
For Vin <0, the op-amp output is positive and D1 is forward biased on and D2 is
reversed biased off. Under this condition the output Vout is the same as described
by Equation (18). But when Vin > 0 the op-amp's output is negative, D1 is off
and D2 is forward biased on. D2 forward biased on keeps the feedback loop
closed so that V- = V+ = 0. The current flowing in diode D2 is equal to the
current flowing in R1 (Vin/R1). With diode D2 forward biased on and V- equal
to zero, the op-amp's output is equal to -Vx and the op-amp output is kept from
going to its most negative value (negative saturation). What makes the circuit of
Figure 11 faster than the circuit of Figure 10 is that turning off the diodes is
usually faster than an op-amp coming out of saturation.
The Ideal Full Wave Rectifier
Consider a sine wave input Vin as described in Equation (1) as input to the half
wave rectifier given in Figure 11 with diodes the direction of diodes D1 and D2
swapped. This produces a negative going half wave rectifier output V2 as shown
in Figures 12(a) and (b). Next, consider
V3 = Vin + 2 . V2 (20)
5-11
Figure 11: Half wave rectifier without op-amp saturation.
The best way to analyze Equation (20) is to determine V3 when Vin > 0 and when
Vin is < 0. When Vin < 0, the output V2 of the inverted have wave rectifier
output (Figure 12(b) is zero and Equation (20) reduces to
V3 = Vin + 2 . 0 = Vin for Vin < 0 (21)
For Vin > 0, V2 is simply equal to the inverted version of Vin (V2 = -Vin) and
Equation (20) reduces to
V3 = Vin + 2 . (-Vin) = -Vin for Vin > 0 . (22)
Equations (21) and (22) can be combined and be written as
V3 = -| Vin | (23)
Equation (23) is nothing more the inverted version of the full wave rectifier
equation in Equation (7) for the ideal rectifier case of Vx = 0 (Figure 12(c)).
Inverting Equation (23) gives
Vout = | Vin | (24)
and is shown in Figure 12(d). Inverting Equation (20) gives Vout directly as
V3 = -Vin - 2 . V2 (25)
A closer look at Equation (25) shows that this equation is nothing more than a
summing amplifier with gains of -1 and -2, respectively. Figure 13 shows the
circuit diagram for a full wave rectifier using the ideal half wave rectifier and a
two-input summing amplifier with gains of -1 and 2, respectively.
5-12
n
yn n
A1 1
y v
n Vin0 n V20
-A1 -A1
00 500
Time1000 00 500
Time1000
n n
(a) (b)
0.5 A1
V3
00 Vout0.5
x x .( 1 )
n n
0.5 00
-A1 0.5
00 500
Time1000 00 500
Time1000
n n
(c) (d)
Figure 12: (a) The input signal, (b) the inverted half wave rectified signal,
(c) the signal due to Equation (20), and the final output Vout.
Figure 13: An ideal full wave rectifier.
5-13
The Precision Voltage Reference
Many applications require a precision constant DC voltage that does not vary with
temperature and is very accurate. Figure 14 shows a schematic diagram for a
LM285 a precision voltage reference. The schematic diagram is the same as that
used for a zener diode. In addition, using and biasing a precision diode is the
same as a zener diode. The only difference between a precision voltage reference
and a zener diode is the voltage across the diode remains fairly constant over a
large range of bias current, where for a zener diode there is a significant change in
voltage across the part as the bias current changes. For the LM285 precision
voltage reference, the voltage across the device has a constant voltage of 1.235
volts and has a typical change of voltage of only 7 millivolts over the current
range of 10 microamps to 20 milliamps. It has a temperature stability of a typical
value of less than 6 millivolt change in voltage over the temperature range of -40
°C to 85 °C.
Cathode
Anode
Figure 14: A schematic diagram for a precision voltage reference.
Figure 15 shows how to bias a precision voltage reference. Assuming the current
I1 flowing out of the output Vo is zero then I is gvien as
I = (Vcc - Vo) / R , (26)
where Vo = 1.235 volts. To bias the LM285 a bias current in the range of 0.5
milliamps to 20 milliamps is chosen.
I
I1 = 0
LM285
Figure 15: A schematic diagram shown how to bias a precision voltage reference.
Since it was assumed that the current I = 0, typically Vout is connected to an op-
amp buffer to produce a gain so the desired voltage reference can be obtained.
5-14
Figure 16 gives the circuit diagram for a precision voltage reference using the
LM285. The final output is then
R2 
Vout = Vo R1 + 1 . (27)
 
I =1.235
I1 = 0
Figure 16: A schematic diagram for precision voltage reference.
But, Vo = 1.235 volts
R2 
Vout = 1.235 R1 + 1 . (28)
 
To design a precision voltage reference, for a desired output Vout, Equation (28)
is used and the ratio of R2 / R1 is found
R2 Vout
R1 = 1.235 -1 . (29)
Either R1 or R2 is chosen and the other resistor is calculated from Equation (29).
The final step is to solve Equation (26) for R and to calculate R based on the
value for Vcc and the desired current I between 10 microamps and 20 milliamps.
The Ideal Diode Limiter
There are many types of limiter circuits that limit the output to a fixed value.
Many of these circuits are based upon using ether standard or zener diodes to
perform the limiting function. Figure 18a gives the two diode limiter where the
voltage limit can be set using resistors. For this derivation and discussion it is
assumed that V1 and V2 are much greater than the forward biased voltage Vx of
the diodes used so that Vx can be ignored in the derivation. Under this
assumption, ideal diodes will be assumed where Vx is assumed to be zero.
5-15
Analyzing Figure 18(a) further shows that if V1 > 0 and V2 < 0, both diodes will
be off and the output is the simply the circuit shown in Figure 18(b). To satisfy
the V1 > 0 and V2 <0, Vout can be found by relating Vout to VR1 and VR2.
The current through R1 and R2 is given as the voltage across R1 and R2 divided
by the total resistance R1 and R2
VR1 - Vout
I= R1 + R2 (30)
The voltage across R2 is then found as
VR1 - Vout
V(R2) = I . R2 = R1 + R2 (31)
V1 is sum of V(R2) + Vout or
VR1 - Vout
V1 = Vout + R2 R1 + R2 (32)
Rearranging Equation (32) and combining terms gives
R2 . VR1 - R1 . Vout
V1 = R1 + R2 (33)
For the diode D1 to be off, V1 > 0 as stated earlier. Substituting this fact into
Equation (33)
R2 . VR1 - R1 . Vout
0> R1 + R2 (34)
and solving for Vout yields
VR1 . R2
Vout > − R1 (35)
Using a similar approach in solving for V2 and with the requirement that V2 < 0
for D2 to be off, gives
VR2 . R3
Vout < − R4 (36)
As long as
5-16
VR1 . R1 VR2 . R3
− R2 < Vout < − R4 , (37)
both diodes will be off and the circuit of Figure 18(b) applies. Figure 18(b) is a
circuit for an inverting amplifier with
RF
Vout = − RA Vin (38)
Figure 17 shows the transfer function of Vout versus Vin. The center curve is
represented by Equation (38).
Slope ≈ −(RF || R3) / RA Vout
≈ −VR2 . (R3 / R4)
Slope ≈ −RF / RA Vin
≈ −VR1 . (R2 / R1)

Slope ≈ −(RF || R2) / RA
Figure 17: Vout versus Vin for the limiter circuit given in Figure 18.
For the case then V2 > 0, then
VR2 . R3
Vout > − R4 (39)
and the diode D2 is on and diode D1 is off. With Diode D2 on, the resistor R3 is
placed parallel with RF. Vout for this case is then given by
R3 || RF
This is the top left curve in Figure 17. Similarly for the case when V1 < 0, then
VR1 . R2
Vout < − R1 , (41)
5-17
VR1
V1
V2
VR2
(a)
VR1
V1
V2
VR2
(b)
5-18
VR1
V1
V2
VR2
(c)
VR1
V1
V2
(d) VR2
Figure 18: A two diode limiter circuit diagram (a) the actual circuit, (b) the
model for when D1 and D2 are both off, (c) the model for when D1
is off and D2 is on, (d) the model for when for D1 is on and D2 is
off.
5-19
When V1 < 0, diode D1 is on and diode D2 is off as shown in Figure 18(d). Diode
D1 on places R2 is parallel with RF and Vout becomes
R2 || RF
This is the bottom right curve in Figure 16.
Procedure:
General Setup:
2. Download the datasheet LM 285 precision voltage reference.
3. When comparing datasheet data values to experimental data use the typical
values in the datasheet if given.
correct.
current.
the data overlaps.
Experimental Data
1. Build and design the half wave rectifier circuit given in Figure 3 with R = 10K
and the diodes equal to 1N4148s. Set Vin equal to a 200 Hz +10 volt peak-to-
peak sine wave with no DC offset. Obtain a plot of Vin and Vout versus time
using the oscilloscope.
2. Measure the DC voltage with a multimeter and compare this result to Equation
(3).
3. Repeat Step 1 for Figure 7a for R =10K and C = 10 µF. Obtain the peak-to-
peak ripple voltage. How does this value compare to Equation (11)? What is
the DC voltage at the output Vout? How does this value compare to Equation
(13).
4. Build and design the full wave rectifier circuit given in Figure 5 with R = 10K
and the diodes equal to 1N4148s. Set Vin to a 200 Hz +10 volt peak-to-peak
sine wave with no DC offset. Obtain a plot of Vin and Vout versus time the
oscilloscope. Since the output of the full-wave rectifier is not isolated from the
input, special care must be taken. Both the ground of the signal generator and
the oscilloscope are tied together through electrical ground. So attaching the
5-20
signal generator at the input and attaching the oscilloscope at the output shorts
the input and output together. To measure the output using the oscilloscope,
one of the output leads is tied to one channel of the oscilloscope and the other
is tied to an additional channel. Then the math function of the oscilloscope is
used to take the difference between the two leads. The ground of the scope is
tied to the ground lead of the signal generator
5. Measure the DC voltage with the multimeter and compare the results to
Equation (6).
6. Repeat Step 4 for Figure 7b for R =10K and C = 10 µF. Obtain the peak-to-
peak ripple voltage. How does this value compare to Equation (12)? What is
the DC voltage at the output Vout? How does this value compare to Equation
(14).
7. Build and design the ideal half wave rectifier given in Figure 9 for R = 1k. Set
Vin to a 200 Hz +10 volt peak-to-peak sine wave with no DC offset. Also set
+Vcc = 15 volts and -Vcc = -15 volts. Use this same value for all steps unless
otherwise directed. Obtain a plot of Vin and Vout versus time using the
oscilloscope.
8. Change the diode orientation in Figure 9 and repeat Step 7.
9. Change the diode orientation back and change the input frequency of the sine
wave to 2000 Hz, 20kHz, and 200 kHz and repeat Step 7.
10. Build and design the ideal half wave rectifier given in Figure 11 for R1 = R2 =
1k. Set Vin to a 200 Hz +10 volt peak-to-peak sine wave with no DC offset.
Obtain a plot of Vin and Vout versus time using the oscilloscope.
11. Change the diode orientations in Figure 11 and repeat Step 10.
12. Build and design the ideal full wave rectifier given in Figure 13 for R1 = R3 =
2k and R2 = R4 = R5 = 1k. Set Vin to a 200 Hz +10 volt peak-to-peak sine
wave with no DC offset. Obtain a plot of Vin and Vout versus time using the
oscilloscope.
13. Change the diode orientations in Figure 13 and repeat Step 12.
14. Build and design the precision voltage reference given in Figure 16 for Vout =
5 volts. Set R1 equal to 1K and set the current to the precision voltage
reference diode to 1 mA. Measure Vout and V+ and compare this result to the
datasheet for the LM285 and the expected Vout.
15. Build and design the limiter circuit given in Figure 18a for RF = RA = 100k,
R1 = 20k, R2 = 15k, R3 = 10K, and R4 = 20K. Set Vcc = 10V. Set VR1 =
+Vcc and VR2= -Vcc . Using the signal generator, input a sawtooth or triangle
wave on Vin that varies from -Vcc to +Vcc and obtain Vout. Compare this
result to the plot given in Figure 17.
16. Repeat Step 15 with but remove RF.

5-21
5. The procedures.
13. Make sure to include a discussion on how the frequency of the input affects the
output of the ideal half wave rectifiers.
14. Discuss the difference between the ideal half wave and full wave rectifiers and the
non-ideal half wave and full wave rectifiers.
15. Discuss the effect of filtering the output of a half and full wave rectifier.
5-22
EXPERIMENT #6
Active Filters
Goals:
To introduce the concepts of using an operational amplifier to perform filtering of electrical
signals. Both the lowpass and highpass filters will be investigated. The equations for first
order and second order filters will also be given. The frequency response of the various
filters will be measured and compared with expected results.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
4034B oscilloscope:
Equipment:
Oscilloscope: DPO4034B
Triple Power supply
Signal generator
Resistors available in the laboratory (minimum filter resistor should be 10kΩ)
Pre-laboratory:
with: Mulitsim, Workbench or LTSpice IV simulate the following filters.
Simulate using a pulse input of 0 to 1 volt to the filter and compare one cycle to the
equations below.
First order Filters:

a. Simulate a first order lowpass filter using the circuit given in Figure 4 with ωo
= 10,000 rad / sec.
b. Using the AC simulation mode of the simulator obtain the lowpass filter
magnitude spectrum from 10 Hz to 10,000 Hz.
c. Determine the attenuation factor in dB / Decade from Step b.
d. Apply a 1 volt peak square input with a frequency of 200 Hz. Simulate and
plot the time response of this filter. Use 1 µsec rise and fall times, or less, for
6- 1
the pulse generator.
e. Simulate a first order highpass filter using the circuit given in Figure 7 with ωo
= 10,000 rad / sec.
f. Using the AC simulation mode of the simulator obtain the highpass filter
g. Determine the attenuation factor in dB / Decade from Step f.
h. Apply a 1-volt peak square input with a frequency of 200 Hz. Simulate and
Second order Filters
i. Simulate a second order lowpass filter using the circuit given in Figure 10 with
ωo = 10,000 rad / sec with Q = 2.
j. Using the AC simulation mode of the simulator, obtain the lowpass filter
k. From Step j, measure Vout at ω = ωo and compare this result to K . Q.
l. Apply a 1 volt peak square input with a frequency of 200 Hz. Simulate and
m. Measure the peak overshoot and compute the percent overshoot using Equation
(31)
n. Repeat Steps l and m for Q = 0.5, 1, and 5. How do these simulations compare
to Figure 12?
o. Compare the measured % overshoot to the calculated value from Equation
(31).
p. Simulate a second order highpass filter using the circuit given in Figure 13
with ωo = 10,000 rad / sec with Q = 2.
q. Using the AC simulation mode of the simulator, obtain the highpass filter
r. From Step q, measure Vout at ω = ωo and compare this result to K . Q.
s. Apply a 1 volt peak square input with a frequency of 200 Hz. Simulate and
t. Repeat Step s for Q = 0.5, 1, and 5. How does these simulations compare to
Figure 15?
Butterworth Filter
u. Simulate a fifth order lowpass Butterworth filter using the steps described in
the laboratory experiment with ωo = 10,000 rad / sec and Kd = 5. The
attenuation factor should be -100 dB / Decade.
v. Using the AC simulation mode of the simulator obtain the lowpass filter
w. From Step v, measure Vout at ω = ωo.
x. Apply a 1 volt peak square input with a frequency of 200 Hz. Simulate and
6- 2
Discussion:
Filtering of a signal is an important aspect of electronic signal processing. It
provides a means of reducing the noise present in a signal and means of removing
unwanted interference. Filtering of a signal is easily implemented using resistor,
inductor and capacitor circuits or resistor, capacitor and op-amp circuits. The
classification of a filter is based upon which frequency components have been
attenuated.
There are four major types of filters. An ideal lowpass filter is defined as one that
contains no transition set of frequencies in which the filter goes from passing
frequency components to the attenuation of frequency components:
1 𝑓𝑓𝑓𝑓𝑓𝑓 𝜔𝜔 ≤ 𝜔𝜔𝐶𝐶
𝐻𝐻(𝜔𝜔) = � . (1)
0 𝑓𝑓𝑓𝑓𝑓𝑓 𝜔𝜔 > 𝜔𝜔𝐶𝐶
Figure 1(a) shows a plot of its magnitude spectrum. This filter has a finite
discontinuity at the cutoff frequency ωc.
H(f) H(f)
1 1
0 ωc f 0 ωc f
(a) (b)
Figure 1: The magnitude spectrums for (a) the ideal lowpass filter
and (b) the ideal highpass filter.
In a similar way, the ideal highpass filter is defined as
1 𝑓𝑓𝑓𝑓𝑓𝑓 𝜔𝜔 ≥ 𝜔𝜔𝐶𝐶
𝐻𝐻(𝜔𝜔) = � . (2)
0 𝑓𝑓𝑓𝑓𝑓𝑓 𝜔𝜔 < 𝜔𝜔𝐶𝐶
This ideal filter also has a finite discontinuity. Figure 1(b) gives the highpass filter
magnitude spectrum. The ideal lowpass and highpass filters presented above
cannot be built using electronic components as these filters would need an infinite
number of storage elements such as capacitors and inductors.
Realistic filters do not have a sharp or zero transition band of passing frequency
components to attenuate frequency components. Figure 2 shows the three bands
associated with a typical filter. The pass band is the band where frequency
components of the input to the filter essentially remain unchanged. The attenuation
band is where the frequency components of the input are attenuated and the
6- 3
transition band is the band where the filter transitions from passing frequency
components to attenuating frequency components.
Pass Transition Attenuation

Band Band Band
Frequency
Figure 2: The three regions of a filter.
Figure 3(a) gives the magnitude spectrum for a typical lowpass filter. This filter
passes the frequencies below the cutoff frequency ωc and attenuates the frequency
components above the cutoff frequency. As shown in Figure 3(a), there is a gradual
transition from passing frequency components to attenuating frequency
components. Figure 3(b) gives a typical highpass filter. This filter passes the high
frequency components above the cutoff frequency ωc and attenuates the low
frequency components.
Figure 3(c) gives the magnitude spectrum for a bandpass filter. This filter passes
frequency components in the range of frequencies ω1 to ω2, with the center
frequency of the pass band given by ω0. The final filter is the band-reject filter,
given in Figure 3(d). This filter attenuates the frequency components in the range
of ω1 to ω2.
There are many types of electronic filters that are available. Many of these filters
come directly from electronic circuit designs that have existed for many decades.
Some of the most common ones are the Butterworth, elliptical, Chebyshev, and
Bessel filters as well as the simple first order resistor and capacitor network and the
second order resistor, capacitor, and inductor network. In this laboratory
experiment, the buffered version of the lowpass and highpass resistor-capacitor
filter circuits will be investigated along with the lowpass and highpass second order
resistor, capacitor, and op-amp filter circuits known as active filters.
First Order Filters

Figure 4 shows the circuit used to implement a buffered version of a first order
lowpass filter. The op-amp is nothing more than a unity gain buffer isolating the
output of the R-C filter. The transfer function of this filter is given as
Vout(s)  1 
H(s) = Vin(s) =  s  , (3)
 + 1
ωo 
6- 4
where ωo = ( RC)-1 and is known as the cutoff frequency of the filter.
Lowpass Highpass
HL(f) HH (f)
1 1
0 ωc f 0 ωc f
(a) (b)
Bandpass Band-reject
1 HB (f) 1 HR (f)
0 ω ωo ω f 0 ω ωo ω f
1 2 1 2
(c) (d)
Figure 3: Normalized frequency response curves of four common one-

dimensional filters used in Fourier filtering; (a) the lowpass filter, (b) the
highpass filter, (c) the bandpass filter, and (d) band-reject filter.
Figure 4: A buffered version of a first order lowpass filter.
Letting s = jω and substituting it into Equation (3) gives
Vout(ω)  1 
Vin(ω)  jω 
H(jω) = = (4)
 + 1
ωo 
The magnitude and phase are then given by
6- 5
Vout(ω)  1 
| H(jω) | = | |=  (5)
Vin(ω) ω2
 + 1
 ωo 
and
Vout(ω)  jω 
arg( H(jω) ) = arg( ) = −arctan  . (6)
Vin(ω) ωo
At the frequency ωo, the magnitude is equal to 1 / 2 and the phase is equal to -
45°. The magnitude in decibels (dB) is found by
| H(ω) | in dB = 20 log( | H(ω) | ) (7)
At the cutoff frequency ωo, the magnitude in dB is equal to -3.01 dB or simply -

3dB. Below the cutoff frequency ωo, the response of the filter is one and the
frequency components of the filter input remains unchanged. Above the cutoff
frequency, the frequency components are attenuated at a rate of -20dB per decade.
dB
0 Degree
0 0
-3 dB
| H(ω) | in dB Arg H(ω)
-45°
50 50
0
1 .10 1 .10
3 4
1 .10 1 .10
3 4
1 10 100
ωo 1 10 100
ωo
Rad/Sec Rad / Sec
Figure 5: The magnitude and phase spectrums for a first order lowpass R-C filter.
The response to a step input can be found by taking the inverse Laplace transform
of
1  1 
Vout(s) = s .  s  , (8)
 + 1
ωo 
with the Laplace transform of a unit step u(t) equal to 1 / s and is given as
Vout(t) = (1 − e-t/RC) u(t) (9)
A plot of Equation (9) is given in Figure 6.
6- 6
1.5
Vout(t)
0.5
0
0 Time
Figure 6: The step response to a first order lowpass R-C filter
The same procedures are used to find the frequency and time response for a first
order highpass filter. Swapping the capacitor and resistor in Figure 4 changes the
first order lowpass filter to a first order highpass filter, shown in Figure 7(a).
Figure 7(a): A buffered first order highpass R-C filter.
The transfer function of this filter is given as
 s

H(s) = Vin(s) =  s
Vout(s) ωo 
, (10)
 + 1
ωo 
where ωo = ( RC)-1 and is known as the cutoff frequency of the filter. Letting s =
jω and substituting it into Equation (10) gives
6- 7
 jω
Vout(ω)  ωo 

H(jω) = = . (11)
Vin(ω)  jω 
ωo + 1
The magnitude and phase are then given by
ω
 
|= 
Vout(ω) ωo
| H(jω) | = | (12)
Vin(ω)  ω2
+ 1
 ωo 
and
Vout(ω)  jω 
arg( H(jω) ) = arg( ) = 90° −arctan  . (13)
Vin(ω) ωo
At the frequency ωo, the magnitude is equal to 1 / 2 and the phase is equal to
+45°. The magnitude in decibels (dB) is found by Equation (7). At the cutoff
frequency ωo, the magnitude in dB is equal to -3dB.
100
dB
0
Degree
0 | H(ω) | in dB
-3 dB
Arg H(ω)
20
50 -45°
40
2 60 0
1 10 100
ωo 1 .10
3
1 .10
4 1 10 100 ωo 1 .10
3
1 .10
4
1 4
Rad/Sec Rad / Sec
Figure 7(b): The magnitude and phase spectrums for a first order highpass R-C filter.
Below the cutoff frequency, the frequency components are attenuated at a rate of
20dB per decade (Figure 7(b)). Above the cutoff frequency ωo, the response of the
filter is one and these frequency components remain unchanged.
The response to a step input can be found by taking the inverse Laplace transform
of
 s

1  ωo   ωo 
 1

Vout(s) = s . s = , (14)
 + 1  s + 1
ωo  ωo 
6- 8
with the Laplace transform of a unit step u(t) equal to 1 / s and is given as
Vout(t) = e-t/RC u(t) (15)
A plot of Equation (15) is given in Figure 8.
Vout(t)
0.5
0
0 Time
Figure 8: The step response to a first order highpass R-C filter
Second Order Filters

Figure 9 shows the circuit used to implement a buffered version of a second order
lowpass filter. This circuit uses both positive and negative feed back to achieve a
second order system. The transfer function of this filter is given as
Vout(s) K . ωo2
H(s) = Vin(s) = (16)
ωo
s2 + Q s + ωo2
where the cutoff frequency ωo (-3 dB point) is given by
1
ωo2 = C1 C2 R1 R2 , (17)
the gain K by
Rb
K = Ra + 1 , (18)
and the Quality factor Q by
6- 9
1 R2 C21/2 R1 C21/2 R1 C11/2
=  
Q R1 C1 +   + (1-K) R2 C2 (19)
R2 C1  
Figure 9: The circuit diagram for a second order lowpass filter.
If both R1 and R2 are is set equal to R and C1 and C2 are set equal to C then the
cutoff frequency ωo reduces to
1
ωo = R C , (20)
the quality factory becomes
1
Q=3−K , (21)
or
1
K=3-Q , (22)
and the gain remaining the same as Equation (18)
Rb
K = Ra + 1 , (23)
A closer look at Equation (21), with R1 = R2 = R and C1 = C2 = C shows that the

quality factor and the gain K are no longer independent and a directly coupled by
Equations (21) or (22). In designing this second order filter, highest priority is that
6- 10
the desired Q must first be met. If the gain K, does not meet the desired gain as set
forth by the design requirement, it is much easier to add an additional amplifier
stage to increase the overall gain or to add a voltage divider to reduce the overall
gain to the desired level. Figure 10 shows the circuit diagram for the second order
lowpass filter with R1 =R2 =R and C1 = C2 = C.
Figure 10: The circuit diagram for a second order lowpass

with R1 = R2 = R and C1 = C2 = C filter.
The frequency response of this filter can be found by substituting s = jω into

Equation (16), giving
Vout(ω) K . ωo2
H(ω) = = (24)
Vin(ω) ωo 2
Q j ω + (ωo - ω )
2
The magnitude response is found from Equation (24) as
K . ωο2
| H(ω) | = f(Vout(ω),Vin(ω)) =
ωo2 2
ω + (ωo2 − ω2)2
Q2
(25)
At ω = ωo, Equation (25) reduces to
6- 11
Vout(ωο)
H(ωο) = = -j . K . Q (26)
Vin(ωο)
The magnitude of | H(ωo) | is equal to K . Q and the phase is -90°. At resonance,

the gain of the filter increased by the quality factor Q. Figure 11 gives the lowpass
filter response for various quality factor Q values with the value of K set equal to
one for all cases.
20 20
dB dB
0 0
Q = 0.5 Q=1
20 20
40 40
1 10 100 1 .10
3
1 .10
4 1 10 100 1 .103 1 .104
Rad / Sec Rad / Sec
(a) (b)
20 20
dB dB
0 0
Q=2 Q=5
20 20
40 40
3 4 3 4
1 10 100 1 .10 1 .10 1 10 100 1 .10 1 .10
Rad / Sec Rad / Sec
(c) (d)
Figure 11: The magnitude spectrum for the second order lowpass filter
given in Equation (16) for various quality factor values.
The attenuation factor for a second order filter is -40 dB / decade as compared for
a first order system of -20 dB / decade. The rate of attenuation is twice as fast as a
first order lowpass filter. As the Q increases, the increase in the gain of the filter
response at ω = ωo can be easily seen in Figure 11 (comparing Figure 11a to Figure
11b).
Applying a step input of u(t) with a corresponding Laplace transform for u(t) of 1
/ s yields
6- 12
1 K . ωo2
Vout(s) = s (27)
ωo
s2 + Q s + ωo2
Using partial fraction expansion, the standard Laplace tables, and some algebra
gives the step response for a second order lowpass filter as described by Equation
(16) as
 e-ωo . t / (2Q)  1 
Vout(t) = K1- sin 1 - 4Q2 ωo t +  , (28)
1  
 1 - 4Q2 
 
where
 1- 2
1
θ =
 4Q 
( 2 )
atan
 1  = atan 4Q - 1 (29)
 2Q 
Figure 12 shows the step response for a fixed cutoff frequency ωo and for various
quality factors, Q. These factors correspond to the same quality factors used to
generate the magnitude spectrums given in Figure 11, except that for these plots, K
is not set to one, but set using Equation (22). For Q > 0.5 there is ringing present.
The frequency of this ringing ωr is given by
1
ωr = 1- 2 ωo (30)
4Q
which is different from the resonance frequency ωo. Note, that the increase in
ringing and the amount of overshoot in the waveform are due to an increase value
of Q. For Q = 0.5 there is no ringing and no overshoot. Actually, for Q <0.5 the
second order transfer function of Equation(16) can be factored into two real poles
and can be implemented using the two first order lowpass filters shown in Figure
4. The percent overshoot given in the step responses is defined as
Vpeak - Vfinal
% overshoot = Vfinal 100% , (31)
where Vpeak is the peak voltage in the step response and Vfinal is final value of
the step response after the ringing has decayed to zero as shown in Figure 12. In
summary, the higher value of Q the higher the overshoot. J. C. Daly from the
Electrical and Computer Engineering at the University of Rhode Island gives the
percent overshoot as a function of Q as
6- 13
π
% overshoot = e - 100% (32)
4Q2 - 1
1.5 3
Vpeak
1 2
Vfinal
0.5 1
0 0
0 0.00 2 0.00 4 0 0 .0 0 2 0 .0 0 4
(a) (b)
4 6
0 0
0 0 .0 0 2 0 .0 0 4 0 0 .0 02 0 .0 04
(c) (d)
Figure 12: The step response for the second order lowpass filter
given in Equation (16) for various quality factor values. For
(a) Q = 0.5, (b) Q = 1, (c) Q = 2, and (d) Q = 5.
Figure 13 gives the circuit used to implement a buffered version of a second order
highpass filter for R1 = R2 = R and C1 = C2 = C. The only difference between this
filter and the lowpass version of this filter is that the R's and the C's are swapped.
The transfer function of this filter is given as
K . s2
Vout(s) = , (33)
ωo
s2 + Q s + ωo2
where
1
ωo = R C , (34)
6- 14
1
Q=3−K , (35)
or
1
K=3-Q , (36)
and
Rb
K = Ra + 1 . (37)
which are the same equations as Equations (20) - (23), repeated here for clarity.
Figure 13: The circuit diagram for a second order highpass

with R1 = R2 = R and C1 = C2 = C filter.
The frequency response of this filter can be found by substituting s = jω into

Equation (16)
-K . ω2
H(ω) = f(Vout(ω),Vin(ω)) = (38)
ωo
Q jω + (ωo − ω )
2 2
The magnitude response is found from Equation (24) as
6- 15
K . ω2
| H(ω) | = f(Vout(ω),Vin(ω)) =
ωo2 2
ω + (ωo2 − ω2)2
Q2
(39)
At ω = ωo, Equation (25) reduces to
Vout(ωο)
H(ωο) = =j.K.Q (40)
Vin(ωο)
The magnitude of | H(ωo) | is equal to K . Q and the phase is 90°. At resonance,

the gain of the filter increased by the quality factor Q. This is the same gain factor
as for the second order lowpass filter but the difference is the phase is +90° for the
high pass and -90° for the lowpass filter. Figure 14 gives the highpass filter
response for various quality factors values with the value of K set equal to one for
all cases.
Applying a step input of u(t) with a corresponding Laplace transform of u(t) as 1 /

s yields
1 K . s2 K.s
Vout(s) = s = (41)
ωo ωo
s2 + Q s + ωo2 s2 + Q s + ωo2
Using standard Laplace tables and some algebra gives the step response for a
second order highpass filter as described by Equation (33) as
Vout(t) = K e-wo . t / (2Q) .
  1  1  1 
cos 1- 2 wo t − sin 1- 2 wo t   (42)
  4Q  4Q2 - 1  4Q 
The Butterworth Filter

The Butterworth filter offers the ability to control the rate at which the filter changes
from passing frequency components to attenuating them. In addition, this filter
linearly changes from the pass band to the attenuation band without the presence of
the ripples that are typically found in some of the other filters. This filter is known
as a maximumly flat filter.
The Butterworth lowpass filter is described by
1
H(ω) = , (43)
 ω  2N
1+ 
 ωο
6- 16
where N is the order of the filter and ωo is the cutoff frequency or -3 dB attenuation
point. As N increases, the transition band at which the filter’s frequency response
changes from the pass band to the attenuation band decreases. For N = ∞, the
lowpass Butterworth filter becomes the ideal lowpass filter with zero transition
band. The rate of attenuation is -N . 20 dB / decade. For ω = 0, the response of
this filter is unity and at ω = → ∞, the response is zero. Similar to the Butterworth
lowpass filter, the Butterworth highpass filter is defined as
1
H(ω) = , (44)
ωο 2N
1+ 
 ω
For ω = 0, the response of this filter is zero and for ω → ∞ , the response is one.
20
dB
dB Q = 0.5 0 Q=2
0
20
20
40 40
1 .1 0 1 .1 0 1 .10 1 .10
101 0 3 4 10 3 4
1 100 1 10 100
Rad / Sec Rad / Sec
(a) (b)
20
0
dB dB
0
Q=1 Q=5
0
20
20
40 40
0
1 .1 0 1 .1 0
3 4
1 .1 0 1 .1 0
10 3 4 10
1 10 1 00 1 10 100
Rad / Sec Rad / Sec
(c) (d)
Figure 14: The magnitude spectrum for the second order highpass filter
given in Equation (16) for various quality factor values.
6- 17
3 3
2 2
1 1
0 0
1 1
0 0.001 0.002 0.003 0.004 0 0.001 0.002 0.003 0.004
(a) (b)
2
2
2 4
0 0.001 0.002 0.003 0.004 0 0.001 0.002 0.003 0.004
(c) (d)
Figure 15: The step response for the second order highpass filter,
given in Equation (33) for various quality factor values. For
(a) Q = .5, (b) Q = 1, (c) Q = 2, and (d) Q = 5.
To design a Butterworth filter, the locations of the poles are required. Most tables
that give the Butterworth poles are computed with a normalized cutoff frequency
of ωo = 1. Table 1 gives the poles for up to a 7th order filter factored into first and
second order terms for a normalized frequency ωo = 1. The advantage of this table
is that a high order filter can be implemented by cascading several second order
filters with a first order filter. For example, if N = 6, there will three second order
filter stages and no first order stage.
The steps involved in designing an Nth order Butterworth lowpass filter is as

follows.
1. Pick the order N of the filter and the desired filter gain Kd (the desired
gain of the overall filter) and cutoff frequency ωo.
2. Using Table 1, obtain the normalized factored poles ωo = 1 for the given
N.
6- 18
3. For N odd, there will be an (s + 1) pole. This can be easily implemented
with the first order lowpass filter given in Figure 4. Pick C and find R
from
1
R= (45)
C ωo
4. For each second order section (Figure 10) and Equation (16), the K and
Q must be found. This is done by using the corresponding constant in
front of the s term in the second order pole equation. This term is equal
to ωo / Q. But ωo is equal to 1 so this term is simply equal to 1 / Q.
Table 1: The factored Poles for a Butterworth Filter.

N Second order Factored Butterworth filter Normalized Poles
(ωo = 1)
1 (s + 1)
2 (s2 + 1.414s + 1)
3 (s + 1) (s2 + s + 1)
4 (s2 + 0.7654s + 1) (s2 + 1.847s + 1)
5 (s +1) (s2 + 1.618s + 1) (s2 + 0.618s + 1)
6 (s2 + 0.5176s + 1) (s2 + 1.414s + 1) (s2 + 1.9319)
7 (s + 1) (s2 + 0.445s + 1) (s2 + 1.247s + 1) (s2 + 1.8019s + 1)
5. Using
1
K=3-Q , (46)
solve for K given Q from step 4 and with
Rb
K = Ra + 1 . (47)
Pick Ra or Rb and then solve Equation (47) for the other resistor (Ra or
Rb).
6. Pick C and solve for R using
1
R= (48)
C ωo
7. Since K and Q are dependent, compute the actual Ka of total gain

implemented for all stages. The total actual gain is implemented in the
design is given by
Ka = K1 . K2 . K3 . K4 …. , (49)
6- 19
where K1, K2, K3 etc. are the actual gains used in each of the first and
second order stages as given by Equation (37).
8. If the actual implemented gain Ka < Kd (the original desired gain) then
an additional gain stage as shown in Figure 16 is required with a gain of
Kd Ry
Kg = Ka = Rx + 1 . (50)
Pick Rx or Ry and solve for the other resistor.
Figure 16: A non-inverting amplifier with a gain of Kg.
9. If the original desired gain Kd is less than the actual implemented gain
Ka, then a buffered voltage divider network as shown in Figure 17 will
be needed to reduce the total gain
Kd Rx
Kg = Ka = Rx + Ry . (51)
Pick Rx or Ry and solve for the other resistor.

10. The design is now complete.
11. To design a highpass Butterworth filter, all of the steps are identically
the same as for the lowpass filter except the R's and C's are interchanged
and Figure 7 applies for the first order highpass filter and Figure 13
applies for the second order highpass filter.
6- 20
Figure 17: A buffered voltage divider.
Procedure:
General Setup:
correct.
cutoff frequency, or quality factor.
the data overlaps.
8. The square wave used with laboratory experiment is assumed to have a 50% duty
cycle.
First order Filters:

1. Build a first order lowpass filter using the circuit given in Figure 4 with ωo =
10,000 rad / sec (minimum filter resistor should be 10kΩ).
2. Applying a 1 volt peak sine wave input with frequencies varying from 100 Hz
to 100 kHz, plot its magnitude spectrum. Measure at least 3 points per decade
1X, 2X, and 5X.
3. Determine the attenuation factor in dB / Decade.
4. Apply a 1-volt peak-to-peak square wave input with a frequency of 200 Hz.
Measure and plot, using an oscilloscope, the step response of this filter.
5. Repeat Step 4 for square wave frequencies of 1000, 2000, and 5000 Hz.
6. Build a first order highpass filter using the circuit given in Figure 7(a) with ωo
= 10,000 rad / sec.
6- 21
7. Applying a 1 volt peak sine wave input with frequencies varying from 100 Hz
to 100 kHz, plot its magnitude spectrum. Measure at least 3 points per decade
1X, 2X, and 5X.
8. Determine the attenuation factor in dB / Decade.
10. Repeat Step 9 for square wave frequencies of 1000, 2000, and 5000 Hz.
Second order Filters

1. Build a second order lowpass filter using the circuit given in Figure 10 with ωo
= 10,000 rad / sec with Q = 2 (minimum filter resistor should be 10kΩ).
2. Applying a 2-volt peak-to-peak sine wave input with frequencies varying from
100 Hz to 100 kHz, plot its magnitude spectrum. Measure at least 3 points per
decade 1X, 2X, and 5X. What is the attenuation factor in dB / Decade?
3. Measure Vout at ω = ωo and compare this result to K . Q.
5. Measure the peak overshoot and compute the percent overshoot using Equation
(31)
6. Repeat Steps 4 and 5 for Q = 0.5 and 5. How do these oscilloscope plots
compare to Figure 12.
7. From step 6, compare the measured % overshoot to Equation (31).
8. Build a second order highpass filter using the circuit given in Figure 13 with
ωo = 10,000 rad / sec with Q = 2.
decade 1X, 2X, and 5X. What is the attenuation factor in dB / Decade?
10. Measure Vout at ω = ωo and compare this result to K . Q.
12. Repeat Step 11 for Q = 0.5 and 5. How do these oscilloscope plots compare to
Figure 15.
Butterworth Filter
13. Build a fifth order Butterworth filter using the steps described in the laboratory
experiment with ωo = 10,000 rad / sec and Kd = 5. The attenuation factor
should be -100 dB / Decade. Make sure that the R’s and C’s are easily
swappable (minimum filter resistor should be 10kΩ).
14. Applying a 2 volt peak-to-peak sine wave input with frequencies varying from
decade 1X, 2X, and 5X.
15. Measure Vout at ω = ωo.
16. Apply a 2-volt peak-to-peak square input with a frequency of 200 Hz.
17. Compare the measure low frequency gain to the desired gain of 5.
6- 22
18. Swapping the R's and the C's in the lowpass Butterworth filter design, build a
5th order highpass Butterworth filter with a desired gain Kd of 5.
decade 1X, 2X, and 5X.
20. Measure Vout at ω = ωo.
21. Apply a 2-volt peak-to-peak square wave input with a frequency of 10 kHz.
22. Compare the measured high frequency gain to the desired gain of 5.
experiment. Include in your report;
5. The procedures.
experiment.
13. Make sure to include comparisons with simulated results and actual results.
14. Include the comparison of the measure percent overshoot with Equation (31).
15. Include all time plots.
16. Include all frequency plots.
17. Include the designs steps used to design the 5th order Butterworth filter. List all resistor
and capacitor values used in a table.
18. How are the time and frequency domain signals related?
6- 23
EXPERIMENT #7
Voltage Comparators and Schmitt Triggers
Goals:
To introduce the concepts of using an operational amplifier as a voltage comparator. The
theory of voltage comparator will be presented along with the design of several comparator
circuits. The Schmitt trigger comparator will be presented.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
4034B oscilloscope:
Equipment:
Triple Power supply
Multimeter
TL084 Operational Amplifier
LM393 Comparator
Pre-laboratory:
with: Mulitsim, Workbench or LTSpice IV simulate the various comparator
circuits.
a. Download the National Semiconductor LM393 voltage comparator datasheet and

become familiar with this part.
b. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, simulate the
comparator circuit of Figure 3.
c. Use a 10 volts peak 500 Hz triangle waveform for the input Vin (DC offset =0 volts).
d. Plot Vout as a function of time for Vref = 1volt.
e. Determine the voltage Vin where Vout switches from +Vcc to -Vcc.
7- 1
f. Repeat Steps b - e for Vref = 2 volts, 5 volts and 8 volts.
g. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, simulate the
h. Use a 10 volts peak 500 Hz triangle waveform for the input Vin (DC offset =0 volts).
i. Plot Vout as a function of time for Vref = 1 volt.
j. Determine the voltage Vin where Vout switches from +Vcc to -Vcc.
k. Repeat Steps g - j for Vref = 2 volts, 5 volts and 8 volts.
l. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, simulate the
m. Let R2 =10k and R1 =1k.
n. Use a 5 volts peak 500 Hz triangle waveform for the input Vin (DC offset =0 volts).
o. Determine the voltage Vin where Vout switches from +Vcc to -Vcc.
p. Plot Vout as a function of time.
q. Determine Vout max and Vout min. Replace +Vcc with Vout max and -Vcc with
Vout min in Equations (22) - (25).
r. Compare the Equations (22) - (25) with Step o.
s. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, simulate the
t. Let R2 =10k and R1 =1k.
u. Use a 5 volts peak 500 Hz triangle waveform for the input Vin (DC offset =0 volts).
v. Determine the voltage, Vin, where Vout switches from +Vcc to -Vcc.
w. Plot Vout as a function of time.
x. Determine Vout max and Vout min. Replace +Vcc with Vout max and -Vcc with
Vout min in Equations (30) - (33).
y. Compare the Equations (30) - (33) with Step v.
z. Simulate the pulse width modulator circuit of Figure 14.
aa. Use a 0 to 10 volt 1000 Hz sawtooth waveform. Vary Vin from 0 to 10 volts (0, 1, 2,
5, 8, and 10 volts) and measure T1 the time Vout = +Vcc.
bb. Plot T1 versus Vin.
cc. Compare Step bb to Equation (36) with T=0.001 sec and K 10 volts.
Discussion:
Voltage comparison is commonly required in electronic circuit design when there
is a need to compare two input voltages. Figure 1 shows the circuit diagram for a
voltage comparator. It is the same diagram as an operational amplifier and in many
cases an operational amplifier can be used as a voltage comparator. When an
operation amplifier is used as a comparator, care must be taken so that the input
does not exceed its common mode input range.
I- +Vcc
+
V Vout
-
V
I+ -Vcc
Figure 1: A circuit diagram of a typical voltage comparator
7- 2
Voltage comparators require either a dual power supply like an op-amp or a single
supply. The type of power supply that is required depends on the voltage range of
the voltage comparator's output. The output voltage Vout for a comparator is
Va for V+ > V-

Vout =  (1)
Vb for V+ < V-
Figure 2 gives a diagram of Vout versus Vin. The output has two possible states.
State 1: for V+ > V- and the second state for V+ < V-. As with an op-amp the
current flowing in the two inputs I+ and I- can be assumed to be zero.
When an op-amp is used as a voltage comparator, the open loop equation of the op-
amp (from laboratory Experiment #1) is
Vout = Aod (V+ - V-) , (2)
where Aod is the open loop gain of the op-amp. Since Aod is very large, with
Vout
(V+ - V-) = Aod (3)
and with Vout bounded between the two powers supply voltages:
-Vcc ≤ Vout ≤ +Vcc , (4)
if V+ > V- then Vout must be equal +Vcc, the positive output rail of the op-amp.
But, if V+ < V-, then Vout = -Vcc, the negative rail of the op-amp. As mentioned
earlier V+ and V- must be maintained within the allowed common mode input of
the op-amp.
Vout = Va
V+< V- V+ > V-
Vout = Vb
Figure 2: Vout versus Vin for a voltage comparator.
Figure 3 is a common comparator circuit with Vin connected to V+ with a dual

power supply for the comparator of +Vcc and -Vcc. Using the voltage divider
equation, V- is given by
7- 3
R1
V- = +Vcc R1 + R2 (5)
and
+Vcc R1
for Vin > +Vcc R1 + R2
Vout =  R1 (6)
-Vcc for Vin < +Vcc R1 + R2
Figure 4 is a graph of Vout versus Vin, showing the transition of Vout from +Vcc
to - Vcc when
R1
Vin = +Vcc R1 + R2 . (7)
Since the voltage divider circuit of Figure 3 does nothing more than produce a
reference voltage that sets the value of Vin that will result in Vout changing states,
this voltage divider circuit can be replaced by the label Vref, which can be called
the reference voltage.
Figure 3: A simple comparator circuit.
Vref
Figure 3: A simple comparator circuit.
Vout = +Vcc
Vin
+Vcc R1
Vout = -Vcc R1 + R2
Figure 4: Vout versus Vin for the comparator circuit of Figure 3.
7- 4
Changing the inputs to the voltage comparator circuit given in Figure 3 as shown
in Figure 5 produces the output of
Vout = +Vcc for Vin < Vref

Vout = Vout = 0 (8)
 for Vin > Vref
Vref
Figure 5: Another comparator circuit.
Figure 6 gives its corresponding plot of Vout versus Vin. The difference in the two
comparator circuits of Figures 3 and 5 is the polarity of the output with respect to
the input Vin. For figure 3, Vout = + Vcc for
R1
Vin > +Vcc R1 + R2 , (9)
while for the comparator circuit for Figure 5, Vout = + Vcc for
R1
Vin < +Vcc R1 + R2 . (10)
Vout = +Vcc +Vcc R1

R1 + R2
Vin
Vout = -Vcc
Figure 7 gives Vout as a function of time for the comparator circuit of Figure 3.
During the time Vin > Vref, Vout = +Vcc else Vout = -Vcc.
7- 5
Vin
Vref
0
0
Time
Vout
+Vcc
0
Time
-Vcc
Figure 7: Vout as a function of time for the comparator circuit of Figure 3.
If the LM393 comparator as shown in Figure 8, is used to implement the comparator

circuit given in Figure 3, then
+Vcc for Vin > Vref

Vout = 0 for Vin < Vref , (11)

where the output voltage Vout is defined as Va = +Vcc and Vb = 0. The output of
the LM393 comparator is an open collector transistor and it needs a pull-up resistor
(typically 2k to 4k). The only requirement in picking the value of the pull-up
resistor is the maximum current for the output transistor cannot exceed 10
milliamps. Figure 9 gives the output as a function time for the comparator circuit
for Figure 3 using the LM393 comparator.
Figure 8: A simple comparator circuit using the LM39
Figure 8: A simple comparator circuit using the LM393 comparator.
7- 6
Vin
Vref
0
0
Time
Vout
+Vcc
0
0 Time
Figure 9: Vout as a function of time for the comparator circuit of Figure 3

using an LM393 comparator.
Consider the comparator circuit given in Figure 10. Starting with
+Vcc for V+ > V-

Vout =  . (12)
-Vcc for V+ < V-
VREF
Figure 10: A comparator circuit with hysteresis (Schmitt Trigger).
But V- = Vref,
+Vcc for V+ > Vref

Vout =  . (13)
 -Vcc for V+ < Vref
7- 7
Solving for V+ gives
Vout -Vin R1 . Vout + R2 .Vin

V+ = Vin + R1 R1 + R2 = R1 + R2 . (14)
Substituting Equation (14) into Equation (13) for the case when Vout = +Vcc yields
R1 . Vout + R2 .Vin
Vout = +Vcc when R1 + R2 > Vref . (15)
Solving Equation (15) for Vin gives
R1  R1
Vout = +Vcc when Vin > Vref  R2 +1 - Vout R2 . (16)
 
or substituting for Vout = +Vcc
R1  R1
Vout = +Vcc when Vin > Vref  R2 + 1 - Vcc R2 . (17)
 
Using the same approach for when Vout = -Vcc gives
R1 . Vout + R2 .Vin
Vout = -Vcc when R1 + R2 < Vref . (18)
Substituting Vout with -Vcc and solving for Vin gives
R1  R1
Vout = -Vcc when Vin < Vref  R2 +1 + Vcc R2 . (19)
 
If Vout = +Vcc then by Equation (17) Vout switches to -Vcc when
R1  R1
Vout (+Vcc→ -Vcc) when Vin < Vref  R2 +1 - Vcc R2 . (20)
 
and if Vout = -Vcc then by Equation (19) Vout switches to +Vcc when
R1  R1
Vout (-Vcc→ +Vcc) when Vin > Vref  R2 +1 + Vcc R2 . (21)
 
For the special case when Vref = 0 Equations (17) and (19) reduce to
𝑅𝑅1
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = +𝑉𝑉𝑉𝑉𝑉𝑉 when 𝑉𝑉𝑉𝑉𝑉𝑉 > +𝑉𝑉𝑉𝑉𝑉𝑉 . (22)
𝑅𝑅2
and
7- 8
𝑅𝑅1
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = +𝑉𝑉𝑉𝑉𝑉𝑉 when 𝑉𝑉𝑉𝑉𝑉𝑉 > −𝑉𝑉𝑉𝑉𝑐𝑐 . (23)
𝑅𝑅2
If Vout = +Vcc, then by Equation (22) Vout switches to -Vcc when
R1
Vout (+Vcc→ -Vcc) when Vin < -Vcc R2 . (24)
R1
Vout (-Vcc→ +Vcc) when Vin > +Vcc R2 . (25)
Figure 11 gives a plot of Vout versus Vin for the case when Vref = 0 volts. Note
the hysteresis that exist between transitioning Vout from -Vcc to +Vcc and from
+Vcc to -Vcc of
2. R1
Hysteresis value = Vcc R2 . (26)
This type of comparator circuit with hysteresis is commonly called a Schmitt

Trigger.
Vout = +Vcc
+Vcc R1
R2
Vin
-Vcc R1
R2
Vout = -Vcc
Figure12 gives another commonly used Schmitt trigger circuit. Using the same
approach in solving the Schmitt trigger circuit given in Figure 8
Consider the comparator circuit given in Figure 12. Starting with
+Vcc for V+ > V-

Vout =  . (27)
 -Vcc for V+ < V-
7- 9
Figure 12: A comparator circuit with hysteresis (Schmitt Trigger).
But V- = Vin,
+Vcc for V+ > Vin

Vout =  . (28)
-Vcc for V+ < Vin
Solving for V+ gives

R1
V+ = Vout R1 + R2 . (29)
Substituting Equation (29) into Equation (28) for the case where Vout = +Vcc
R1
Vout = +Vcc when Vin < +Vcc R1 + R2 . (30)
For the case when Vout = -Vcc, Vout becomes
R1
Vout = -Vcc when Vin > -Vcc R1 + R2 . (31)
If Vout = +Vcc then by Equation (30) Vout switches to -Vcc when
R1
Vout (+Vcc→ -Vcc) when Vin > +Vcc R1 + R2 . (32)
R1
Vout (-Vcc→ +Vcc) when Vin < -Vcc R1 + R2 . (33)
Figure 13 gives Vout versus Vin for the Schmitt trigger circuit given in Figure 12.
7- 10
R1
-Vcc Vout = +Vcc
R1 +R2
Vin
R1
+Vcc
R1 +R2
Vout = -Vcc
Figure 13: Vout versus Vin for the Schmitt Trigger circuit of Figure 12.
As illustrated in laboratory experiment #4, a comparator can be used as a pulse

width modulator as shown in Figure 14. Defining Vout as
+Vcc for Vin > Vx

Vout = 0 for Vin < Vx , (34)

Vin V+
Vout
V-
Vx
0 Sawtooth
T Waveform
K
Vin
T1
Figure 14. A block diagram of a pulse width modulator.
But, the sawtooth waveform over one period T can written as
t
Vx = K T for 0 ≤ t < T (35)
As long as Vx < Vin Vout will be equal to +Vcc. The point in time (T1) when Vx
> Vin, Vout goes to zero as shown in Figure 15. Solving Equation (35) for t and
setting Vx = Vin give the time T1 as
Vin
T1 = T K for 0 ≤ Vin < K . (36)
7- 11
Volts
T
1
Va
Vb
T Time
Figure 15: An example Vout from the pulse width modulator given in Figure 12.
Procedure:
General Setup:
2. Download the datasheet for the LM393 comparator. This will be needed to
obtain the pin-out of the comparator. When comparing datasheet data values to
correct.
current.
the data overlaps.
Comparator Circuits
1. Download the National Semiconductor LM393 voltage comparator datasheet
and become familiar with this part.
2. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, build
the comparator circuit of Figure 3.
3. Use a 20 volt peak-to-peak 500 Hz triangle waveform for the input Vin (DC
offset =0 volts).
4. Plot Vout as a function of time for Vref = 1volt using an oscilloscope.
5. Determine the voltage Vin where Vout switches from +Vcc to -Vcc.
6. Repeat Steps 3 - 5 for Vref = 2 volts and 8 volts.
7- 12
offset =0 volts).
9. Plot Vout as a function of time for Vref = 1volt using an oscilloscope.
11. Repeat Steps 8 - 10 for Vref = 2 volts and 8 volts.
the comparator circuit of Figure 10 with Vref = 0 volts.
13. Let R2 =10k and R1 =1k.
offset =0 volts).
16. Plot Vout as a function of time using an oscilloscope.
17. Determine Vout max and Vout min from the oscilloscope traces. Replace
+Vcc with Vout max and -Vcc with Vout min in Equations (22) - (25).
18. Compare the Equations (22) - (25) with Step 15.
20. Let R2 =10k and R1 =1k.
offset =0 volts).
23. Plot Vout as a function of time using an oscilloscope.
24. Determine Vout max and Vout min from the oscilloscope traces. Replace
+Vcc with Vout max and -Vcc with Vout min in Equations (30) - (33).
25. Compare the Equations (30) - (33) with Step 22.
26. Repeat steps 2-5 and steps 7-10 using the LM393 comparator with around a
2k pull-up resistor.
 For the comparator it is necessary to use a 10 volt peak-to-peak 500 Hz
triangle waveform for the input Vin with a DC offset = 5 volts (i.e. the
triangle wave is from 0 to 10 V, rather than from -10 to 10 V). Use this in
place of the triangle wave described in steps 3 and 8.
27. Build the pulse width modulator circuit of Figure 14 (using the LM393). Do
not forget the pull-up resistor.
28. Use a 0 to 10 volt 1000 Hz sawtooth waveform. Vary Vin from 0 to 10 volts
(0, 2, 4, 8, and 10 volts) and measure T1 the time Vout = +Vcc.
29. Plot T1 versus Vin.
30. Compare Step 29 to Equation (36) with T=0.001 sec and K = 10 volts.
5. The procedures.
7- 13
experiment.
7- 14
EXPERIMENT #8
Oscillators and Waveform Generators
Goals:
To introduce the concepts of using an operational amplifier as an oscillator to produce an
output waveform. The Schmitt trigger comparator will be used to produce a square wave
and a triangle waveform.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
4034B oscilloscope:
Equipment:
Triple Power supply
Resistors available in the laboratory (use a minimum of 1k resistors)
Multimeter
TL084 Operational Amplifier
Pre-laboratory:
with: Mulitsim, Workbench or LTSpice IV simulate the various oscillator and
waveform generator circuits.
a. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, design and
simulate the phase shift oscillator circuit of Figure 1 (use a minimum of 10 kΩ for
resistors). Set ωo = 5,773 rad / sec. Adjust R2 until oscillation occurs (somewhere
above 8 . R). Make sure to run the simulation for a long enough time.
b. From the output waveform determine the frequency of oscillation and the peak-to-
peak value.
c. Increase R2 to 15 . R and repeat step b. Discuss the difference observed in-between
steps b and c.
8- 1
d. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, design and
simulate the Wien-bridge oscillator circuit of Figure 3. Set ωo = 10,000 rad / sec.
Adjust R2 until oscillation occurs (somewhere above 2 . R1). Make sure to run the
simulation for a long enough time.
e. From the output waveform determine the frequency of oscillation and the peak-to-
peak value.
f. Increase R2 to 8 . R1 and repeat step e. Discus the difference observed in between
steps e and f.
g. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, design and
simulate the Schmitt trigger oscillator circuit of Figure 5. Set fo = 1000 Hz. Make
sure to run the simulation for a long enough time.
h. Obtain waveforms for Vout, V-, and V+. Determine the frequency of oscillation and
the peak-to-peak value of Vout.
i. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, design and
simulate the triangle-square wave waveform generator circuit of Figure 7. Set fo =
1000 Hz. Make sure to run the simulation for a long enough time.
j. Obtain waveforms for Vout and Vx. Determine the frequency of oscillation and the
peak-to-peak value of Vout.
Discussion:
Oscillators and waveform generators are commonly used to generate sine wave,
triangle wave and square wave signals used as input sources to various types of
electronic circuits. Figure 1 shows the circuit diagram for a Phase Shift Oscillator
Depending on R2 this oscillator can produce either a sine wave or square wave
output. To analyze this circuit the feedback loop is opened and its transfer
function is found from its input, all the way back, to its output.
Figure 1: A circuit diagram for a phase shift oscillator.
Figure 2 shows the feedback loop open at point A. The goal is to find the output
Y as a function of the input X. Starting at X, the transfer function from X to X1 is
X1(s) RCs
=
X(s) RCs + 1 . (1)
8- 2
Since the next stage (U2) is identically the same as the fist stage (U3), the transfer
function from X2 to X1 is
X2(s) RCs
X1(s) = RCs + 1 . (2)
A Y
X
X1 X2
Figure 2: The phase shift oscillator with its loop feedback open at point A.
The transfer function for the final stage (U1) is given as
Y(s) -R2 -R2 Cs

X2(s) = =
1 RCs + 1 . (3)
R + sC
The loop feedback is then given as
Y(s) X1(s) X2(s) Y(s)

X(s) = X(s) X1(s) X2(s) . (4)
Combine Equations (1), (2) and (3) together in Equation (4) gives the total loop
feedback transfer function of
Y(s) RCs RCs -R2 Cs

=
X(s) RCs + 1 RCs + 1 RCs + 1 (5)
or
Y(s) -R2 R2C3s3 -R2  RCs 3

X(s) = (RCs + 1)3 = R RCs + 1 . (6)
Substituting jω for s gives
Y(jω) -R2  RCjω 3

=   . (6)
X(jω) R RCjω + 1
8- 3
For this circuit to oscillate, the feedback must be positive feedback with a
magnitude of 1 and a feedback phase of zero degrees:
 Y(jω) 
 =1 (8)
 X1(jω) 
and
 Y(jω) 
Arg  = 0° . (9)
 X1(jω) 
The criteria given in Equations (8) and (9) are known as the Barkhausen criteria.
Expanding Equation (6) gives
Y(jω) -R2 RCjω [RCω]2

= R . (10)
X(jω) [1 - 3(ωRC)2] + RCjω[3 - (RCω)2]
Since Equation (8) is real and contains no imaginary terms, to satisfy this criteria
Equation (10) must also be real. This occurs when
[1 - 3(ωRC)2] = 0 . (11)
Solving Equation (11) for ω gives
1
ω= = ωo . (12)
3RC
This is the frequency of oscillation and will be called ωo.
At ωo, Equation (10) reduces to
Y(jωo) -R2 -RCjωο [RCωo]2

= , (13)
X(jωo) R RCjωο[3 - (RCωo)2]
but by Equation (12)
Y(jωo) R2 1/3 1/3 R2 1

= = (14)
X(jωo) R 1/3(3 - 1/3) R 8
Before Equation (14) can be solved, another look at the Barkhausen criteria is
needed. The Barkhausen criteria state that a magnitude of 1 and 0° of phase are
required for oscillation. This is another way of stating that
8- 4
Y(jωo) Y(jωo)  Y(jωo) 
=1→  = 1 and arg  = 0° . (15)
X(jωo) X(jωo)  X(jωo) 
Substituting Equation (15) into Equation (14) and solving for R2 gives
R2 = 8 . R . (16)
Equation (16) defines the minimum value that R2 can be to obtain oscillation
based on ideal conditions. Equation (16) is for the ideal case assuming an ideal
op-amp. Typically, R2 is selected such that R2 set to be slightly greater than 8 ·
R to guarantee oscillation. R2 is usually implemented using a variable resistor
and is increased in value to the point where oscillation begins. Equations (12) and
(16) are the two design equations that are needed to design and build a phase shift
oscillator. Usually C is chosen and Equation (12) is used to find R. Then
Equation (16) is used to find the minimum value for R2.
Another common oscillator is the Wien-Bridge Oscillator, shown in Figure 3,

which can be used to generate sine or square waves, depending on the gain. The
same approach will be used to analyze this oscillator that was used for the phase
shift oscillator. Figure 4 shows Wien-bridge with the loop feedback opened.
Figure 3: The Wien-bridge oscillator.
Point Y can be written in terms of X1 as
Y(s) R2
X1(s) = R1 + 1 (17)
and X1 in terms of X as
8- 5
R
X1(s) RCs + 1 RCs
X(s) = R 1 + RCs = (RCs)2 + 3RCs +1 . (18)
RCs + 1 + Cs
X1 Y
A
Figure 4: The Wien-bridge oscillator with a loop feedback opened at A.
Combining Equations (17) and (18) gives the transfer function of the loop
feedback as
Y(s) R2  RCs

X(s) = R1 + 1 (RCs)2 + 3RCs +1 . (19)
Substituting jω for s gives
Y(jω) R2  RCjω R2  RCjω

= R1 + 1 =  + 1  .
X(jω)   (RCjω)2 + 3RCjω +1 R1  1- (RCω)2 + 3RCjω
(20)
Since Equation (20) must be real with no imaginary terms to satisfy Equations (8)
and (9), the Barkhausen criteria:
1 - (RCω)2 = 0 (21)
or
1
ω = RC = ωo , (22)
8- 6
where, ωo is the frequency of oscillation. Substituting ω =ωo into Equation (20)
gives
Y(ωo) 1 R2 
=  + 1 . (24)
X1(ωo) 3 R1 
Since to satisfy the Barkhausen criteria, the phase of Equation must be 0° and the
magnitude is 1 or
1 R2 
3 R1 + 1 = 1 . (23)
Solving for R2 gives
R2 = 2 . R1 . (25)
Equation (25) defines the minimum value that R2 can be to obtain oscillation
based on ideal conditions. Equation (22) is for the ideal case assuming an ideal
op-amp. Typically, R2 is selected such that R2 set to be slightly greater than 2 ·
R1 to guarantee oscillation. R2 is usually implemented using a variable resistor
and is increased in value to the point where oscillation begins. Equations (22) and
(25) are the two design equations that are needed to design and build a phase shift
oscillator. Usually C is chosen and Equation (22) is used to find R. R1 is chosen
and then Equation (25) is used to find the minimum value of R2.
Another type of oscillator or waveform generator is one that generates a square

wave output using a Schmitt trigger and an RC network. Figure 5 gives the circuit
diagram for a Schmitt trigger oscillator. The two inputs to the op-amp can be
written in terms of Vout as
R1
V+ = R1 + R2 Vout (26)
and
1
V- = RCs +1 Vout (27)
Resistors R1 and R2 form the positive feedback that is needed for a Schmitt
trigger. From laboratory experiment #7, for
R1
Vout = +Vcc when V- < +Vcc R1 + R2 . (28)
For the case when Vout = -Vcc
8- 7
R1
Vout = -Vcc when V- > -Vcc R1 + R2 . (29)
If Vout = +Vcc, then by Equation (28) Vout switches to -Vcc when
R1
Vout (+Vcc→ -Vcc) when V- > +Vcc R1 + R2 . (30)
R1
Vout (-Vcc→ +Vcc) when V- < -Vcc R1 + R2 . (31)
Equations (28) - (31) assume that Vout is a rail to rail op-amp with Vout(max) =
+Vcc and Vout(min) = -Vcc. If the maximum and minimum Vout is any other
values than +Vcc is replaced with Vout(max) and -Vcc is replaced with
Vout(min). If R1 = R2, then Equation (28) - (31) reduce to reduces to V+(s) = 1/2
Vout or +Vcc / 2 or -Vcc / 2.
Figure 5: The circuit diagram for a Schmitt trigger oscillator.
Since the output of this circuit is a square wave, this looks like a step input to the
RC network that is connected from Vout to V- terminal of the op-amp and is
given by
V-(t) = Vf + (Vi - Vf)·e-t/RC , (32)
where Vf is the final voltage the capacitor charges to and Vi is the initial voltage
on the capacitor at the time the step input occurred.
Assume R1 = R2 and the Vout = -Vcc and Vout just changes states to +Vcc, and
since Vout has been at -Vcc, the initial voltage on the capacitor will be -Vcc / 2
8- 8
(V+ = Vout / 2). At this point the capacitor starts charging to +Vcc and Equation
(32) becomes
V-(t) = +Vcc + (-Vcc / 2 - Vcc) e-t/RC = +Vcc -3 / 2 . Vcc . e-t/RC, (33)
The capacitor continues to charge to +Vcc until V- > V+ = +Vcc / 2. At this point
Vout switches states, going to -Vcc. Setting V-(t) = Vcc / 2 and solving for t
gives the total time T1 it takes the capacitor to charge to +Vcc / 2
T1 = RC . ln(3) = 1.0986 . RC . (34)
At this point Vout switches back from +Vcc to - Vcc, the capacitor starts to
charge to -Vcc with an initial voltage on the capacitor of +Vcc / 2. Substituting
these values into Equation (32) gives
V-(t) = -Vcc + (+Vcc / 2 + +Vcc) e-t/RC = -Vcc +3 / 2 . Vcc . e-t/RC, (33)
The capacitor continues to charge to -Vcc until V- < V+ = -Vcc / 2. At this point
Vout switches states, going to +Vcc again. Setting V-(t) = Vcc / 2 and solving for
t gives the total time T2 it takes the capacitor to charge to -Vcc / 2
T2 = RC . ln(3) = 1.0986 . RC . 34)
The process of charging the capacitor to +Vcc / 2 to -Vcc / 2 produces a square

wave with a period Tp
Tp = T1 + T2 = RC . 2 . ln(3) . (35)
The frequency of oscillation is then defined as
1 1 0.455
f = Tp = = . (36)
RC . 2 . ln(3) RC
Figure 5 gives a sample output showing Vout, V- and V+ as a function of time.
Another form of an oscillator using a Schmitt trigger is shown in Figure 7. This is

a triangle-square wave generator, which uses an integrator and a Schmitt trigger.
The equations that describe the Schmitt trigger are taken from Laboratory #7 and
given here as
R1
Vout = +Vcc when Vx > -Vcc R2 . (37)
and
8- 9
R1
Vout = -Vcc when Vx < +Vcc R2 . (38)
If Vout = +Vcc then by Equation (37), Vout switches to -Vcc when
R1
Vout (+Vcc→ -Vcc) when Vx < -Vcc R2 . (39)
R1
Vout (-Vcc→ +Vcc) when Vx > +Vcc R2 . (40)
V+
Vout
+Vcc
V-
V+
+Vcc / 2
V-
V+
V-
-Vcc / 2
T1 T2
-Vcc
0 Time
Figure 6: The Schmitt trigger oscillator waveforms.
But, Vx is nothing more than the integral of Vout since V1 = Vout.
t t
-1 -1
Vx(t) = RC ⌠
⌡ V1(τ) d τ + Vx(0 - )= ⌠
RC ⌡Vout(τ) d τ + Vx(0 )
- , (41)
0 0
where Vx(0-) is the initial voltage across the capacitor. Vout simply switches
between +Vcc and -Vcc. When Vout is switching from -Vcc to +Vcc this can be
modeled as a unit step with an amplitude of v1(t) = +Vcc. Substituting this value
into Equation (41) gives
8-10
t
-1 -1
Vx(t) = RC ⌠
⌡ +Vcc d τ = RC (+Vcc) . t + Vx(0-) . (42)
0
If R2 = 2 . R1, then Vout switches from -Vcc to +Vcc when Vx = +Vcc / 2 and
Vout switches from +Vcc to -Vcc when Vx = -Vcc / 2. For the case when Vout
switches from -Vcc to +Vcc, the initial voltage across the capacitor Vx(0-) =
+Vcc / 2. Substituting this value into Equation (42) gives
-1 +Vcc
Vx(t) = RC (+Vcc) . t + 2 . (43)
The Vx(t) now decreases until it reaches a value of -Vcc / 2 at which point Vout
switches to +Vcc. Setting Vout(t) = -Vcc / 2 in Equation (43) and solving for t
gives the total time, T2, for Vout = -Vcc
T2 = RC . (44)
V1
Vx
Figure 7: Triangle-square wave waveform generator.
Using Equation (41) and substituting V1(t) = -Vcc and with the initial voltage
across the capacitor Vx(0-) = -Vcc / 2 gives
-1 -Vcc
Vx(t) = RC (-Vcc) . t + 2 (45)
Equation (45) describes the case when Vout = +Vcc. At the point Vout switches
from +Vcc back to -Vcc, Vx = +Vcc / 2. Substituting this value into Equation
(45) and solving for T gives the total time T1 with Vout = +Vcc:
T1 = RC . (46)
8-11
The total period of oscillation is then defined as
Tp = RC + RC = 2 . RC . (47)
And the frequency of oscillation
1 1
f = Tp = . (44)
2 . RC
Figure 7 gives the signal waveforms for Vout and Vx. Also shown in Figure 6 are
T1 and T2.
+Vcc
Vout
+Vcc / 2
Vx
Vx
Vout
-Vcc / 2
T1 T2
-Vcc
Time
Figure 8: The Triangle-Square wave waveforms.
Procedure:
General Setup:
1. Record the model and serial number of the oscilloscope, power supply,
multimeter and function generator used in laboratory experiment.
correct.
current.
8-12
the data overlaps.
Oscillators and Waveform Generator Circuits

1. Using an op-amp with +Vcc set to +15 volts and -Vcc set to -15 volts, design
and build the phase shift oscillator circuit of Figure 1 (use a minimum of 10 kΩ
for resistors). Be certain to include bypass capacitors at the two power
supplies, of value 100µF each. Set ωo = 5,773 rad / sec. Use a resistor box for
R2. Adjust R2 until oscillation occurs (somewhere above 8 . R). Measure this
value of R2 and include it in the laboratory report.
2. From the output waveform determine the frequency of oscillation and the peak-
to-peak value. Obtain oscilloscope waveforms of Vout as a function of time.
3. Increase R2 to about 15 . R and repeat step 2. Discuss the difference observed
in between steps 2 and 3.
and build the Wien-bridge oscillator circuit of Figure 3. Be certain to include
bypass capacitors at the two power supplies, of value 100µF each. Set ωo =
10,000 rad / sec. Use a resistor box for R2. Adjust R2 until oscillation occurs
(somewhere above 2 . R1). Measure this value of R2 and include it in the
laboratory report.
5. From the output waveform determine the frequency of oscillation and the peak-
to-peak value. Obtain oscilloscope waveforms of Vout as a function of time.
6. Increase R2 to 8 . R1 and repeat step 5. Discuss the difference observed in
between steps 5 and 6.
and build the Schmitt trigger oscillator circuit of Figure 5. Be certain to include
bypass capacitors at the two power supplies, of value 100µF each. Set fo =
1000 Hz.
8. Obtain oscilloscope waveforms of Vout, V-, and V+ as a function of time.
9. Determine the frequency of oscillation the duty cycle, and the peak-to-peak
value of Vout.
10. By changing the capacitor, increase the frequency of oscillation until Vout is
no longer an acceptable square wave. Measure this frequency and include it in
the laboratory report. Obtain oscilloscope waveforms of Vout as a function of
time.
11. Disconnect R2 from ground and apply a 0 to 5 volt voltage source between the
disconnected end of R2 and ground. Determine the frequency of oscillation, the
duty cycle, and the peak-to-peak value of Vout. Obtain oscilloscope
waveforms of Vout as a function of time.
and build the triangle-square wave waveform generator circuit of Figure 7. Be
certain to include bypass capacitors at the two power supplies, of value 100µF
each. Set fo = 1000 Hz.
13. Obtain oscilloscope waveforms of Vout and Vx as a function of time.
Determine the frequency of oscillation and the peak-to-peak value of Vout.
8-13
5. The procedures.
8. All plots (oscilloscope waveforms) generated for each step.
8-14
EXPERIMENT #9
The 555 Timer
Goals:
To introduce the concepts of using the versatile LM555 timer as a monostable pulse
generator, an astable oscillator and as a pulse width modulator. The internal block
diagram of the LM555 will also be presented.
References:
Edition, 2007, ISBN: 978-0-07-252362-1.
4034B oscilloscope:
Equipment:
Triple Power supply
Resistors available in the laboratory (use a minimum of 1k resistors)
Multimeter
LM555 (NE555) Universal Timer
Pre-laboratory:
with: Multisim, Workbench or LTSpice IV simulate the various oscillator and
waveform generator circuits.
a. Using LM555 with +Vcc set to +10 volts, design and simulate the astable
oscillator of Figure 3(a) with fo = 1000 Hz and with a duty cycle of 33%.
b. Record Vout, and the Threshold Pin 6 simulated waveforms. Compare these two
waveforms to the waveforms given in Figure 4. How are they the same and how
are they different?
c. What is the frequency and duty cycle for this circuit.
d. Add a 1N5818 diode across Rb as shown in Figure 5.
e. Record Vout and the Threshold Pin 6 simulated waveforms.
9- 1
f. What is the measured frequency and duty cycle for this circuit?
g. Using LM555 with +Vcc set to +10 volts design and simulate the monostable
oscillator of Figure 6 with a pulse width of 0.5 millisecond. For V3, use a square
wave with a 50% duty cycle that goes from 0 to +Vcc / 2 with a frequency of 200
Hz.
h. Record Vout, V3, and the Trigger Pin 2 simulated waveforms. How does Vout
and Trigger Pin 2 of Step g compare to the plot given in Figure 8?
i. Using LM555 with +Vcc set to +10 volts and -Vcc set to -10 volts design and
simulate the pulse width modulator of Figure 9 with a pulse width of 0.2
milliseconds. This is the same circuit as the monostable circuit but with the
addition of a unity gain buffer and an additional signal source Vg.
j. Set V3 to a 0 to +Vcc / 2 square wave with a 50% duty cycle and a frequency of
2000 Hz.
k. Set Vg = 6.67 volts DC and measure Tp from the simulated waveform for Vout
and compare this result to what is expected from Equation (16).
l. Set Vg to a sine wave with a peak value of 3 volts and an offset of 4 volts so that
Vg varies in a sinusoidal manner from 1 volt to 7 volts.
m. Measure Vout and Vg simulated waveforms. Compare these results to that given
in Figure 10.
Discussion:
The LM555 / NE555 timer is a versatile integrated circuit that can be configured
as an oscillator, a pulse width modulator and a single, variable width, pulse
generator known as an astable oscillator or one shot. Most datasheets give many
other application of this device. Figure 1 is the pin-out for the LM555 timer and
Figure 2 gives the internal block diagram. The LM555 contains two voltage
comparators, one set-reset (RS, also SR) flip-flop (also latch or register), one
inverter and one open collector NPN transistor. The voltage divider composed of
R1, R2 and R3 set the voltage at the V- input of comparator C2 (Pin 5) to 2/3
+Vcc and the V+ input of comparator C1 to 1/3 +Vcc. The transistor Q1 (Pin 7)
is typically used as a method of discharging any timing capacitors used in any
timing circuit configurations.
Figure1: The pin-out for the LM555 timer IC.
9- 2
The set-reset flip-flop (RS-FF) is placed in a set or reset condition depending on
the R and S inputs. Table 1 gives the output Q of the RS-FF as a function of R
and S. When R = 0, S = 0, the RS-FF is in a hold state and Q does not change.
When R = 1 and S = 0, the RS-FF is in a reset state and Q goes to 0 and when R =
0, S = 1, the RS-FF is in a set state and Q = 1. The condition for R = 1, S = 1, is
not allowed. There is also the ability to externally reset the RS-FF using the
RESET NOT pin (Pin 4).
Table 1 The Next State Table for and RS-FF

R S Q Old QNew
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 X
1 1 1 X
Figure 2: Functional block diagram for the LM555 Timer
Figure 3(a) shows the LM555 timer configured as an astable oscillator (the output
indefinitely changes states between Vcc and 0). Resistors Ra, Rb, and capacitor C
form the timing network that determines the frequency of oscillation and the duty
cycle of the square wave output. Figure 3(b) gives the same astable oscillator
circuit showing also the internal functional block diagram for the LM555 timer.
Capacitor CX in Figure 3(a) is used as a bypass filter for the reference voltages
going to the two comparators C1 and C2. The capacitor is used to filter any noise
that may be present on +Vcc to maintain a constant reference voltage on V+ of C1
and V- on C2.
9- 3
(a)
CX
(b)
Figure 3: (a) The external circuit diagram of the LM555 timer configured
as an astable oscillator and (b) the same circuit showing the
internal functional block diagram of the LM555 timer.
9- 4
Assuming initially Q = 1, the transistor Q1 is off, and the initial voltage across the
capacitor is just slightly greater than 1/3 +Vcc. Since the Trigger input (pin 2)
and Threshold (pin 6) are tied together, V+ < V- of C2 and V+ < V- of C1, the
output of both C1 and C2 are 0. The RS-FF is in a hold condition maintaining Q
= 1. The capacitor C starts to charge toward +Vcc through Ra and Rb. Equation
(32) from laboratory experiment 8 gives the voltage across the capacitor as
Vpin_2(t) = Vf + (Vi - Vf)e-t/RC , (1)
where Vf is the final voltage and Vi is the initial voltage across the capacitor.
Substituting Ra + Rb for R, Vi = 1/3 +Vcc, and Vf = +Vcc gives
Vpin_2(t) = +Vcc + (-2/3 +Vcc)e-t/(Ra+Rb)C , (2)
Figure 4 shows the voltage across the capacitor C and Vout as a function on time.
The capacitor initially has a voltage 1/3 +Vcc and starts charging toward +Vcc.
The capacitor continues to charge to +Vcc until the voltage across the capacitor
reaches 2/3 +Vcc. At this point, V+ > V- of C2 and V+ < V- of C1 yielding the
output of C2 = 1 and the output of C1 = 0. This sets the RS-FF to a reset
condition changing Q = 0. The output Vout = 0, and Qnot of U1 is now 1, turning
on the transistor Q1. This starts discharging the capacitor C toward 0. When the
voltage across the capacitor goes below 2/3 +Vcc, V < V- of C2 and V+ > V- of
C1, yielding the output C2 = 0 and the output of C1 = +0. The RS-FF is now in
hold condition leaving Q = 0 of the RS-FF and the transistor Q1 on continuing to
discharge the capacitor.
+Vcc
2/3 +Vcc
1/3 +Vcc
0 T1 T2 time
Figure 4: Vout and the voltage across the capacitor C as a function of time.
9- 5
The time T1 it takes to charge to 2/3 +Vcc is found by substituting +2/3 +Vcc for
Vpin_2(t) into Equation (2) and solving for t
T1 = ln(2) . (Ra + Rb) . C . (3)
During the charge cycle the capacitor C discharges through Rb and the transistor
Q1. The voltage across the capacitor is then defined as
Vpin_2(t) = (2/3 +Vcc)e-(t - T1)/Rb C , (4)
The capacitor C continues to discharge until it reaches a voltage of 1/3 +Vcc. At

this point, V+ < V- of C2 and V+ > V- of C1, yielding the output C2 = 0 and the
output of C1 = 1. This sets the output of the RS-FF to the condition Q =1. The
transistor Q1 turns off and Vout goes to 1 starting a new cycle of oscillation. The
time it takes T2 - T1 to discharge the capacitor to 1/3 +Vcc is found by
substituting this value into Equation (4) for Vpin_2(t) and solving for t -T1, with t
= T2
T2 - T1 = ln(2) . (Rb) . C (5)
The total time period of oscillation T2 is found by adding Equations (3) and (5)
together
T2 = ln(2) . (Ra + 2 . Rb) . C (6)
The frequency of oscillation which is given by 1 / T2 is
1 1.44
f= = . (7)
ln(2) (Ra + 2 Rb) C (Ra + 2 . Rb) . C
. . .
The duty cycle which is defined as the time the output is low to the total time
period is
T2 - T1 Rb .100%
D% = T2 = . (8)
Ra + 2 . Rb
A closer investigation of Equation (8) yields that for a 50% duty cycle, Ra would
have to be zero which is not possible for the astable oscillator circuit
configuration of Figures 3(a) and (b). To build an astable oscillator with a 50%
duty cycle requires the addition of a diode, as shown in Figure 5. During charging
of capacitor C, the diode is on. Essentially Rb is in parallel with the on-state
(forward-biased) resistance of the diode, which is typically much smaller than the
resistance Rb. For the most part, this parallel combination can be considered as
zero ohms. The best diode to use in this configuration is a Schottky diode, as this
9- 6
diode has a much smaller turn-on voltage than a regular diode. Since the parallel
combination of Rb and the forward-biased diode (on) resistance is approximately
zero ohms, the capacitor only charges through resistor Ra yielding a charge time
for T1 of
T1 = ln(2) . Ra . C . (9)
When the capacitor is discharging, the diode is on and the capacitor discharges
through Rb as described by equation (4) yielding a discharge time of
T2 - T1 = ln(2) . Rb . C . (10)
The total period of oscillation is then given by adding Equations (9) and (10)
together
T2 - T1 = ln(2) . (Ra + Rb) . C . (11)
and the frequency of oscillation as
1 1.44
f= = . (12)
ln(2) . (Ra + Rb) . C (Ra + Rb) . C
The duty cycle is then given by
T2 - T1 Rb .
D% = T2 = Ra + Rb 100% (13)
If Ra = Rb, then the duty cycle reduces to 50%.
Figure 5: An astable oscillator using the LM555 timer with a 50% duty cycle.
9- 7
The LM555 timer can also be configured as a monostable oscillator generating a
single pulse of a given pulse width when triggered. Figure 6 shows the LM555
timer in a monostable configuration. Ra and C determine the pulse width. R1,
R2, C1, D1, and D2 form an input network to trigger the LM555 timer. V3 is
assumed to be a pulse input in the range of 0 to +Vcc / 2. Diodes D1 and D2 are
used to protect pin 2 of the LM555 timer. D1 turns on when the trigger input
exceeds +Vcc + Vd (the forward diode voltage) and D2 turns on when the trigger
input goes below -Vd. These two diodes guarantee that the trigger input is
bounded between -Vd to +Vcc + Vd protecting this input pin. Resistors R1, R2
and the capacitor C2 form a highpass filter used to take the derivative of the input
V3. The trigger input which has the steady input of +Vcc / 2 uses the edges of V3
to trigger a single pulse output from the LM555 timer. Figure 7 shows the trigger
input and the V3 supply. Note how the input network has taken the derivative of
V3. The trigger input (Pin 2) is nothing more the derivative of V3 superimposed
on a +Vcc /2 offset due to the steady value of the trigger input of +Vcc / 2.
Figure 6: The LM555 timer in a monostable configuration.
+Vcc
Pin 2 Trig
+Vcc / 2
V3
0 Time
Figure 7: The trigger input to the monostable oscillator circuit given in Figure 6.
9- 8
A negative going edge on the trigger input starts a trigger event that generates a
single pulse. At this point in time, the voltage on the capacitor C is 0 volts. The
trigger event on the trigger input sets the RS-FF to a set condition (C2 = 0 , and
C1 = 1 from Figure 2) and starts capacitor C charging through Ra. As the trigger
input returns to its steady state value of +Vcc / 2, V+ < V- of C1 and V+ < V- of
C2 (see Figure 2) yielding the output C1 = 0 and the output of C2 = 0. This sets
the RS-FF to a hold condition leaving RS-FF output Q = 1 (see Figure 2). With Q
= 1, Qnot = 0 and the transistor Q1 is still off and the capacitor continues to
charge through Ra toward +Vcc. This capacitor continues to charge until it
reaches a voltage of 2/3 +Vcc. At this point, V+ > V- of C1 and V+ < V- of C2
yielding the output C1 = 1 and the output of C2 = 0, setting the RS-FF to a reset
condition. This turns on Q1 discharging the capacitor C to 0. Starting with
Equation (1) with Vf = +Vcc and the initial voltage across the capacitor C, Vi = 0
gives
Vpin_2(t) = +Vcc (1 -e-t/RaC) . (14)
The capacitor C charges towards +Vcc until it reaches the value 2/3 +Vcc. At this
point, V+ < V- of C1 and V+ > V- of C2 yielding the output C1 = 0 and the
output of C2 = 1. This sets the RS-FF to a reset condition leaving Q = 0. With Q
= 0, Qnot = 1, transistor Q1 turns on and the capacitor discharges to zero where
the capacitor voltage stays at this value until another negative-going trigger pulse
occurs on the trigger input.
The total time Tp it takes the capacitor to reach 2/3 +Vcc is found by substituting
this value into Equation (14) and solving for t
Tp = ln(3) . Ra . C (15)
Figure 8 shows Vout, the voltage across the capacitor C, Vcapacitor, and the
trigger input as a function of time.
Since the pulse width of the monostable oscillator circuit depends on the charging
to the voltage of 2/3 +Vcc, changing this voltage value changes the time it takes
for condition of V+ > V- of C2 and V+ < V- of C1. At this point, the outputs C1
= 0 and C2 = 1 setting the RS-FF to reset state on the transistor Q1 and
discharging the capacitor C to zero. Removing the 0.01 µf capacitor applied to
the CV input and applying a varying voltage as shown in Figure 9 will vary the
pulse width of the pulse output. The op-amp circuit is nothing more than a unity
gain buffer isolating the voltage source Vg from reference voltage CV input of the
LM555 timer. Letting Vg be the voltage on the CV input, the total time Tp to
reach this voltage on the capacitor is
 Vg 
Tp = - Ra . C . ln1 - +Vcc (16)
 
9- 9
Figure 9 is nothing more than a pulse width modulator (PWM) with the pulse
width proportional to the input voltage Vg. Figure 10 gives an example of Vout
as a function Vg. For this example, +Vcc = 10 volts and Vg is a sine wave with a
peak value of 3 volts and an offset of 4 volts so that Vg varies in a sinusoidal
manner from 1 volt to 7 volts. Figure 10 shows how the pulse width increases as
the value of Vg increases.
+Vcc
Vout
Trigger - Pin 2
2/3 +Vcc Trigger - Pin 2
1/2 +Vcc
Vcapacitor
Vout
Tp
0
0 Time
Figure 8: Vout, the voltage across the capacitor C Vcapacitor, and

the trigger input Pin 2 as a function of time for monostable
oscillator circuit given in Figure 6.
Figure 9: A LM555 timer configured as a pulse width modulator.
9-10
Vout
+Vcc
Vg
0 Time
Figure 10: An example of using the LM555 timer as a pulse width modulator.
Procedure:
General Setup:
correct.
current.
the data overlaps.
The LM555 Universal Timer Circuits

1. Using an LM555 timer with +Vcc set to +10 volts, design and build the astable
oscillator of Figure 3(a) with fo = 1000 Hz and with a duty cycle of 33% (as
defined in Equation (8)).
2. Measure and record with an oscilloscope Vout, and the threshold input (pin 6).
Compare these two waveforms to the waveforms given in Figure 4. How are
they same and how are they different?
3. What is the measured frequency and duty cycle for this circuit.
4. Compute the percentage difference between the measured and original design
9-11
requirements for the frequency and the duty cycle. Discuss the differences in
the laboratory report.
5. What is the value on the threshold input (pin 6) when Vout changes states?
6. Setting the oscilloscope to AC coupling, and increasing the vertical sensitivity
of the oscilloscope measure and record the voltage at +Vcc Pin 8. Discuss
what you observe in the laboratory report.
7. Now connect at least a 10µf capacitor between +Vcc Pin 8 and ground and
repeat Step 6. Discuss what you observe in the laboratory report. Leave this
capacitor connected between +Vcc and ground for the rest of the laboratory
experiment.
8. Add a 1N4148 diode across Rb as shown in Figure 5.
9. Measure and record with an oscilloscope Vout, and the threshold input (pin 6).
10. What is the measured frequency and duty cycle for this circuit.
11. How did adding the diode change the frequency and duty cycle? How does the
measured frequency compare to the values calculated from Equations (12) and
(13)?
12. Using an LM555 timer with +Vcc set to +10 volts design and build the
monostable oscillator of Figure 6 with fo = 1000 Hz and with a pulse width of
0.5 millisecond. For V3, use a square wave with a 50% duty cycle that goes
from 0 to +Vcc / 2 with a frequency of 200 Hz.
13. Measure and record with an oscilloscope Vout, V3 and the trigger input (pin
2).
14. How does Vout and the trigger input of Step 14 compare to the plot given in
Figure 8?
15. Measure the actual pulse width of Vout and compare this result to Equation
(15).
16. Using an LM555 timer with +Vcc set to +10 volts and -Vcc set to -10 volts
design and build the pulse width modulator of Figure 9 with a pulse width of
0.2 milliseconds. This is the same circuit as the monostable circuit but with the
addition of a 2X non-inverting amplifier and an additional signal source Vg.
17. Set V3 to 0 to +Vcc / 2, square wave with a 50% duty cycle and a frequency of
2000 Hz.
18. Set Vg = 6.67 volts DC and measure Tp. Compare this result to what is
expected from Equation (16).
19. Varying Vg from 0.5 to 4 volts (0.5, 1.5, 3.5 and 4), measure Tp and compare
these values to the results expected from Equation (16).
20. Set Vg to a sine wave with a peak value of 1.5 volts and an offset of 2 volts so
that Vg varies in a sinusoidal manner from 0.5 volt to 3.5 volts (Note: On the
AFG3022 Function Generator, make sure that the Frequency CH1= CH2 is
“Off”).
21. Measure and record with an oscilloscope Vout and Vg. Compare these results
to that given in Figure 9.
9-12
5. The procedures.
8. All plots (oscilloscope waveforms) generated for each step.
9-13
APPENDICES
A-1
Appendix A
Available Resistors and Capacitors
A-2
Appendix A
A-3
Appendix A
A-4

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LABORATORY MANUAL

UNIVERSITY OF CENTRAL FLORIDA

Safety: Safety Rules and Operating Procedures

Introduction: When in Doubt, Read This

Experiment #1: Linear Operational Amplifier Applications - 2.5 Wks

Experiment #2: More Linear Operational Amplifier Applications - 2.5Wks

Experiment #3: Linear Voltage Regulators - 1 Wk

Experiment #4: Switching Voltage Regulators - 1 Wk

Experiment #5: Precision Diodes and Applications - 1 Wk

Experiment #6: Active Filters - 2 Wks

Experiment #7: Voltage Comparators and Schmitt Triggers - 1 Wk

Experiment #8: Oscillators and Waveform Generators – 1 -Wk

Experiment #9: The 555 Timer 1 - Wk

Appendix A: Available Resistors and Capacitors

6. University property must not be taken from the laboratory.

10. ANYONE VIOLATING ANY RULES OR REGULATIONS MAY BE DENIED

Each student will be assigned to a team and is expected to be a contributing member of

Pre-Laboratory Grade (20 points):

Laboratory Performance (30 points):

Laboratory Report Grade (50 points):

Guidelines for Laboratory Reports:

Organization in your report is important. It should be presented in chronological order

Arbitrary Function Generator:

a. Design a gain Av of 3 non-inverting amplifier using a minimum of 1k-ohm

Vout = -3V1 - 2V2 ,

Vout = Aod(V+ - V-) (1)

Figure 1: A Schematic diagram of a typical op-amp.

-Vcc ≤ Vout ≤ + Vcc (2)

Figure 2: The schematic for an inverting amplifier.

The voltage gain for an inverting amplifier is given as:

Vin - 0v Vin 0v - Vout -Vout

is nothing more than the peak output voltage.

Figure 5: The schematic for a non-inverting amplifier.

The gain Av for a non-inverting amplifier is given by:

Vin - 0v Vin Vout - Vin

The bandwidth of a non-inverting amplifier depends on the size of the signal on

Consider the non-inverting amplifier of Figure 5. According to Equation (9), when

Unity Gain Buffer or Voltage Follower

Figure 9: The schematic for a unity gain buffer amplifier.

An application of the inverting amplifier is that of the summing amplifier shown in

Figure 12: A schematic for a summing amplifier.

IRF =IR1 + IR2 + IR3 + IR4 (12)

0 - Vout V1-0 V2-0 V3-0 V4-0

and finally solving for Vout gives:

-RF -RF -RF -RF

Op-amps driving capacitive loads

Unity Gain buffer.

1. The equipment used model and serial number.

a. Design a gain Ad = 2 difference amplifier using a minimum of 1k-ohm resistors

The output voltage is then given by

Figure 2: An example of a differential amplifier with input noise.

The amplifier used in Figure 2 is a difference amplifier with Vout defined as

Vout = Ad . (V1 - V2) . (2)

But V1 and V2 can be written in terms of the differential voltage sources as

Substituting V1 and V2 into Equation 2 gives

Vout = Ad . [ (V + N ) - (-V + N) ] . (5)

Figure 3 gives the schematic of using a single op-amp to implement a difference

If the sum R1 + R2 is set equal to R3 + R4, then Equation (7) reduces to