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AMBA

The document describes an APB protocol state diagram and Verilog code for an APB slave module. The state diagram shows the IDLE, SETUP, and ENABLE states of the peripheral bus and how it transitions between states for read and write transfers. The Verilog code implements an APB slave module with a state machine that transitions between SETUP, write ENABLE, and read ENABLE states to perform read and write operations to memory based on the peripheral bus control signals.

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viswanath Somanchi
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171 views3 pages

AMBA

The document describes an APB protocol state diagram and Verilog code for an APB slave module. The state diagram shows the IDLE, SETUP, and ENABLE states of the peripheral bus and how it transitions between states for read and write transfers. The Verilog code implements an APB slave module with a state machine that transitions between SETUP, write ENABLE, and read ENABLE states to perform read and write operations to memory based on the peripheral bus control signals.

Uploaded by

viswanath Somanchi
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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APB protocol on EMACS

Tuesday, July 30, 2019 5:30 PM

APB:

State diagram:

The state diagram, shown can be used to represent the activity of the
peripheral bus.
Operation of the state machine is through the three states described
below:
IDLE The default state for the peripheral bus.

SETUP When a transfer is required the bus moves into the SETUP
where the appropriate select signal, PSELx, is asserted. The
only remains in the SETUP state for one clock cycle and will
always move to the ENABLE state on the next rising edge of
ENABL In the ENABLE state the enable signal, PENABLE is
E The address, write and select signals all remain stable during
transition from the SETUP to ENABLE state.
The ENABLE state also only lasts for a single clock cycle and
after this state the bus will return to the IDLE state if no
transfers are required. Alternatively, if another transfer is to
follow then the bus will move directly to the SETUP state.
It is acceptable for the address, write and select signals to
during a transition from the ENABLE to SETUP states.

Verilog code :
Verilog code :
module apb_slave
#(
addrWidth = 8,
dataWidth = 32
)
(
input clk,
input rst_n,
input [addrWidth-1:0] paddr,
input pwrite,
input psel,
input penable,
input [dataWidth-1:0] pwdata,
output logic [dataWidth-1:0] prdata
);

logic [dataWidth-1:0] mem [256];

logic [1:0] apb_st;


const logic [1:0] SETUP = 0;
const logic [1:0] W_ENABLE = 1;
const logic [1:0] R_ENABLE = 2;

// SETUP -> ENABLE


always @(negedge rst_n or posedge clk) begin
if (rst_n == 0) begin
apb_st <= 0;
prdata <= 0;
end
else begin
case (apb_st)
SETUP : begin
// clear the prdata
prdata <= 0;

// Move to ENABLE when the psel is asserted


if (psel && !penable) begin
if (pwrite) begin
apb_st <= W_ENABLE;
end

else begin
apb_st <= R_ENABLE;
end
end
end

W_ENABLE : begin
// write pwdata to memory
if (psel && penable && pwrite) begin
mem[paddr] <= pwdata;
end

// return to SETUP
apb_st <= SETUP;
end

R_ENABLE : begin
// read prdata from memory
if (psel && penable && !pwrite) begin
prdata <= mem[paddr];
end

// return to SETUP
apb_st <= SETUP;
end
endcase
end
end
Endmodule

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