P.USHA, CH.KARUNA et al.

ISSN: 2348-4098
DATE OF PUBLICATION: NOV 05, 2014 VOLUME 2 ISSUE 7 SEP-OCT 2014

AN EFFICIENT IMPLEMENTATION OF AUTOMATIC WASHING MACHINE CONTROL

SYSTEM USING VERILOG
P.USHA [1], CH.KARUNA [2]

1. Assistant Professor, ECE Department, KG Reddy College of Engineering and Technology

2. Assistant Professor, ECE Department, KG Reddy College of Engineering and Technology

ABSTRACT

As described by digital system the language Verilog HDL is widely used in the circuit design, has its own advantages to be able
to used as software language which describes hardware features that makes it efficient and has good readability, portability,
etc. Its advantages not only reduce the hardware development cycle but also greatly reduce development costs. This article
describes the characteristics and application of Verilog HDL and takes the automatic washing machine control system as
examples to illustrate the practicality of HDL. The result of simulation shows this method is feasible and effective.

KEYWORDS: Verilog‐ Hardware description languages, Automatic washing machine control system.

1. INTRODUCTION OF VERILOG HDL (2) wash, (3) pump out, and (4) extraction (spin).The
important parts of the washing machine; this will also
With rapid development of science and technology, the help us understand the working of the washing machine.
design of electronic systems also produce a revolutionary
change, a new class of development tools related to a) Water inlet control valve: When you load the clothes in
electronic systems are spreading quickly. Hardware washing machine, this valve gets opened automatically
Description language (HDL) is a method to description of and it closes automatically depending on the total
digital circuit. HDL describes a certain function of digital quantity of the water required.
circuit usually has one or more files composition. With
the rapid development of electronic system design b) Water pump: The water pump circulates water
automation (EDA) and large scale programmable of logic through the washing machine. It works in two directions,
device, HDL has hierarchical description and simulation re‐circulating the water during wash cycle and draining
of any electronic components characteristics, so that the the water during the spin cycle.
circuit designers and developers could describe the
feature of the circuit freely. c) Tub: There are two types of tubs in the washing
machine: inner and outer. The clothes are loaded in the
Verilog language is a kind of abstract level of hardware inner tub, where the clothes are washed, rinsed and
description language. This language supports the early dried. The inner tub has small holes for draining the
abstract design concept, and could realize the later water. The external tub covers the inner tub and supports
abstract design. It includes the hierarchical structure, it during various cycles of clothes washing.
which allows designers to describe the complexity of the
control. d) Agitator or rotating disc: The agitator is located inside
the tub of the washing machine. It performs the cleaning
Verilog HDL is a language which is not only easy to use operation of the clothes. During the wash cycle the
but also has strong function, especially the Verilog HDL agitator rotates continuously and produces strong
industrial standardization, conforms to the trend of rotating currents within the water due to which the
microelectronics technology development. Verilog HDL is clothes also rotate inside the tub.
used in digital design modeling from the switch level to
abstract algorithm design level. These constructions can e) Motor of the washing machine: The motor is coupled to
not only be used to design pattern on hardware inter the agitator and produces it rotator motion.
current behavior, but also on hardware design of
f) Timer: The timer helps setting the wash time for the
scheduling pattern.
clothes manually.
2. THE DESIGN OF AUTOMATIC WASHING g) Drain pipe: The drain pipe enables removing the dirty
MACHINE water from the washing that has been used for the
washing purpose.
Because the Verilog HDL has the advantage of powerful
language structure and concise code for complex control 2.2. Washing Machine Controller specifications
logic. So, this dissertation is based on Verilog HDL to
design the control system of the washing machine. The washing machine controller has the following
functionalities:
2.1. The principle of automatic washing machine
1. The wash machine has the following consecutive
All automatic washers, regardless of type, model, or states: idle, fill, wash, drain, fill, rinse, drain, spin.
make, have only four basic functions of operation: (1) fill,

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P.USHA, CH.KARUNA et al. ISSN: 2348-4098
DATE OF PUBLICATION: NOV 05, 2014 VOLUME 2 ISSUE 7 SEP-OCT 2014

2. There is one control line to the washer water being used in the system. This, however, is beyond the
feed. Choice of hot or cold water wash is done manually scope of this dissertation.
by the user for simplicity.
3. There are two drum rotation speeds: low speed
for wash cycle and high speed for the spin cycle. Speed
control is accomplished through an electrically controlled
mechanism.
4. During the wash cycle, the drum direction of
rotation is controlled through the agitator mechanism.
Figure1is the Icon for the washing machine controller
indicating main input and output lines

Figure 3: The main components of the washing machine
control system.
Figure1: Different States of washing machine

The below figure shows the block diagram of the
automatic wash machine controller, in which the user Table1: Alphabetical listing of input and output signals
selects the start button, the remaining process is for the FSM. All signals are active high.
continued on the time allocated to each state of the
machine i.e. wash, fill, drain etc. D IN Machine door (lid) is open

Start IN Start wash machine

Td IN Drain time required to empty the

machine tub

Tf IN Fill time required to fill the machine tub

Tr IN Rinse time

Ts IN Spin time

Tw IN Wash time
A OUT Activate the agitator mechanism
Figure 2: block diagram of washing machine
M OUT Enable motor
3. WASH MACHINE CONTROLLER DETAIL
P OUT Activate the pump mechanism to drain
Figure2 shows the main components of the washing the water
machine controller. The controller is composed of two
blocks: a finite ‐ sate machine (FSM) block and a timer R OUT Timer reset
block. The FSM block receives some signals from the user,
S OUT Activate motor speed control
from the timer, and from other hardware parts such as
mechanism
the door sensor. FSM block output control the timer block
and other hardware components of the washing machine. W OUT Activate water source solenoid
Table1 identifies the FSM input and output signals and

their functionality. The timer block generates the correct
time periods required for each cycle after it has been 4. PIT FALLS OF ASYNCHRONOUS SIGNALS
reset. The timer block is composed of an up‐counter and
combinational logic to give the correct time signals once The FSM resets the counter each time it starts a new
certain count values have been achieved. Of course the phase (e.g. wash, drain, etc.) in response to the timer
timer values will be determined by the clock frequency outputs. However, for the combination of a Mealy

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P.USHA, CH.KARUNA et al. ISSN: 2348-4098
DATE OF PUBLICATION: NOV 05, 2014 VOLUME 2 ISSUE 7 SEP-OCT 2014

machine and an asynchronous counter reset creates 6. PROJECT REQUIREMENTS

problems. When input signal is set it immediately resets
the timer before the Mealy machine had a chance to In this project we are required to design, model, and
change states. The end result is that the Mealy FSM will be simulate a washing machine controller.
stuck in its present state.This is best illustrated with the  Use a two or a three‐process FSM Verilog coding style for
detailed timing diagram in Figure3. The present state (PS) the FSM block.
of the washer is filling where the drum is being filled with  Verilog code for the timer design.
water until the timer asserts the signal Tf. When this  Write a test bench to verify the operation of the timer.
condition happens, the FSM must do two actions:  Synthesize the controller on FPGA and study the
performance parameters (delay, FPGA resources, power
1. Move to the next state Wash
consumption, and equivalent gate count).
2. Rest the timer
7. PROGRAM
3. Wash clothes until the wash time period Tw is asserted.
module washmachine (rst, clk, start, w, s, a, m, d);
We see from the figure that when the reset signal R is
asserted, the timer immediately zeros its count and all its initial a=0;
output signals are zeroed. This includes the signal Tf. Now
initial m=0;
we have a problem: The present state of the wash
machine is in the fill cycle Fill and the signal Tf is zero. initial s=0;
Hence the next state switches back to Fill. The machine
will remain stuck in this state and over flow the drum initial d=0;
with water. The main problem is that signals like Tf were
allowed to change values more than once within the same always@ (posedge clk, posedge rst)
clock period. This is unacceptable especially for a Mealy
FSM. The correct sequence should have been: begin

Fill → Wash if (rst)

But now our sequence will be begin

Fill → Fill state<= _initial;

And the machine will never get past the fill phase. end

One obvious solution to this problem is to use else

synchronous reset for the counter. Another solution is to
add an extra state after each operation phase of the begin
washer so that checking the time signal and resetting the
counter are accomplished in two deferent states. case (state)

5. DESIGN FLOW _initial:

Fill:
To design the washing machine the following are
required to be done. Wash:
1. Design the Mealy state diagram for the washing Drain:
machine whose specifications are listed in Section2.2.
2. List the states of your state transition diagram Fill:
3. Design the timer but having the timing specifications.
4. In new washing machines the door is locked as long as Rinse:
the machine is in operation. Draw the Mealy state
diagram that satisfies this requirement. Drain:

Dry:

Default:

endcase

end

endmodule

Figure 4: Working of Washing Machine

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P.USHA, CH.KARUNA et al. ISSN: 2348-4098
DATE OF PUBLICATION: NOV 05, 2014 VOLUME 2 ISSUE 7 SEP-OCT 2014

7.1 Simulation of the Automatic Washing Machine enter water state. As long as you no longer press start
button, washing machine will automatically execute the
When reset signal comes, all of the signals are set to process according to the predetermined process. The
zeros; then if you put on start button the machine will simulation results are as shown in figure 4.

Figure 4.Simulation of Automatic Washing machine controller

8. CONCLUSION [4] WangJiGang, GuGuoChang. Structures and patterns in

communication system software application research
In this paper we use Verilog HDL language to design (J].journal of computer application pract, (I I): 43‐45.
automatic washing machine control system. We use this
powerful language structure and concise code to describe [5] YangJimin YangJiBing, digital system design and
the complex control logic. Through comprehend the VerilogHDL [M].beijing: electronic industry press, 2003,
corresponding hardware circuit and tools of Verilog HDL 23(11):43‐45.
language to generate more than traditional logical design
method which can adapt to the social development needs. [6] YuanJunQuan, SunMinQi, CaoRui. VerilogHDL digital
We use hardware description language form digital system design and its application [M].concrete: Xian
system design which is not only flexible and convenient University of electronic science and technology press,
but also reduce the cost of development and the 2002.
development cycle. This design method plays an
increasingly important role in the future digital system
design.

REFERENCES
[1]. Wangguan etc. Verilog HDL and digital circuit design
[M].beijing mechanical industry press, 2005.9

[2] XiaYu wen. Verilog digital system design guide
[M].beijing: aerospace university press, 2003. 2‐10
[3] Thomas & Moorby, the Hardware Verilog
DescriptionLanguage [M]. Beijing tsinghua university
press, 2001. 23‐36.

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