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Experiment No-:7 Aim-: Tools and Version Used-: Theory

The document describes an experiment to implement a D flip-flop using VHDL. It provides background on how D flip-flops differ from D latches in their clocking behavior. A circuit diagram and state table are shown. VHDL code is then provided and simulated to realize the D flip-flop design using Xilinx software. The result and discussion confirm that the D flip-flop was successfully implemented through VHDL code and simulation.

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Sheetal Dagar
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29 views3 pages

Experiment No-:7 Aim-: Tools and Version Used-: Theory

The document describes an experiment to implement a D flip-flop using VHDL. It provides background on how D flip-flops differ from D latches in their clocking behavior. A circuit diagram and state table are shown. VHDL code is then provided and simulated to realize the D flip-flop design using Xilinx software. The result and discussion confirm that the D flip-flop was successfully implemented through VHDL code and simulation.

Uploaded by

Sheetal Dagar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment no-:7

Aim-:To implement the D flip-flop using VHDL


Tools and version used-:Xilinx ISE Design suite 14.7
Theory-:
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
The circuit diagram of D flip-flop is shown in the following figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip-flop is
similar to D Latch. But, this flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.

The following table shows the state table of D flip-flop.

D Q(t+1)

0 0

0 1

Therefore, D flip-flop always Hold the information, which is available on data input, D of
earlier positive transition of clock signal. From the above state table, we can directly write
the next state equation as

Q(t+1)=D
Next state of D flip-flop is always equal to data input, D for every positive transition of the
clock signal. Hence, D flip-flops can be used in registers, shift registers and some of the
counters.
VHDL Program-:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity q is

Port ( q : out STD_LOGIC;

notq : out STD_LOGIC;

d:in STD_LOGIC

clk : in STD_LOGIC);

end q;

architecture Behavioral of q is

begin

process(clk)

if(clk=1)

q<=d;

notq<=notd;

end if;

end process;

end Behavioral;

Simulation-:
Result-:We had realised D flip-flop using Xilinx Software.

Discussion on Result-:VHDL code written and simulated, syntax, truth table, logic block,
RTL Schematic and waveform analysis are performed.

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