8/12/2019 VLSI Basics: VLSI design flow

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22 March 2015

VLSI design flow

VLSI Design Flow

VLSI design Flow

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of steps, and
eventually produces a packaged chip. A typical design cycle may be represented by the flow chart
shown in Figure. Our emphasis is on the physical design step of the VLSI design cycle. However, to
gain a global perspective, we briefly outline all the steps of the VLSI design cycle.
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1.System Specification:
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The first step of any design process is to lay down the specifications of the system.
System specification is a high level representation of the system. The factors to be Select Language
considered in this process include: performance, functionality, and physical dimensions Powered by Translate
(size of the die (chip)). The fabrication technology and design techniques are also
considered. Popular Posts
The specification of a system is a compromise between market requirements, technology
and economical viability. The end results are specifications for the size, speed, power, VLSI design flow
and functionality of the VLSI system. VLSI Design Flow
VLSI design Flow The
VLSI design cycle
2. Architectural Design: starts with a formal
specification of a VLSI chip, follows
a series of steps...
The basic architecture of the system is designed in this step. This includes, such
Floorplanning
decisions as RISC (Reduced Instruction Set Computer) versus CISC (Complex
What is
Instruction Set Computer), number of ALUs, Floating Point units, number and structure Floorplanning???? A
of pipelines, and size of caches among others. floorplanning is the
process of placing
The outcome of architectural design is a Micro-Architectural Specification (MAS). While blocks/macros in the chip/core
MAS is a textual (English like) description, architects can accurately predict the area, thereby determining th...

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performance, power and die size of the design based on such a description.
Electromigration & IR
drop
3. Behavioral or Functional Design: What is
Electromigration???
Electromigration is
the gradual displacement of metal
In this step, main functional units of the system are identified. This also identifies the
atoms in a semiconductor. It occurs
interconnect requirements between the units. The area, power, and other parameters of when the current d...
each unit are estimated.
The behavioral aspects of the system are considered without implementation specific Power Planning
What is Power
information. For example, it may specify that a multiplication is required, but exactly in Planning????
which mode such multiplication may be executed is not specified. We may use a variety Power planning is a
of multiplication hardware depending on the speed and word size requirements. The key step which typically is
done with floorplanning in which
idea is to specify behavior, in terms of input, output and timing of each unit, without
power grid network is ...
specifying its internal structure.
The outcome of functional design is usually a timing diagram or other relationships Blockages and Halo
between units. This information leads to improvement of the overall design process and Blockages Blockages are specified
locations where placing cells are
reduction of the complexity of subsequent phases. Functional or behavioral design prevented or blocked. These act as
provides quick emulation of the system and allows fast debugging of the full system. guidelines for placing standard c...
Behavioral design is largely a manual step with little or no automation help available.
4. Logic Design: Topics

Arrival time
In this step the control flow, word widths, register allocation, arithmetic operations, and
Backend
logic operations of the design that represent the functional design are derived and
Basic Terminology
tested.
Blockages
This description is called Register Transfer Level (RTL) description. RTL is expressed in
Buffer and Gate Relocation
a Hardware Description Language (HDL), such as VHDL or Verilog. This description can
be used in simulation and verification. This description consists of Boolean expressions Buffer and Gate Sizing
and timing information. The Boolean expressions are minimized to achieve the smallest Clock Tree Optimization
logic design which conforms to the functional design. This logic design of the system is Clock Tree Synthesis
simulated and tested to verify its correctness. In some special cases, logic design can be congestion
automated using high level synthesis tools. These tools produce a RTL description from congestion driven placement
a behavioral description of the design. CTS goals
Delay
5. Circuit Design: Delay Insertion
Design Flow
The purpose of circuit design is to develop a circuit representation based on the logic Detailed placement
design. The Boolean expressions are converted into a circuit representation by taking Dummy Load Insertion
into consideration the speed and power requirements of the original design. Circuit Effects of CTS
Simulation is used to verify the correctness and timing of each component. Electromigration
The circuit design is usually expressed in a detailed circuit diagram. This diagram shows Floorplanning
the circuit elements (cells, macros, gates, transistors) and interconnection between these gate array placement
elements. This representation is also called a netlist. Tools used to manually enter such Global Placement
description are called schematic capture tools. In many cases, a netlist can be created Halo
automatically from logic (RTL) description by using logic synthesis tools.
Hold time
In-placement optimization
6. Physical Design: IR Drop
In this step the circuit representation (or netlist) is converted into a geometric Jitter
representation. As stated earlier, this geometric representation of a circuit is called a Legalization
layout. Layout is created by converting each logic component (cells, macros, gates, Level Adjustment
transistors) into a geometric representation (specific shapes in multiple layers), which macro block placement
perform the intended logic function of the corresponding component. Connections mixed size placement
between different components are also expressed as geometric patterns typically lines in
OCV
multiple layers.
Physical Design
The exact details of the layout also depend on design rules, which are guidelines based
Placement
on the limitations of the fabrication process and the electrical properties of the
Post placement optimization
fabrication materials. Physical design is a very complex process and therefore it is
Powerplanning
usually broken down into various sub-steps. Various verification and validation checks
Pre-placement optimization
are performed on the layout during physical design.
Reconfiguration
In many cases, physical design can be completely or partially automated and layout can
be generated directly from netlist by Layout Synthesis tools. Layout synthesis tools, Recovery time
while fast, do have an area and performance penalty, which limit their use to some Removal time
designs. Manual layout, while slow and manually intensive, does have better area and Required time
performance as compared to synthesized layout. However this advantage may dissipate Routing
as larger and larger designs may undermine human capability to comprehend and Setup & Hold
obtain globally optimized solutions. Setup time
Skew

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7. Fabrication: Slack
After layout and verification, the design is ready for fabrication. Since layout data is standard cell placement
typically sent to fabrication on a tape, the event of release of data is called Tape Out. VLSI Design Flow
Layout data is converted (or fractured) into photo-lithographic masks, one for each
layer. Masks identify spaces on the wafer, where certain materials need to be deposited, Blog Archive
diffused or even removed. Silicon crystals are grown and sliced to produce wafers.
Extremely small dimensions of VLSI devices require that the wafers be polished to near ► 2018 (1)
►

perfection. The fabrication process consists of several steps involving deposition, and ► 2017 (1)
►
diffusion of various materials on the wafer. During each step one mask is used. Several ▼ 2015 (17)
▼
dozen masks may be used to complete the fabrication process. ► April (4)
►
A large wafer is 20 cm (8 inch) in diameter and can be used to produce hundreds of
▼ March (13)
▼
chips, depending of the size of the chip. Before the chip is mass produced, a prototype is
Placement of different design
made and tested. Industry is rapidly moving towards a 30 cm (12 inch) wafer allowing styles & Optimizatio...
even more chips per wafer leading to lower cost per chip.
Placement
Blockages and Halo
8. Packaging, Testing and Debugging:
Electromigration & IR drop
Finally, the wafer is fabricated and diced into individual chips in a fabrication facility.
Power Planning
Each chip is then packaged and tested to ensure that it meets all the design
specifications and that it functions properly. Chips used in Printed Circuit Boards (PCBs) Floorplanning
are packaged in Dual In-line Package (DIP), Pin Grid Array (PGA), Ball Grid Array Physical design setup
(BGA), and Quad Flat Package (QFP). Chips used in Multi-Chip Modules (MCM) are not Overview of Physical Design
packaged, since MCMs use bare or naked chips. Flow
VLSI design flow
Posted by Jimmy at 2:00 am Basic Terminology 3
Labels: Design Flow, VLSI Design Flow Basic Terminology 2
Setup & Hold Slack Check

15 comments: Basic Terminology

Semicon Technologies 26 April 2016 at 15:40

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Unknown 5 August 2017 at 21:26

Very well explained.... Thanks
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Nandha kumar 17 August 2017 at 22:05

Contributors
nice information...:)
Jimmy
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Tarang

tarun kumar kundrapu 21 August 2017 at 00:29

koushik-thx-Bro
Reply

Yogananda KH 12 November 2017 at 17:09

Very cleared explanation.
Reply

Unknown 26 June 2018 at 22:26

Vivid explanation.. indeed
Reply

sumedhait 20 August 2018 at 16:57

This is probably the best and most concise step by step explanation of VLSI designing. Thank you.
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Reply

rohith m 6 September 2018 at 08:59

Total concept is FASAAAKKKKKK
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Unknown 12 December 2018 at 15:40

thanks a lot sir/mam
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gundla narendar 19 January 2019 at 20:38

Nice information
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Unknown 1 April 2019 at 14:00

Thanks
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