EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS

(Credit - 4)

Unit Three: 8085 Instructions and

Timing Diagram

School of Electronics Engineering

Kalinga Institute of Industrial Technology
Deemed to be University
 Instruction Size

1 Instruction

The 8085 microprocessor instruction set has 74 operation codes that result in 246 instruc-
tions. An instruction is a binary pattern designed inside a microprocessor to perform a
specific function.
Each instruction has two parts: first is the task to be performed, called the operation
code (opcode), and the second is the data to be operated on, called the operand.

The 8085 instructions can be classified based on three criteria:

1. Instruction size

2. Function

3. Addressing modes

2 Instruction Size

Instruction size refers to the number of bytes an instruction requires for its complete op-
eration. Based on instruction size, 8085 instruction set can be classified into the following
three groups:

• 1-byte instructions: An 1-byte instruction includes the opcode and the operand in
the same byte. For example– MOV C,A; ADD B. [Opcode and only registers]

• 2-byte instructions: In a 2-byte instruction, the first byte specifies the opera-
tion code and the second byte specifies the operand. For example– MVI A,32H;
ADI 54H. [Opcode and 8-bit data]

• 3-byte instructions: In a 3-byte instruction, the first specifies the opcode and the
following two bytes specify the operands. For example– LXI H,F150H; LDA 8000H.
[Opcode and 16-bit data]

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 Function

3 Function

The 8085 instruction set can be classified into the following five functional categories:

• Data Transfer: This group of instruction copies data from source location to desti-
nation location. The various types of data transfer that takes place are:
a) between registers – MOV D,B,
b) between memory location and register – LDA F200H,
c) specific data byte to a register or a memory location – MVI C,43H, and
d) between and I/O device and accumulator – IN 85H.

• Arithmetic: These instructions perform arithmetic operations such as:

a) addition – ADD B,
b) subtraction – SUB C,
c) increment – INR M, and
d) decrement – DCX H.

• Logical: These instructions perform various logical operations with the contents of
the accumulator such as:
a) AND, OR, XOR – ANA B, ORA M, XRI 43H,
b) Rotate – RLC, RAR,
c) Compare – CMP B, and
d) Complement – CMA.

• Branching: This group of instructions alters the sequence of program execution

either conditionally or unconditionally. Conditions here signify the state of flags.
JNZ F170H, CALL F070H.

• Machine Control: These instructions control machine functions such as stop, interrupt,
or do nothing. HLT, NOP

Note: In arithmetic and logical operations, one of the operands is always the accumulator.
The other operand can be a register, an 8-bit data, or a memory location. The increment
and decrement operations are a little bit different as they can be performed on any one
of the register or in memory location.

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 Addressing Modes

4 Addressing Modes

The various formats of specifying the operands in the instruction are called the Addressing
Modes. The term addressing mode signifies how the data to be operated upon by an
instruction is specified. Based on addressing modes, the 8085 instructions are classified
into the following five groups:

• Register Addressing Mode: In this mode, the data to be operated upon is in a

general purpose register. Eg. MOV A,B, ADD B.

• Direct Addressing Mode: In this mode, the data to be operated upon is given directly
by the address specified in the instruction. Eg. STA F500H, IN 85H.

• Register Indirect Addressing Mode: In this mode, the data to be operated upon is
given indirectly by the contents of a register pair. Eg. MOV M,A, LDAX B.

• Immediate Addressing Mode: In this mode, the data to be operated upon is given
in the instruction immediately. Eg. MVI A,32H, ADI 43H.

• Implicit Addressing Mode: In this mode, the data to be operated upon is already
known and need not be specified explicitly in the instruction. Eg. CMA, RLC.

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 Timing Diagram

5 Timing Diagram

Timing diagram is a graphical representation of various control signals generated during

execution of an instruction. In the timing diagram of an instruction, buses and various
control signals are shown which includes the following:

• Higher-order address bus: A15 −A8 ,

• Multiplexed data and lower-order address bus: AD7 −AD0 ,

• ALE,

• IO/M,

• RD, and WR.

5.1 Machine Cycle

Machine cycle is defined as the time required to complete one operation of accessing
memory, I/O, or acknowledging an external request. Depending on the operation, we
have the following machine cycles:

• Opcode Fetch M/C.

• Memory Read M/C and Memory Write M/C.

• I/O Read M/C and I/O Write M/C.

• Interrupt Acknowledge M/C.

• Halt M/C, Hold M/C and Reset M/C.

• Bus Idle M/C

5.2 T-state

T-state is defined as one subdivision of the operation performed in one clock period. Each
T-state is precisely equal to one clock period.

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 Timing Diagram

5.3 Instruction Cycle

Instruction cycle is defined as the time required to complete the total execution of an
instruction. It consists of the opcode fetch machine cycle and any other machine cycles if
required.

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 Opcode Fetch Machine Cycle

6 Opcode Fetch Machine Cycle

The first operation in any instruction is opcode fetch. The microprocessor needs to get
(fetch) the opcode from the memory; only after that the microprocessor can begin to
execute the instruction. So the first machine cycle of any instruction is Opcode Fetch
Machine Cycle.
The opcode fetch machine cycle is shown below

Opcode Fetch M/C

T1 T2 T3 T4

CLK

A15 –A8 Higher Order Memory Address Unspecified

AD7 –AD0 Lower Order

Opcode
Memory Address

ALE

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1

RD bc

bc

WR

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 Opcode Fetch Machine Cycle

To perform opcode fetch, the microprocessor executes the following steps:

Step 1: T1 — The microprocessor places the 16-bit memory address from the Program
Counter (PC) on the address bus. The ALE signal goes high during T1 to indicate
that the multiplexed bus is now giving address; i.e.,
PCH → A15 − A8 ; PCL → AD7 − AD0 .
Since the opcode is to be fetched from memory IO/M = 0. The microprocessor
identifies that it is an opcode fetch machine cycle with the help of status signals;
S1 = 1, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor can
take (read) the opcode from the memory location whose address was known dur-
ing T1 . After taking the opcode, the microprocessor places it in the Instruction
Register.
Step 3: T4 — The opcode placed in the IR is now decoded and the microprocessor
performs the instructions accordingly.

Note: After the T3 state, the contents of the bus A15 − A8 are unknown, and the data
bus AD7 − AD0 goes into high impedance.
For some instructions, the opcode fetch machine cycle takes more than 4 T-states. In
that case, the remaining T-states (T5 , T6 ) are used for internal microprocessor operations.

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 Memory Read Machine Cycle

7 Memory Read Machine Cycle

After performing the opcode fetch machine cycle, and depending on the instruction de-
coded the microprocessor may need to perform a memory read machine cycle. In this
machine cycle, data is transferred from the memory to the microprocessor.

The memory read machine cycle is shown below

Memory Read M/C

T1 T2 T3

CLK

A15 –A8 Higher Order Memory Address

AD7 –AD0 Lower Order

Data from Memory
Memory Address

ALE

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 0

RD bc bc

WR

9
 Memory Read Machine Cycle

To perform memory read, the microprocessor executes the following steps:

Step 1: T1 — Depending on the instruction, the microprocessor places a 16-bit memory
address from either Program Counter (PC), Stack Pointer (SP), BC Register
pair, DE Register pair, HL Register pair or WZ Temporary register pair on the
address bus. The ALE signal goes high during T1 to indicate that the multiplexed
bus is now giving address; i.e.,

PCH PCL

SPH SPL

B C
A15 − A8 AD7 − AD0
D E

H L

W Z

Since data is to be read from memory IO/M = 0. The microprocessor identifies

that it is a read machine cycle with the help of status signals; S1 = 1, S0 = 0.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor
can take (read) the data from the IO device whose address was known during
T1 . After taking the data, the microprocessor places the data in any one of the
8-bit registers (except IR).

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 Memory Write Machine Cycle

8 Memory Write Machine Cycle

After performing the opcode fetch machine cycle, and depending on the instruction de-
coded the microprocessor may need to perform a memory write machine cycle. In this
machine cycle, data is transferred from the microprocessor to the memory.

The memory write machine cycle is shown below

Memory Write M/C

T1 T2 T3

CLK

A15 –A8 Higher Order Memory Address

AD7 –AD0 Lower Order Data from µP

Memory Address
to Memory

ALE

IO/M, S1 , S0
IO/M = 0, S1 = 0, S0 = 1

RD

WR bc

bc

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 Memory Write Machine Cycle

To perform memory write, the microprocessor executes the following steps:

Step 1: T1 — The microprocessor places a 16-bit memory address from either Stack
Pointer (SP), BC Register pair, DE Register pair, HL Register pair or WZ
Temporary register pair on the address bus. The ALE signal goes high dur-
ing T1 to indicate that the multiplexed bus is now giving address; i.e.,

SPH SPL

B C

D A15 − A8 E AD7 − AD0

H L

W Z

Since data is to be written to memory IO/M = 0. The microprocessor identifies

that it is a write machine cycle with the help of status signals; S1 = 0, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the WR signal goes low. Now the microprocessor can
give (write) the data to the memory location whose address was known during
T1 . So according to the instruction, data from any one of the 8-bit registers
(except W, Z and IR) is written to the memory.

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 IO Read Machine Cycle

9 IO Read Machine Cycle

After performing the opcode fetch machine cycle, and depending on the instruction de-
coded the microprocessor may need to perform an IO read machine cycle. In this machine
cycle, data is transferred from the input device to the microprocessor.

The IO read machine cycle is shown below

IO Read M/C

T1 T2 T3

CLK

A15 –A8 8-bit Port Address

AD7 –AD0 8-bit Data from

Port Address Input Device to Acc.

ALE

IO/M, S1 , S0
IO/M = 1, S1 = 1, S0 = 0

RD bc bc

WR

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 IO Read Machine Cycle

To perform IO read, the microprocessor executes the following steps:

Step 1: T1 — The 8-bit IO port address is available in W register and the same 8-bit IO
port address is also available in the Z register, i.e., in IO read machine cycle, W
and Z will have identical 8-bit address of the input device from which data is to
be read. This port address will be placed on the address bus. The ALE signal
goes high during T1 to indicate that the multiplexed bus is now giving address;
i.e.,
W → A15 − A8 ; Z → AD7 − AD0 .
Since data is to be read from IO device IO/M = 1. The microprocessor identifies
that it is a read machine cycle with the help of status signals; S1 = 1, S0 = 0.
Step 2: T2 , T3 — During T2 and T3 , the RD signal goes low. Now the microprocessor
can take (read) the data from the IO device whose address was known during T1 .
After taking the data, the microprocessor places the data in the accumulator.

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 IO Write Machine Cycle

10 IO Write Machine Cycle

After performing the opcode fetch machine cycle, and depending on the instruction de-
coded the microprocessor may need to perform an IO write machine cycle. In this machine
cycle, data is transferred from the microprocessor to the output device.

The IO write machine cycle is shown below

IO Write M/C

T1 T2 T3

CLK

A15 –A8 8-bit Port Address

AD7 –AD0 8-bit Data from Acc.

Port Address to Output Device

ALE

IO/M, S1 , S0
IO/M = 1, S1 = 0, S0 = 1

RD

WR bc

bc

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 IO Write Machine Cycle

To perform IO write, the microprocessor executes the following steps:

Step 1: T1 — The 8-bit IO port address is available in W register and the same 8-bit IO
port address is also available in the Z register, i.e., in IO write machine cycle, W
and Z will have identical 8-bit address of the output device to which data is to
be written. This port address will be placed on the address bus. The ALE signal
goes high during T1 to indicate that the multiplexed bus is now giving address;
i.e.,
W → A15 − A8 ; Z → AD7 − AD0 .
Since data is to be written to IO device IO/M = 1. The microprocessor identifies
that it is a write machine cycle with the help of status signals; S1 = 0, S0 = 1.
Step 2: T2 , T3 — During T2 and T3 , the WR signal goes low. Now the microprocessor
can give (write) the data to the IO device whose address was known during T1 .
So according to the instruction, data from the accumulator is written to the
output device.

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 Timing Diagram of IN instruction

11 Timing Diagram of IN instruction

The IN instruction timing diagram is shown using the following example.

F000: IN 85H
Assume data DAH is there in the input device.
The memory and I/O representation for this IN instruction is shown below.

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 Timing Diagram of IN instruction

M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : IO Read M/C

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
8-bit address
A15 –A8 F0H Unspecified F0H of input device
85H

Lower Order Opcode Lower Order Data from Memory Lower Order Data from Input Device to Acc.
8-bit address 8-bit address
AD7 –AD0 00H DBH 01H of input device of input device
DAH
85H 85H
Memory Address Memory Address Memory Address
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ALE

Timing Diagram of IN instruction

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0 IO/M = 1, S1 = 1, S0 = 0

RD
bc

bc

bc
bc

bc

bc
WR
 Timing Diagram of OUT instruction

12 Timing Diagram of OUT instruction

The IN instruction timing diagram is shown using the following example.

F000: OUT 80H
Assume data ACH is there in the accumulator.
The memory and I/O representation for this OUT instruction is shown below.

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 Timing Diagram of OUT instruction

M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : IO Write M/C

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
8-bit address
A15 –A8 F0H Unspecified F0H of output device
80H

Lower Order Opcode Lower Order Data from Memory Lower Order Data from Acc. to Output Device
8-bit address 8-bit address
AD7 –AD0 00H D3H 01H of output device of output device
ACH
80H 80H
Memory Address Memory Address Memory Address
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ALE

Timing Diagram of OUT instruction

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0 IO/M = 1, S1 = 0, S0 = 1

RD
bc

bc
bc

bc
WR

bc
bc
 Timing Diagram of LDA instruction

13 Timing Diagram of LDA instruction

The LDA instructino timing diagram is shown using the following example.
F000: LDA F150H
Assume data 56H is there in memory location F150H .
The memory representation for this LDA instruction is shown below.

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 Timing Diagram of LDA instruction

M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : Memory Read M/C M4 : Memory Read M/C

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3

CLK

Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
A15 –A8 F0H Unspecified F0H F0H F1H

Lower Order Opcode Lower Order Data from Memory Lower Order Data from Memory Lower Order Data from Memory
Lower byte Higher byte Data at memory
AD7 –AD0 00H 3AH 01H of the address 02H of the address 50H address F150H
50H F1H 56H
Memory Address Memory Address Memory Address Memory Address
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ALE

Timing Diagram of LDA instruction

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0 IO/M = 0, S1 = 1, S0 = 0 IO/M = 0, S1 = 1, S0 = 0

RD bc bc bc bc

bc bc bc bc

WR
 Timing Diagram of STA instruction

14 Timing Diagram of STA instruction

The STA instructino timing diagram is shown using the following example.
F000: STA F650H
Assume data 78H is there in the accumulator.
The memory representation for this STA instruction is shown below.

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 Timing Diagram of STA instruction

M1 : Opcode Fetch M/C M2 : Memory Read M/C M3 : Memory Read M/C M4 : Memory Write M/C

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3

CLK

Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address Higher Order Memory Address
A15 –A8 F0H Unspecified F0H F0H F6H

Lower Order Opcode Lower Order Data from Memory Lower Order Data from Memory Lower Order Data from µP
Lower byte Higher byte Data in Acc.
AD7 –AD0 00H 32H 01H of the address 02H of the address 50H to memory address F650H
50H F6H 78H
Memory Address Memory Address Memory Address Memory Address to Memory
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ALE

Timing Diagram of STA instruction

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0 IO/M = 0, S1 = 1, S0 = 0 IO/M = 0, S1 = 0, S0 = 1

RD bc bc bc

bc bc bc

WR bc

bc
Previous Questions

2018

Addn. Endsem
1. Which of the following instructions will be used in I/O mapped IO scheme: [1]
STA 9000H , or OUT 20H
2. The content of the accumulator is 50H . What would be the content of accu- [1]
mulator and zero flag after the execution of CMP A instruction in 8085 micro-
processor?
3. If the time required to execute MOV B,C is 2µs, then find the time required to [1]
execute ADD M in the same microprocessor system
4. Identify the addressing modes and name the machine cycles used to fetch and [3]
execute each of the following instructions individually.
i. LDAX D ii. CMA iii. SHLD 2000H
5. Define a clock cycle and a machine cycle. Draw the timing diagram for fetching [1+3]
and executing the instruction STAX B and explain the various signals used in
the timing diagram. [Opcode for STAX B is 02H ]
6. Short notes: Difference between memory-mapped IO and IO-mapped IO. [2.5]
Endsem
1. List the machine cycles used to fetch and execute the instruction LXI H, [1]
5050H .
2. Explain the functioning of stack using PUSH and POP instructions. [3]
3. Identify the addressing modes and name the machine cycles used to fetch and [2]
execute each of the following instructions individually.
i. LHLD 2020H ii. MOV A,M
4. Draw the timing diagram for fetching and executing the instruction STA [3]
1947H . Explain the various signals used in the timing diagram. [Opcode
for STA is 32H ]
5. Differentiate between SUB and CMP instructions and JMP and CALL instructions [2]
of 8085.
6. Short notes: Rotate instructions of 8085 [2.5]

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7. Short notes: Memory-mapped IO and IO-mapped IO [2.5]
Midsem
1. What would be the contents of accumulator after the execution of the following [0.5]
instructions: MVI A, 0FH and XRI 0FFH .
2. For accessing IO location 6100H in a memory mapped IO scheme which in- [0.5]
struction/s can be used
3. The contents of [SP], [[SP]] and [[SP]+1] are presently 209CH , CCH and 47H [1]
respectively. What would be the contents of [SP] and [DE] after the execution
of the instruction POP D?
4. If the time required to fetch and execute the instruction LDAX B is 3.5µs, then [1]
find the clock frequency.
5. With suitable instruction/s discuss how Z flag is set. [1]
6. Draw the timing diagram for INA machine cylce for fetching and executing the [3]
instruction RST 6 and explain the various signals used in the timing diagram.
[Opcode for RST 6 is F7H ]
7. What operations are performed on execution of the following instructions? [2]
Also identify the addressing modes for each of them.
i. DAA ii. CMP M
8. Name the machine cycles used to fetch and execute each of the instructions. [1]
i. LHLD 4BCDH ii. SUB M
9. Find the content of accumulator and flag register after the execution of MVI [1]
A, 77H and XRA A instructions.
10. Explain the addressing modes of 8085 with examples. [3]
11. Draw the timing diagram for fetching and executing the instruction INR M and [3]
explain the signals used in the timing diagram. [Opcode of INR M is 34H ]

2017

Endsem
1. If a crystal of 4MHz is connected across X1 and X2 pins of an 8085 micro- [1]
processor, what would be the time taken to execute the instruction CALL
5000H

26
2. What is the difference between INA and Opcode Fetch machine cycle? Draw [1+3]
the timing diagram for fetching and executing a one byte RST 5 opcode from
the external hardware and explain the various signals shown in the timing
diagram. [Opcode of RST 5 is EFH ]
3. Identify the addressing modes and name the machine cycles to fetch and exe- [3]
cute the following instructions.
i. SHLD 8085H ii. CMP M iii. ADI 80H
4. Short notes: Rotate instructions of 8085 [2.5]

Midsem
1. The contents of [SP], [[SP]] and [[SP]+1] are presently 3375H , 66H and 00H [1]
respectively. What would be the contents of [SP] and [BC] after the execution
of the instruction POP B?
2. Identify the machine cycles to fetch and execute the following instructions. [1]
i. LHLD 6000H ii. ADD M
3. If a crystal of 2MHz is connected across X1 and X2 pins of an 8085 micro- [1]
processor, what would be the time taken to execute the instruction STA
3050H ?
4. After the execution of the instructions MVI A, 0C8H and CPI 0C8H , what [1]
would be the status of accumulator and the zero flag?
5. What is the basic difference between IO-mapped and memory-mapped IO [2]
schemes?
6. Define a machine cycle and T-state. Draw the timing diagram for fetching and [1+3]
executing the instruction OUT 0FH and explain the various signals used in the
timing diagram. [Opcode for OUT is D3H ]
7. Explain what operations are performed on execution of the following instruc- [3]
tions? Also identify the addressing modes for each of them.
i. RLC ii. DAA iii. STAX D

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