VLSIGURU DFT TRAINING SCAN INSERTION LABS

SCAN INSERTION LABS GUIDELINES

1. Login to Unix
2. SCAN SETUP
3. DIRECTORY STRUCTURE
4. TOOL USAGE
5. SCAN INPUTS and OUTPUTS
6. DIFFERENT MODES OF SCAN INSERTION
7. TOOLS COMMANDS
8. STEPS FOR SCAN INSERTION
9. OBSERVATIONS

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1. LOGIN TO UNIX
Unix commands are very important for DFT labs. Unix commands are case sensitive.
Before scan insertion labs, please go through basic commands of Unix. Please refer
basic VIM editor manual for all unix commands.
IT ADMIN will provide below info and software

• VNC is created for each user and get VNC login id & password from the IT
admin.
• Also get IP address of your VNC
• Install software for putty and VNC viewer from the IT admin
• Whoever want VPN connections, please discuss with institutions head. Need
to install cybercrome.
• VNC user id and password and VPN user id and password are different.
Please find below steps for login VNC Unix
Steps to login into UNIX
Step 1: Click on the putty icon which is saved on the desktop. Please enter ip address
of your VNC. Then enter your user id and password which is shared by the IT Admin.
Pleas find below snapshot for enter your vnc user id and password
Open Putty
Enter Login ID and Password

Now enter vncserver (Lower case). It will give information about your vncserver number.
Please don’t create multiple vncserver. Each time login, vncserver number is different.
Please find below snapshot for vncserver.

Now it shows desktop number, in above snapshot desktop number is 7

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Step 2:
Open VNC and enter server number along with desktop number as shown below and
click on continue

After clicking on continue, below window will pop up. Enter password and click on
OK .

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Once you login with your password , it will direct you to UNIX desktop as show in
below

Do right click and click on open Terminal

Once clicking on open terminal it will open terminal as shown in below

Steps to Execute Test Cases

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2. SCAN INSERTION STEPS

Please find below steps for Scan Insertion
STEPS
Step1: - Hope all got all got UNIX, VPN Account and able to access
Step2: - mkdir /home/<user_name>/scan_insertion
Step3: - cd /home/<user_name>/scan_insertion
Step4: - cp -rf
/home/tools/Mentor/DFT_Training/kiran/Scan_insertion /home/<user_name>/sca
n_insertion
Step5: - tcsh (press Enter)
Step6: - source /home/tools/mentor/cshrc_mentor
Step7: - cd scan
Step8: - cd case1
Step9: - Source run_dft
SCAN INSERTION

• Scan Controllability and observability.

• Please go through all test cases and read each test case problem definition.
• Analyse all clocks, Resets, Scan chain information.
• Analyse all reports like scan cells, scan chains.
• Analyse all DRC rules
• Read all Warnings in log files
• Tool commands as per design requirements
• Understand all input and output files
NOTES
Note1:- Scan insertion has 12 Labs, Please go through README and follow
instruction and go through LAB_QUESTION
Note2:- Add command set_context dft -scan in the beginning of the dofile
Note3:- Add read_veriog < Netlist path> in the run file or dofile after above
command
Note4:- Dump all reports like scan cells.rpt, scan_chains.rpt, DRC.rpt, nonscan.rpt,
clock.rpt
Note5:- Please go through complete log file each line, analyze Warnings, Errors
Note6:- Understand Corresponding DRC rules like S1 is scan rule violations
Note7:- Analyze Clocks and Resets are controllable means Clock path should be clean,
it should not come from combo or sequential
Note8:- Please tool manual for different commands.

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3. DIRECTORY STRUCTURE
Please find below directory structure for all test cases. There are twelve testcases in
scan insertion labs exercises
scan_insertion:- parent directory
scan :- subdirectory
case1:- Each test case directory
netlist:- this directory has synthesis netlist which released by the synthesis team.

log:- This directory consists of scan insertion log file. Log file consists of all
commands, warnings, errors. Its mandatory needs to understand competently
dofie:- This directory is consists of scan insertion dofile. Dofile contains set of tool
commands which execute scan insertion flow. Dofile is always vary from all different
test cases

report:- This directory consists of all report files which are dumped by the tool. It is
mandatory to understand all report files
output:- This directory consists of Scan inserted netlist, Scan deffile and ATPG Setup
files. Scan inserted netlist is output of the Scan insertion flow and it is used
compression as input file. Scan Def file is required for physical design team. ATPG
Setup files required for the pattern generation

scan_insertion
|
scan
|____ case1
|___netlist
|___log
|___dofile
|___report
|___output

Run file
run_dfta -> run file to invoke the tool.
Problem definition file

readme -> describes the testcase

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4. TOOL USAGE
Mentor Tessent Shell tool is used for Scan insertion flow. Tessent Scan, which is
Tessent Shell operating in “dft -scan” context
Please find below command is used for source tessent shell tool
source /home/tools/mentor/cshrc_mentor
after sourcing above command, need to check tool is sourced or not. Please use
below command
which tessent. It will display tool path on the terminal.

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5. SCAN INPUTS AND OUTPUTS

INPUTS
1. Synthesis Netlist
Synthesis netlist is released by the Synthesis team. Synthesis netlist has D
Flip-Flops with DFF standard cell and check all combinational gates with
standard cells
2. Library cells
It is in .mdt format. Standard cells library is released by the Standard Cell
Design team. Standard cells are based on the technologies like 22nm, 14nm,
7nm, 5nm. It has all combinational and sequential logic gates. Observe DFF
flops with cells and SDFF flops with cells with primitives
3. Tools commands
Read netlist with verilog

Read library with .mdt

Define clocks
Define reset
As per design add tool commands. Please refer tshell_ref documents for all
commands and DRC rules.
OUTPUTS
1. Scan Inserted Netlist

It is scan inserted netlist. Check SI to Q connections. It has SDFF flops with

Standard cells

2. ATPG Dofile
It has clocks and resets definitions. Also, it has all scan chains information
3. ATPG Test proc
It has all procedures like test_setup, shift, load_unload

4. SCAN DEF
It has scan chain information as per Physical design requirements

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5. Reports
Design Rules Checking (C1, C2, S1, S2, D5, D6)
Scan chain reports and Scan cells reports

Clock and reset Reports

Report dft check
Report_pin_constraints
Also dump necessary reports based on the test cases and project wise

6. Logs
Please go through complete log file and note all points. Analyse all warnings
DRC and Errors

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6. DIFFERENT MODES OF SCAN INSERTION

The default system mode after tool invocation is setup. The context the tool is in
determines which system mode you can specify with the set_system_mode
command. See the Tessent Shell User’s Manual for more information about contexts
and system modes

Set system Setup

Setup :-A required literal that specifies to enter Tessent Shell setup mode. This is
the default. Used as the entry point into the tool. Used to define the current context
and specify the design information. In this mode, read netlist, read library models,
define clocks, resets, constraints using command

Set system Analysis

analysis:-A required literal that specifies to enter Tessent Shell analysis mode.
Used to perform design editing and introspection. In this mode, tool analyses clocks,
resets, checking all design rules, analysing scan chains, analysing wrappers

Set system insertion

insertion:- A required literal that specifies to enter Tessent Shell insertion mode.
Used to perform design analysis, test pattern generation, PDL retargeting, and
simulation.

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7. TOOLS COMMANDS
Invoke Tessent Shell
Read in Verilog source file (Netlist), assign library file and assign log file.
All these switches are defined in the run file
tessent -shell -verilog netlist.v -lib tsmc.mdt -log case.log
Specify clocks
Clocks are primary input signals that change the state of sequential logic
elements. Adds scan or non-scan clocks to the clock list for proper scan operation.
Declares a pin or a port as a clock. The defined clock may be of type source or a
generated source.
Resets are primary input signals that reset the state of sequential logic
elements. Bases on the design it may active low or active high.
Setup> add_clocks 0 clk
Setup> add_clocks 1 reset

Setup Test Logic configuration

Test logic options make clock, set and rest lines controllable to get a
scannable design
Setup> set_test_logic -clock on -set on -reset on
Enter to DFT mode
Enter scan insertion system mode and perform scan identification. Analyse all DRC
violations. Fix all DRC rules and also check all clocks and reset are reaching to all
Flops. Report detailed statistical report of scan identification, sequential instances
and scannable instances
Setup> set_system_mode dft
Please check below all below DRC rules

General Rules
Procedure Rules
Scan Chain Trace Rules
Scan Cell Data Rules
Clock Rules
Ram Rules
BIST Rules
EDT Rules
Timing Rules

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Insert scan chain and Review report

Set number of scan chains to insert. Also use clock mixing, edge mixing
Analysis>Insert_test_logic -number8
The tool inserts test structures into a design to increase the fault coverage
(testability) of the design. Specifically, the tool attempts to increase a design’s fault
coverage with the insert_test_logic command by doing the following:
• Identifies sequential cells and replaces them with corresponding scan cells,
and stitches them together into a scan chain. (Referred to as scan cell
replacement and stitching.)
• Supports the adding of both system-defined and user-defined test points.
• Supports the automatic adding of test logic.
Analysis> report_scan_chains
Displays a report on all the current scan chains.
Analysis> report_scan_cells
Displays a report on the scan cells that reside in the specified scan chains
Analysis>report_scan_groups
Displays a report on all the current scan chain groups.
Analysis>report_dft_signals
Reports all the DFT signals added or to-be-created in the design.
Analysis>report_drc_rules
Displays either a summary of DRC violations (fails) or violation occurrence
message(s).
Output scanned design
Write scan inserted netlist using tool command and use same scan inserted
netlist for Compression and ATPG Pattern generation. Write Scan Def file for physical
team to scan-ordering purpose. Also Write ATPG setup files for ATPG pattern
generation
Write_netlist scan_insert.v -verilog -replace
Write_scan_order case.scandef
Write_atpg_setup case.dofile

8. STEPS FOR SCAN INSERTION

9. OBSERVATIONS

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