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    Data Sheet: 74HC/HCT238

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    Andrew S Olmosn
    The document describes a 3-to-8 line decoder/demultiplexer integrated circuit. It has 3 address inputs (A0, A1, A2) that are decoded to provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). It has multiple enable inputs, including two active LOW (E1, E2) and one active HIGH (E3), allowing expansion to more outputs. The circuit can decode memory chip selects or function as an 8-line demultiplexer. The document provides detailed specifications, pinouts, logic diagrams, truth tables and more.

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    © All Rights Reserved
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    Data Sheet: 74HC/HCT238

    Uploaded by

    Andrew S Olmosn
    40 views7 pages
    The document describes a 3-to-8 line decoder/demultiplexer integrated circuit. It has 3 address inputs (A0, A1, A2) that are decoded to provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). It has multiple enable inputs, including two active LOW (E1, E2) and one active HIGH (E3), allowing expansion to more outputs. The circuit can decode memory chip selects or function as an 8-line demultiplexer. The document provides detailed specifications, pinouts, logic diagrams, truth tables and more.

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    Componente electrónico

    Original Title

    Datasheet

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    The document describes a 3-to-8 line decoder/demultiplexer integrated circuit. It has 3 address inputs (A0, A1, A2) that are decoded to provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). It has multiple enable inputs, including two active LOW (E1, E2) and one active HIGH (E3), allowing expansion to more outputs. The circuit can decode memory chip selects or function as an 8-line demultiplexer. The document provides detailed specifications, pinouts, logic diagrams, truth tables and more.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views7 pages

    Data Sheet: 74HC/HCT238

    Uploaded by

    Andrew S Olmosn
    The document describes a 3-to-8 line decoder/demultiplexer integrated circuit. It has 3 address inputs (A0, A1, A2) that are decoded to provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). It has multiple enable inputs, including two active LOW (E1, E2) and one active HIGH (E3), allowing expansion to more outputs. The circuit can decode memory chip selects or function as an 8-line demultiplexer. The document provides detailed specifications, pinouts, logic diagrams, truth tables and more.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 7

    INTEGRATED CIRCUITS

    DATA SHEET
    For a complete data sheet, please also download:

    • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications


    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
    • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

    74HC/HCT238
    3-to-8 line decoder/demultiplexer
    Product specification December 1990
    File under Integrated Circuits, IC06
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    FEATURES provide 8 mutually exclusive active HIGH outputs


    (Y0 to Y7).
    • Demultiplexing capability
    The “238” features three enable inputs: two active LOW
    • Multiple input enable for easy expansion (E1 and E2) and one active HIGH (E3). Every output will be
    • Ideal for memory chip select decoding LOW unless E1 and E2 are LOW and E3 is HIGH.
    • Active HIGH mutually exclusive outputs This multiple enable function allows easy parallel
    • Output capability: standard expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
    decoder with just four “238” ICs and one inverter.
    • ICC category: MSI
    The “238” can be used as an eight output demultiplexer by
    using one of the active LOW enable inputs as the data
    GENERAL DESCRIPTION
    input and the remaining enable inputs as strobes. Unused
    The 74HC/HCT238 are high-speed Si-gate CMOS devices enable inputs must be permanently tied to their
    and are pin compatible with low power Schottky TTL appropriate active HIGH or LOW state.
    (LSTTL). They are specified in compliance with JEDEC
    The “238” is identical to the “138” but has non-inverting
    standard no. 7A.
    outputs.
    The 74HC/HCT238 decoders accept three binary
    weighted address inputs (A0, A1, A2) and when enabled,

    QUICK REFERENCE DATA


    GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

    TYPICAL
    SYMBOL PARAMETER CONDITIONS UNIT
    HC HCT
    tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
    An to Yn 14 18 ns
    E3 to Yn 16 20 ns
    En to Yn 17 21 ns
    CI input capacitance 3.5 3.5 pF
    CPD power dissipation capacitance per package notes 1 and 2 72 76 pF

    Notes
    1. CPD is used to determine the dynamic power dissipation (PD in µW):
    PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
    fi = input frequency in MHz
    fo = output frequency in MHz
    ∑ (CL × VCC2 × fo) = sum of outputs
    CL = output load capacitance in pF
    VCC = supply voltage in V
    2. For HC the condition is VI = GND to VCC
    For HCT the condition is VI = GND to VCC − 1.5 V

    ORDERING INFORMATION
    See “74HC/HCT/HCU/HCMOS Logic Package Information”.

    December 1990 2
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    PIN DESCRIPTION

    PIN NO. SYMBOL NAME AND FUNCTION


    1, 2, 3 A0 to A2 address inputs
    4, 5 E1, E2 enable inputs (active LOW)
    6 E3 enable input (active HIGH)
    8 GND ground (0 V)
    15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7 outputs (active HIGH)
    16 VCC positive supply voltage

    Fig.1 Pin configuration. Fig.2 Logic symbol.

    (a)
    (b)

    Fig.3 IEC logic symbol.

    December 1990 3
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    Fig.4 Functional diagram. Fig.5 Logic diagram.

    FUNCTION TABLE

    INPUTS OUTPUTS
    E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
    H X X X X X L L L L L L L L
    X H X X X X L L L L L L L L
    X X L X X X L L L L L L L L
    L L H L L L H L L L L L L L
    L L H H L L L H L L L L L L
    L L H L H L L L H L L L L L
    L L H H H L L L L H L L L L
    L L H L L H L L L L H L L L
    L L H H L H L L L L L H L L
    L L H L H H L L L L L L H L
    L L H H H H L L L L L L L H

    Note
    1. H = HIGH voltage level
    L = LOW voltage level
    X = don’t care

    December 1990 4
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    DC CHARACTERISTICS FOR 74HC


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: MSI

    AC CHARACTERISTICS FOR 74HC


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HC
    SYMBOL PARAMETER UNIT V WAVEFORMS
    +25 −40 to +85 −40 to +125 CC
    (V)
    min. typ. max. min. max. min. max.
    tPHL/ tPLH propagation delay 47 150 190 225 ns 2.0 Fig.6
    An to Yn 17 30 38 45 4.5
    14 26 33 38 6.0
    tPHL/ tPLH propagation delay 52 160 200 240 ns 2.0 Fig.6
    E3 to Yn 19 32 40 48 4.5
    15 27 34 41 6.0
    tPHL/ tPLH propagation delay 50 155 195 235 ns 2.0 Fig.7
    En to Yn 18 31 39 47 4.5
    14 26 33 40 6.0
    tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Figs 6 and 7
    7 15 19 22 4.5
    6 13 16 19 6.0

    December 1990 5
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    DC CHARACTERISTICS FOR 74HCT


    For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
    Output capability: standard
    ICC category: MSI

    Note to HCT types


    The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
    To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

    INPUT UNIT LOAD COEFFICIENT


    An 0.70
    En 0.40
    E3 1.45

    AC CHARACTERISTICS FOR 74HCT


    GND = 0 V; tr = tf = 6 ns; CL = 50 pF

    Tamb (°C) TEST CONDITIONS


    74HCT
    SYMBOL PARAMETER UNIT V WAVEFORMS
    +25 −40 to +85 −40 to +125 CC
    (V)
    min. typ. max. min. max. min. max.
    tPHL propagation delay 21 35 44 53 ns 4.5 Fig.6
    An to Yn
    tPLH propagation delay 17 35 44 53 ns 4.5 Fig.6
    An to Yn
    tPHL propagation delay 22 37 46 56 ns 4.5 Fig.6
    E3 to Yn
    tPLH propagation delay 18 37 46 56 ns 4.5 Fig.6
    E3 to Yn
    tPHL propagation delay 21 35 44 53 ns 4.5 Fig.7
    En to Yn
    tPLH propagation delay 18 35 44 53 ns 4.5 Fig.7
    En to Yn
    tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7

    December 1990 6
    Philips Semiconductors Product specification

    3-to-8 line decoder/demultiplexer 74HC/HCT238

    AC WAVEFORMS

    (1) HC : VM = 50%; VI = GND to VCC.


    HCT: VM = 1.3 V; VI = GND to 3 V.

    Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
    the output transition times.

    (1) HC : VM = 50%; VI = GND to VCC.


    HCT: VM = 1.3 V; VI = GND to 3 V.

    Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
    times.

    PACKAGE OUTLINES
    See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

    December 1990 7

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