Sequential Circuits

introduction
• The information stored in the memory elements at
any given time defines the present state of the
sequential circuit.
• The present state and the external inputs determine
the outputs and the next state of the sequential circuit
• We can specify the sequential circuit by
a time sequence of external inputs, internal states
(present sates and next states) and outputs
The sequential circuits can be classified depending on the timing of their signals
Synchronous sequential circuits and Asynchronous sequential circuits

In synchronous sequential circuits signals can affect the memory elements only
At discrete instants of time

In asynchronous sequential circuits change in input signals can affect memory

Element at any instant of time

The memory elements used in both circuits are flip-flops which are capable of
Storing 1-bit binary information

Sequential circuits

Synchronous ASynchronous
 Flip-Flop and Latches
• Latches and flip-flops both are bitable elements
• These are the basic building blocks of most sequential circuits.
• The main difference between latches and flip-flop is in the
method used for changing their state
• Flip-flop used for a sequential device that normally samples
its input and changes its outputs only at times determined by
the clocking signal
• Latch is used for a sequential device that checks all of its
inputs continuously and changes its outputs accordingly at any
time independent of a clocking signal
• Many times enable signal is provided with the latch
• When enable signal is active output changes occur as input
changes. But when enable signal is not activated input changes
do not affect output
 Basic Flip-Flop

Basic Flip-flop circuit using NOR gate

Basic Flip-Flop using NAND gate
RS-Flip-Flop
 D Flip-Flop
• One way to eliminate the undesirable condition of the
indeterminate state in the RS flip-flop is to ensure that
inputs S and R are never equal to 1 at the same time. This
is done in the D flip-flop
• The D flip-flop receives the designation from its ability to
• Hold into its internal storage. This type of flip-flop is
sometimes called a gated D-latch
JK-Flip-Flop
T-Flip Flop
Triggering of Flip-Flops

The state of a flip flop is switched by a momentary change in the input signal
This momentary change is called a trigger

Clocked flip-flops are triggered by pulses. A pulse starts from an initial value
Of 0 goes momentarily to 1 and after a short time returns to its initial 0 value

The pulse goes through 2 signal transitions from 0 to 1 and return 1 to 0.

The positive transition is defined as the positive edge

And the negative transition as the negative edge
 Master-Slave Flip-Flop

It consists of clocked JK flip-flop as a master and clocked SR flip-flop as a slave.

The output of the master flip-flop is fed as an input to the slave flip-flop.
This flip-flop that have an additional inverter between the CP terminal and the
Input of the master such flip-flops are triggered with negative pulses. So that the
Negative edge of the pulse affect the master and the positive edge affects the
Slave and the output terminal.
 D Flip-Flop
state table and state diagram
T Flip-Flop
SR Flip-Flop
JK Flip-Flop
Conversion of JK Flip-Flop to SR Flip-Flop
SR Flip-Flop to D Flip-Flop
D Flip-Flop to SR Flip-Flop
JK Flip-Flop TO T Flip-Flop
JK Flip-Flop To D Flip-Flop
D Flip-Flop To JK Flip Flop
Analysis and synthesis of sequential circuit
State Table
Stable table
 Register
• Flip flop is a binary cell capable of storing one bit information. they
can be connected together to perform counting operation. Such a
group of flip flop is called COUNTER.
• An array of flip flop is used to store the binary information known as
register.
• Each flip-flip stores one bit information so an N-bit register has a
group of N flip-flops and is capable of storing any binary information
number containing n-bits
• Need of a register 1. temporary storage 2.Shifting capability.
• Concept of storing the data in a register:
A binary 1 is applied as a input and a clock pulse is applied that
stores 1 by setting the flip flop. when the input 1 is removed note
that the flip-flop remain in the SET state thereby storing the 1.The
same procedure is applied for the storing of 0.
• The storage capacity of a register is the
number of bits (1’s and 0’s) of digital data
that it can retain.
Each storage of register represents one bit
of storage capacity and therefore the
number of storage in a register determines
its total storage capacity.
 Buffer register
4 bit buffer register

The input X-bits(XoX1X2X3) set up the flip flop for loading Therefore
when the first clock Pulse arrives all the X-bits are loaded into D-
inputs of all the flip-flops then the Stored binary information is
Q=Q3Q2Q1Q0 =X3X2X1Xo
For example if we want to store a 4-bit binary information 1001 in the
buffer register then these bits are applied at X-bits as
Then the stored binary word =Q=1001
 Data movement in a registers

Basically data can be entered in 2 forms

1.Serial (One bit at a time i.e, bit by bit)
2.Parallel (all the bits simultaneously) and are called as serial form and
parallel form
Respectively.

The data movement in the register is concerned with two characteristics. They are
1.How the binary information is loaded into register
2. How to read the data from the register
According to that the registers are classified into 4 possible modes of operations
They are (a) Serial in-Serial out
(b) Serial in-Parallel out
(C) Parallel in-Serial out
(d) Parallel in-parallel out
Serial in-Serial out
Data movement
SISO-Right shift
SISO
 SIPO Shift Register

In this data bits are entered into the register in serial manner.
But the output Is taken in parallel. once the data bits are stored
each bit appears on its respective output line and all bits are
available simultaneously
PISO-Shift register
 PIPO Shift Register

In parallel in parallel out register there is simultaneous entry of all data bits
And the bits appear on parallel outputs simultaneously.
 Bidirectional shift register

The type of a register allowing shifting of data either to left or to the right side is
Called bidirectional shift register. it has circuit implemented by using logic gates
That enables the data transfer from one stage to the next stage to the right or left
Depending on the level of the control line i.e.
• Operation:
(1) When control input is at High level the gates G1 to G4 are enabled and the state of the Q
output of each flip0flop is passed through to the D input of the respective flip flop. When
clock pulse occurs then the data is shifted by one place to the right
(2) When the control input is at LOW level then the gates G5 to G8 are enabled
and the state of the Q output of each Flip-flop is passed through to the Di of the preceding flip
flop. When clock pulse occurs then data is shifted by one place to the left
Thus when is high data is shifted to right and when is low data is shifted to left. Here
data can be shifted left or right depending on the control input
• A universal shift register is one that has both serial and parallel inputs. It
contain two control pins named S0 and S1 according to the value of S0
and S1 the register will perform different types of operations.
• Operation:
(1) When S0=1 and S1=0 the shift right operation is done
synchronously with the positive edge of the clock. In this
mode the serial data is entered at the shift-right-serial input.
(2) When S0=0 and S1=1then shift left operation is done in
synchronous with the clock. In this mode the serial data is
entered at the shift-left serial input
(3) When So=S1=1 parallel loading operation is done in synchronous with
a positive transition of the clock.
(4) When S0=S1=0 then we have inhibit clock operation in this mode the
operation will inhibit the shifting of data in the shift register
The 4-bit asynchronous counter is also called as divide-by-16 counter because
The frequency of the output waveform of D flip-flop is equal to the clock
Frequency/16 OR fd=f/16 where f=clock frequency, fd=frequency of ff output
Basic Method for designing the ripple counter
whose count is <2n
1.Here N=6 and the number of flip-flop required in n=[log26] =3 .Thus use of 3 JK
flip-flops is necessary and they are named as A, B and C.
2. If we assume a starting count of 000 the diagram shows that the states of the counter
change normally until the count of 101. when the next clock pulse occurs
The count temporarily goes to 110 count before going to the stable 000 count

the dotted lines indicate the temporary nature of the 110 state. The direction of this
Temporary state is so short that for most purposes we can consider that the counter
Goes directly from 101 to 000.note that the 111 state was never reached, not even
Temporarily .
The inputs to the NAND gate are the outputs of the flip-flop B and C so the NAND
Gate output is LOW when QB=1 and QC=1 until that the NAND gate output is HIGH
(which does not affect the clear input of any flip-flop) This condition will occurs
When the counter goes from 101 state to the 110 state (6th clock pulse). The LOW
signal at the NAND gate output will immediately (generally a few nanoseconds )
Clear the counter to 000 state once the flip-flops have been cleared the NAND
output
Goes back to HIGH since the QB=1 and Qc=1 condition no longer exists.

The counting sequence is therefore 000, 001,010,011,100,101 and (temporary

state),000. this type of counter is some times called “permuting counter”, since its
natural count has been changed.

Although the counter goes to the 110 stae, it remains for only few nano seconds
before it recycles to 000. thus we can essentially say that this counter counts from
000 to 101 and then recycles to 000. it essentially skips 110 and 111 so that it goes
through only six different (000 to 101) states, thus , it ia called MOD-6 counter.
A decimal counter follows a sequence if ten states and returns to 0 after the
count Of 9 the counter with ten states in their sequence called are decade
counters. These counters are useful in display applications in which BCD is
required for Conversion to a decimal read out. A counter with a count sequence
of 0 (0000) Through 9 (1001) is called a BCD counter. because its ten states
sequence is The BCD code. The sequence of states is shown in the state
diagram.
 Design of Synchronous counter

Design Procedure:
Step 1. Determine the number of flip-flops needed, i.e., desired number of bits and
The desired counting

Step 2. Choose the type of flip-flop to be used either JK, D or T etc

Step3. Draw the state transitions showing all possible states including those that
Are not part of the desired counting sequence.

Step 4. Use state transitions to obtain the state table that lists all present states and
Next states

Step 5. From the state table derive the circuit excitation table

Step6. Use K-map or any other simplification method to derive the circuit as flip-flop
Input functions ie., design the logic circuits to generate the levels required at
Each flip-flop input.

Step 7.Draw the logic diagram, i.e., implement the final expression
Mistakes are there in the function table
Operation: M is a control input which determines the basic operation of the
Counter. when this input is HIGH we have UP mode of operation and when
It is low we have DOWN mode of operation. The output of the counter is
Q=QCQBQA
Input combinations are wrong
Generate the sequence 10101 using D flip flop
•SSI are the least complex and include basic gates and flip flops.

•Small digital sub systems forms the MSI category. More complex logic
Functions e.g adders, registers, comparators, code converters, counters
Multiplexers etc are fabricated in MSI.

•LSI chips are small digital systems, e.g., digital clocks, calculator,
microprocessors,
ROM, RAM etc
VLSI is a digital system on a chip. Large memory chips and advanced
Microprocessors fall in this category

ULSI is the most complex of digital ICs

 Problem1 A digital gate has an input voltage Vcc equal to 5V. The input current
Is 2mA for high output and 3.4mA for low output. Find the power dissipation.

Sol: Avg value of input current (2+3.4)/2=2.7mA

Power dissipation= 5*2.7=13.5mW

Problem2: A NOT gate has VIL=0.8V VIH=2.5V VOL=0.4V, VOH=3.6V If two such
Gates are cascaded find the low and high noise margins.

Sol: NML=VIL-VOL=0.8-0.4=0.4V
NMH=VOH-VIH=3.6-2.5=1.1V

Wired AND logic

The NAND gates with outputs tied together. This connection creates An additional
AND function without addition of any gate and is known as Wired-AND logic. It is
Also called implied AND or dot And or collector logic