Data Sheet: Advanced Pager Receiver

INTEGRATED CIRCUITS
DATA SHEET
UAA2082
Advanced pager receiver
Product specification 1996 Jan 15
Supersedes data of 1995 Nov 27
File under Integrated Circuits, IC03
Philips Semiconductors Product specification
Advanced pager receiver UAA2082
FEATURES GENERAL DESCRIPTION

• Wide frequency range: VHF, UHF and 900 MHz bands The UAA2082 is a high-performance low-power radio
• High sensitivity receiver circuit primarily intended for VHF, UHF and
900 MHz pager receivers for wide area digital paging
• High dynamic range
systems, employing direct FM non-return-to-zero (NRZ)
• Electronically adjustable filters on chip frequency shift keying (FSK).
• Suitable for data rates up to 2400 bits/s The receiver design is based on the direct conversion
• Wide frequency offset and deviation range principle where the input signal is mixed directly down to
• Fully POCSAG compatible FSK receiver the baseband by a local oscillator on the signal frequency.
Two complete signal paths with signals of 90° phase
• Power on/off mode selectable by the chip enable input difference are required to demodulate the signal.
• Low supply voltage; low power consumption All channel selectivity is provided by the built-in IF filters.
• 1-cell battery-low detection circuit The circuit makes extensive use of on-chip capacitors to
minimize the number of external components.
• High integration level
• Interfaces directly to the PCA5000A, PCF5001 and The battery monitoring circuit has an external sense input
PCD5003 POCSAG decoders. and a 1.1 V detection threshold for easy operation in a
single-cell supply concept.
APPLICATIONS The UAA2082 was designed to operate together with the

PCA5000A, PCF5001 or PCD5003 POCSAG decoders,
• Wide area paging which contain a digital input filter for optimum call success
• On-site paging rate.
• Telemetry
• RF security systems
• Low bit-rate wireless data links.
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
UAA2082H LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1
UAA2082U 28 pads naked die; see Fig.8
1996 Jan 15 2
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VP supply voltage 1.9 2.05 3.5 V
IP supply current 2.3 2.7 3.2 mA
IP(off) stand-by current − − 3 µA
Pi(ref) RF input sensitivity BER ≤ 100; ±4 kHz deviation;
3⁄
data rate 1200 bits/s; Tamb = 25 °C

fi(RF) = 173 MHz − −126.5 −123.5 dBm
fi(RF) = 470 MHz − −124.5 −121.5 dBm
fi(RF) = 930 MHz − −120.0 −114.0 dBm
Pi(mix) mixer input sensitivity BER ≤ 100; fi(RF) = 470 MHz;
3⁄ − −115.0 −110.0 dBm
±4 kHz deviation;
data rate 1200 bits/s; Tamb = 25 °C
Vth detection threshold for battery Tamb = 25 °C 1.05 1.10 1.15 V
LOW indicator Tamb = −10 to +70 °C 1.03 1.10 1.17 V
Tamb operating ambient temperature −10 − +70 °C
1996 Jan 15 3
V bias(osc)
C20
1 nF
VP
1996 Jan 15
R5 R6 L8 R3
C18 C15 R7 C14 C13 C19
1.5 22 27 1.5 kΩ
1 nF nH 27 pF 100 Ω 1 nF 10 µF 1 nF
kΩ C16 XTAL kΩ L7 L6
L9 13 to
50 pF 33 nH 33 nH
560
Philips Semiconductors
nH R4
SENSE
C17 2.2 kΩ C12
15 pF GND3 5 to 20 pF
32 31 30 28 27 26 25
BLOCK DIAGRAMS (173 MHz)
TS 1 CRYSTAL FREQUENCY
24
OSCILLATOR MULTIPLIER
BATTERY 22
LOW R2
INDICATOR low noise 47
LIMITER amplifier Q 21 kΩ
Q GYRATOR ACTIVE
BLI 2
FILTER FILTER 20
to DO 3 DEMO- GND2
4
decoder DULATOR
RE 4
GYRATOR ACTIVE
TPI 5 MIXER Q
LIMITER FILTER FILTER
IF testpoints TPQ 6 I low noise 19
C1 amplifier I
8.2 pF
7 18
V i(RF) RF pre-amplifier
L1 BAND GAP
43 C3 REFERENCE MIXER I
nH 5 to
20 pF 8 VP Vref UAA2082H
10 11 12 13 14 15 16
C2
GND1 L4 L5
8.2 pF
330 L2 L3 C10 C11 150 150
R1 C5 1 nF 22 pF nH
Ω 22 nH 22 nH 22 pF nH
C6 C7 C9
5 to 8.2 pF
C4 1 nF 20 pF 8.2 pF
C8 MLC222
VP 8.2 pF
Pins 9, 17, 23 and 29 are not connected.
handbook, full pagewidth
Fig.1 Block, test and application diagram drawn for LQFP32; fi(RF) = 172.941 MHz.
UAA2082
Product specification
V bias(osc)
C20
1 nF
1996 Jan 15
C18 R5
VP
R6 L8 C15 C13 R3
1 nF 1.5 kΩ R7 C14 C 19
22 27 27 10 µF 1.5 kΩ
C16 100 Ω 1 nF 1 nF
L9 kΩ nH pF L7 L6
13 to XTAL
BLI 560 nH 50 pF
33 nH 33 nH
DO C17 R2
decoder
RE R4
SENSE
2.2 kΩ C12 47 kΩ
TS 15 pF GND3 5 to 20 pF
28 27 26 25 24 23 22 21 20 19 18 17 16 15
BAND GAP CRYSTAL FREQUENCY

REFERENCE OSCILLATOR MULTIPLIER
BATTERY
VP Vref low noise
LOW
UAA2082U amplifier
INDICATOR
Q
GYRATOR ACTIVE
LIMITER
DEMODULATOR
Q
FILTER FILTER
5
GYRATOR ACTIVE
LIMITER
I
FILTER FILTER
low noise
amplifier
RF pre-amplifier I
MIXER I MIXER Q
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TPI TPQ C3 10 pF 10 pF L4 GND2

330 L3 L2 150
R1 C5 1 nF L5
IF testpoints Ω GND1 22 nH 22 nH 8.2 pF C10 C11
5 to 20 pF nH
150
C6 C7 C9 nH
C1 L1 C2 5 to 20 pF 8.2 pF
43 nH C4 1 nF C8
8.2 pF 8.2 pF MLC223
V i(RF) VP 8.2 pF
Fig.2 Block, test and application diagram drawn for naked die; fi(RF) = 172.941 MHz.
UAA2082

Table 1 Tolerances of components shown in Figs 1 and 2 (notes 1 and 2)

TOLERANCE
COMPONENT REMARK
(%)
Inductances
L1 ±5 Qmin = 100 at 173 MHz
L2, L3, L6, L7 ±20 Qmin = 50 at 173 MHz; TC = (+25 to +125) × 10−6/K
L4, L5 ±10 Qmin = 30 at 173 MHz; TC = (+25 to +125) × 10−6/K
L8 ±20 Qmin = 30 at 173 MHz; TC = (+25 to +125) × 10−6/K
Resistors
R1 to R7 ±2 TC = +50 × 10−6/K
Capacitors
C1, C2, C7, C8, C9, C15 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 30 × 10−4 at 1 MHz
C3, C6, C12 − TC = (−750 ±300) × 10−6/K; tan δ ≤ 50 × 10−4 at 1 MHz
C10, C11 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 21 × 10−4 at 1 MHz
C13 ±20
C16 − TC = (−1700 ±500) × 10−6/K; tan δ ≤ 50 × 10−4 at 1 MHz
C17 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 26 × 10−4 at 1 MHz
Notes
1. Recommended crystal: fXTAL = 57.647 MHz (crystal with 8 pF load), 3rd overtone, pullability >2.75 × 10−6/pF
(change in frequency between series resonance and resonance with 8 pF series capacitor at 25 °C), dynamic
resistance R1 < 40 Ω, ∆f = ±5 × 10−6 for Tamb = −10 to +55 °C with 25 °C reference, calibration plus aging tolerance:
−5 × 10−6 to +15 × 10−6.
2. This crystal recommendation is based on economic aspects and practical experience. Normally the spreads for R1,
pullability and calibration do not show their worst case limits simultaneously in one crystal. In such a rare event, the
tuning range will be reduced to an insufficient level.
1996 Jan 15 6
V bias(osc)
C20
1 nF
VP
1996 Jan 15
R5 R6 L8
C18 C14 C13 R3
1.5 22 100 C15 C19
1 nF 1 nF 10 µF 820 Ω
kΩ C16 XTAL kΩ nH 3 to 1 nF L7
L9 13 to 10 pF
50 pF 8 nH L6
560 8 nH
nH R4
SENSE
C17 1.2 kΩ C12
15 pF GND3 2.5 to 6 pF
32 31 30 28 27 26 25
24
BATTERY 22
LOW R2
BLOCK AND TEST DIAGRAMS (470 MHz)

amplifier Q 21 kΩ
LIMITER
Q GYRATOR ACTIVE
BLI 2
FILTER FILTER 20
to DO 3 DEMO- GND2
7
decoder DULATOR
RE 4
GYRATOR ACTIVE
TPI 5 MIXER Q
C1 amplifier I
2.7 pF
7 18
L1 BAND GAP
12.5 C3 REFERENCE MIXER I
nH 2.5 to
10 11 12 13 14 15 16
C2 L4 L5
2.7 pF GND1 40 40
330 L2 L3 C10 C11
R1 nH nH
Ω 8 nH 8 nH C5 1 nF 22 pF 22 pF
C6 C7 C9
2.5 to 2.7 pF
C4 1 nF 6 pF 2.7 pF
C8 MLC224
VP 2.7 pF
Fig.3 Block, test and application diagram drawn for LQFP32; fi(RF) = 469.95 MHz.
UAA2082
V bias(osc)
C20
1 nF
1996 Jan 15
C18 R5 VP
R6 L8 C13 R3
1 nF 1.5 kΩ C14 C 19
22 100 C15 10 µF 820 Ω
C16 1 nF 1 nF
L9 kΩ nH 3 to L7 L6
13 to XTAL
560 nH 10 pF
BLI 50 pF 8 nH 8 nH
DO C17 R2
decoder
RE R4
SENSE 47 kΩ
1.2 kΩ C12
TS 15 pF GND3 2.5 to 6 pF
28 27 26 25 24 23 22 21 20 19 18 17 16 15
BAND GAP CRYSTAL FREQUENCY

REFERENCE OSCILLATOR MULTIPLIER
BATTERY
VP Vref low noise
LOW
UAA2082U amplifier
INDICATOR
Q
GYRATOR ACTIVE
LIMITER
DEMODULATOR
Q
FILTER FILTER
8
GYRATOR ACTIVE
LIMITER
I
FILTER FILTER
low noise
amplifier
RF pre-amplifier I
MIXER I MIXER Q
1 2 3 4 5 6 7 8 9 10 11 12 13 14
TPI TPQ C3 22 pF 22 pF L4 GND2

330 L3 L2 40
R1 C5 1 nF
IF testpoints Ω GND1 8 nH 8 nH 2.7 pF C10 C11 L5
2.5 to 6 pF nH
40
C6 C7 C9 nH
C1 L1 C2 2.5 to 6 pF 2.7 pF
12.5 nH C4 1 nF C8
2.7 pF 2.7 pF MLC225
V i(RF) VP 2.7 pF
Fig.4 Block, test and application diagram drawn for naked die; fi(RF) = 469.95 MHz.
UAA2082
V bias(osc)
C20
1 nF
1996 Jan 15
VP
R5 R6 L8
C18 C14 C13 R3
1.5 22 100 C15 C19
1 nF 1 nF 10 µF 820 Ω
kΩ C16 XTAL kΩ nH 3 to 1 nF L7
L9 13 to 10 pF
50 pF 8 nH L6
560
8 nH
nH R4
SENSE
C17 1.2 kΩ C12
15 pF GND3 2.5 to 6 pF
32 31 30 28 27 26 25
24
MULTIPLIER
OSCILLATOR
BATTERY 22
LOW R2
amplifier Q 21 kΩ
LIMITER
Q GYRATOR ACTIVE
BLI 2
FILTER FILTER 20
9
to DO 3 DEMO- GND2
decoder DULATOR
RE 4
GYRATOR ACTIVE
TPI 5 MIXER Q
amplifier I
RF pre-amplifier 18
7 BAND GAP
REFERENCE MIXER I
8
VP Vref UAA2082H
10 11 12 13 14 15 16
L4 L5
GND1 C10 C11 40 40
22 pF 22 pF nH nH
V i(RF)
C5 C21 L10 C23
1 nF 5.6 pF 12.5 nH 2.5 to 6 pF
C22 MLC226
VP
5.6 pF
Fig.5 Mixer input sensitivity test circuit; fi(RF) = 469.95 MHz.

UAA2082
Table 2 Tolerances of components shown in Figs 3, 4 and 5 (notes 1 and 2)

TOLERANCE
COMPONENT REMARK
(%)
Inductances
L1, L10 ±5 Qmin = 145 at 470 MHz
L2, L3, L6, L7 ±20 Qmin = 50 at 470 MHz; TC = (+25 to +125) × 10−6/K
L4, L5 ±10 Qmin = 40 at 470 MHz; TC = (+25 to +125) × 10−6/K
Resistors
R1 to R6 ±2 TC = +50 × 10−6/K
Capacitors
C1, C2, C7, C8, C9 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 30 × 10−4 at 1 MHz
C3, C6, C12, C23 − TC = (−750 ±300) × 10−6/K; tan δ ≤ 50 × 10−4 at 1 MHz
C4, C5, C14, C18 to C22 ±10 TC = (0 ±30) × 10−6/K; tan δ ≤ 10 × 10−4 at 1 MHz
C10, C11 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 21 × 10−4 at 1 MHz
C13 ±20
C16 − TC = (−1700 ±500) × 10−6/K; tan δ ≤ 50 × 10−4 at 1 MHz
C17 ±5 TC = (0 ±30) × 10−6/K; tan δ ≤ 26 × 10−4 at 1 MHz
Notes
1. Recommended crystal: fXTAL = 78.325 MHz (crystal with 8 pF load), 3rd overtone, pullability >2.75 × 10−6/pF
(change in frequency between series resonance and resonance with 8 pF capacitor at 25 °C), dynamic resistance
R1 < 30 Ω, ∆f = ±5 × 10−6 for Tamb = −10 to +55 °C with 25 °C reference, calibration plus aging tolerance:
−5 × 10−6 to +15 × 10−6.
2. This crystal recommendation is based on economic aspects and practical experience. Normally the spreads for R1,
pullability and calibration do not show their worst case limits simultaneously in one crystal. In such a rare event, the
tuning range will be reduced to an insufficient level.
1996 Jan 15 10
VP
L8 C14
C13 R3
33 nH 150
4.7 µF 330 Ω
pF
1996 Jan 15
C15
Vi(OSC) C19 L7 L6
3.3 pF 150 pF 3 nH 3 nH
SENSE R4
390 Ω C12
GND3
1.7 to 3 pF
32 31 30 28 27 26 25
24
BATTERY 22
LOW
INDICATOR R2
low noise
47
BLOCK AND TEST DIAGRAM (930 MHz)
LIMITER amplifier Q 21
kΩ
Q GYRATOR ACTIVE
BLI 2
FILTER FILTER 20
to DO 3 DEMO- GND2
decoder DULATOR
RE 4
GYRATOR ACTIVE
11
TPI 5 MIXER Q
C1 amplifier I
1.2 pF
7 18
L1 BAND GAP
5 C3 REFERENCE MIXER I
nH 1.7 to
10 11 12 13 14 15 16
C2 L4 L5
GND1 C5
1.0 pF L10 L11 12.5 12.5
120 L2 L3 nH nH
R1 5 nH 5 nH
Ω 3.5 nH 3.5 nH 150 pF
C6 C7 C9
1.7 to 1.5 pF
C4 150 pF 3 pF 1.2 pF
C8 MLC227
VP 1.5 pF

Fig.6 Test circuit; fi(RF) = 930.50 MHz.

UAA2082
Table 3 Tolerances of components shown in Fig.6 (note 1)
TOLERANCE
COMPONENT REMARK
(%)
Inductances
L1 ±10 Qtyp = 150 at 930 MHz
L2, L3, L6, L7 − microstrip inductor
L4, L5 ±5 Qtyp = 100 at 930 MHz
L8 ±10 Qtyp = 65 at 310 MHz
L10, L11 ±10 Qtyp = 150 at 930 MHz
Resistors
R1 to R4 ±2 TC = (0 ±200) × 10−6/K
Capacitors
C3, C6, C12 − TC = (0 ±200) × 10−6/K; tan δ ≤ 30 × 10−4 at 1 MHz
C4, C5, C14, C19 ±10 TC = (0 ±30) × 10−6/K; tan δ ≤ 10 × 10−4 at 1 MHz
C13 ±20
Note
1. The external oscillator signal Vi(OSC) has a frequency of fOSC = 310.1667 MHz.
1996 Jan 15 12
PINNING (LQFP32)
SYMBOL PIN DESCRIPTION

TS 1 test switch; connection to ground
for normal operation
25 VO2MUL
27 SENSE
BLI 2 battery LOW indicator output
26 RMUL
30 GND3
28 OSC
32 OSE
31 OSB
handbook, halfpage
29 n.c.
DO 3 data output
RE 4 receiver enable input
TPI 5 IF test point; I channel
TS 1 24 VO1MUL
TPQ 6 IF test point; Q channel
BLI 2 23 n.c.
VI1RF 7 pre-amplifier RF input 1
DO 3 22 RGYR
VI2RF 8 pre-amplifier RF input 2
RE 4 21 COM
n.c. 9 not connected UAA2082H
TPI 5 20 GND2
RRFA 10 external emitter resistor for
pre-amplifier TPQ 6 19 VI2MQ
GND1 11 ground 1 (0 V) VI1RF 7 18 VI1MQ
VO2RF 12 pre-amplifier RF output 2 VI2RF 8 17 n.c.
VO1RF 13 pre-amplifier RF output 1

10
GND1 11
12
13
14
VI2MI 15
VI1MI 16
9
VP 14 supply voltage MLC228

n.c.
VP
RRFA
VO2RF
VO1RF
VI2MI 15 I channel mixer input 2
VI1MI 16 I channel mixer input 1
n.c. 17 not connected
VI1MQ 18 Q channel mixer input 1
VI2MQ 19 Q channel mixer input 2 Fig.7 Pin configuration; LQFP32.
GND2 20 ground 2 (0 V)
COM 21 gyrator filter resistor; common line
RGYR 22 gyrator filter resistor
VO1MUL 24 frequency multiplier output 1
VO2MUL 25 frequency multiplier output 2
RMUL 26 external emitter resistor for
frequency multiplier
SENSE 27 battery LOW detector sense input
OSC 28 oscillator collector
GND3 30 ground 3 (0 V)
OSB 31 oscillator base; crystal input
OSE 32 oscillator emitter
1996 Jan 15 13
CHIP DIMENSIONS AND BONDING PAD LOCATIONS

See Table 4 for bonding pad description and locations for x/y co-ordinates.
y
24 23 22 21 20 19
handbook, full pagewidth 25 18
26 17
27 16
28
15
3.83
mm UAA2082U
1 14
2 13
3 12
0
0
4 x
5 6 7 8 9 10 11
4.74 mm
MLC229
Where:
Pad number 1 (diameter 124 µm)
Pad 124 µm x 124 µm
Pad not used
Pad 100 µm x 100 µm
Pad 100 µm x 100 µm with reference point
Chip area: 18.15 mm2

Chip thickness: 380 ±20 µm.
Drawing not to scale.
Fig.8 Bonding pad locations.
1996 Jan 15 14
Table 4 Bonding pad centre locations (dimensions in µm)

SYMBOL PAD DESCRIPTION x y
TPI 1 IF test point; I channel −32 1296
TPQ 2 IF test point; Q channel −32 1000
VI1RF 3 pre-amplifier RF input 1 −32 360
VI2RF 4 pre-amplifier RF input 2; note 1 0 0
RRFA 5 external emitter resistor for pre-amplifier 472 0
GND1 6 ground 1 (0 V) 1160 0
VO2RF 7 pre-amplifier RF output 2 1 688 0
VO1RF 8 pre-amplifier RF output 1 2 232 0
VP 9 supply voltage 2 760 0
VI2MI 10 I channel mixer input 2 3 608 0
VI1MI 11 I channel mixer input 1 4 216 0
VI1MQ 12 Q channel mixer input 1 4 216 360
VI2MQ 13 Q channel mixer input 2 4 216 960
GND2 14 ground 2 (0 V) 4 216 1360
COM 15 gyrator filter resistor; common line 4 216 2024
RGYR 16 gyrator filter resistor 4216 2496
VO1MUL 17 frequency multiplier output 1 4216 3136
VO2MUL 18 frequency multiplier output 2 4176 3456
RMUL 19 external emitter resistor for frequency multiplier 3668 3458
SENSE 20 battery LOW detector sense input 2952 3456
OSC 21 oscillator collector 2312 3456
GND3 22 ground 3 (0 V) 1832 3456
OSB 23 oscillator base; crystal input 1328 3456
OSE 24 oscillator emitter 432 3456
TS 25 test switch; connection to ground for normal operation −32 3456
BLI 26 battery LOW indicator output −32 3136
DO 27 data output −32 2512
RE 28 receiver enable input −32 2152
lower left corner of chip (typical values) −278 −186
Note
1. All x/y co-ordinates are referenced to the centre of pad 4 (VI2RF); see Fig.8.
1996 Jan 15 15
INTERNAL CIRCUITS
handbook, full pagewidth 32 31 30 29 28 27 26 25

1
n.c.
2 5 kΩ
VP
24
3 5 kΩ
VP
4 150 kΩ
23
n.c.
22
21
UAA2082H
1 kΩ 1 kΩ
5
20
VP
VP
19
8
18
n.c. VP
150 Ω 17
n.c.
9 10 11 12 13 14 15 16
MLC493
Fig.9 Internal circuits drawn for LQFP32.
1996 Jan 15 16
1996 Jan 15
28 27 26 25 24 23 22 21 20 19 18 17 16 15
150
kΩ VP
5 5
kΩ kΩ
VP
VP
VP
UAA2082U
17
1 1 150 Ω
kΩ kΩ VP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
MLC231
Fig.10 Internal circuits drawn for naked die.

UAA2082
FUNCTIONAL DESCRIPTION The resonant circuit at output pin OSC selects the second
harmonic of the oscillator frequency. In other applications
The complete circuit consists of the following functional
a different multiplication factor may be chosen.
blocks as shown in Figs 1 to 6.
At 930 MHz an external oscillator circuit is required to
Radio frequency amplifier provide sufficient local oscillator signal for the frequency
multiplier.
The RF amplifier is an emitter-coupled pair driving a
balanced cascode stage, which drives an external
Frequency multiplier
balanced tuned circuit. Its bias current is set by an external
300 Ω resistor R1 to typically 770 µA. With this bias The frequency multiplier is an emitter-coupled pair driving
current the optimum source resistance is 1.3 kΩ at VHF an external balanced tuned circuit. Its bias current is set by
and 1.0 kΩ at UHF. At 930 MHz a higher bias current is external resistor R4 to typically 190 µA (173 MHz), 350 µA
required to achieve optimum gain. A value of 120 Ω is (470 MHz) and 1 mA (930 MHz). The oscillator signal is
used for R1, which corresponds with a bias current of internally AC coupled to one input of the emitter-coupled
approximately 1.3 mA and an optimum source resistance pair while the other input is internally grounded via a
of approximately 600 Ω.The capacitors C1 and C2 capacitor. The frequency multiplier output signal between
transform a 50 Ω source resistance to this optimum value. pins VO1MUL and VO2MUL drives the upper switching
The output drives a tuned circuit with capacitive divider stages of the mixers. The bias voltage on pins VO1MUL
(C7, C8 and C9) to provide maximum power transfer to the and VO2MUL is set by external resistor R3 to allow
phase-splitting network and the mixers. sufficient voltage swing at the mixer outputs. The value of
R3 depends on the operating frequency: 1.5 kΩ
Mixers (173 MHz), 820 Ω (470 MHz) and 330 Ω (930 MHz).
The double balanced mixers consist of common base
Low noise amplifiers, active filters and gyrator filters
input stages and upper switching stages driven from the
frequency multiplier. The 300 Ω input impedance of each The low noise amplifiers ensure that the noise of the
mixer acts together with external components (C10, C11; following stages does not affect the overall noise figure.
L4, L5 respectively) as phase shifter/power splitter to The following active filters before the gyrator filters reduce
provide a differential phase shift of 90 degrees between the levels of large signals from adjacent channels. Internal
the I channel and the Q channel. At 930 MHz all external AC couplings block DC offsets from the gyrator filter
phase shifter components are inductive (L10, L11; L4, L5). inputs.
The gyrator filters implement the transfer function of a 7th
Oscillator
order elliptic filter. Their cut-off frequencies are determined
The oscillator is based on a transistor in common collector by the 47 kΩ external resistor R2 between pins RGYR and
configuration. It is followed by a cascode stage driving a COM. The gyrator filter output signals are available on IF
tuned circuit which provides the signal for the frequency test pins TPI and TPQ.
multiplier. The oscillator transistor requires an external
bias voltage Vbias(osc) (1.22 V typ.). The oscillator bias Limiters
current (typically 250 µA) is determined by the 1.5 kΩ
The gyrator filter output signals are amplified in the limiter
external resistor R5. The oscillator frequency is controlled
amplifiers to obtain IF signals with removed amplitude
by an external 3rd overtone crystal in parallel resonance
information.
mode. External capacitors between base and emitter
(C17) and from emitter to ground (C16) make the oscillator
Demodulator
transistor appear as having a negative resistance for small
signals; this causes the oscillator to start. Inductance L9 The limiter amplifier output signals are fed to the
connected in parallel with capacitor C16 to the emitter of demodulator. The demodulator output DO is going LOW or
the oscillator transistor prevents oscillation at the HIGH depending upon which of the input signals has a
fundamental frequency of the crystal. phase lead.
1996 Jan 15 18
Battery LOW indicator Band gap reference

The battery LOW indicator senses the supply voltage and The whole chip except the oscillator section can be
sets its output HIGH when the voltage at input SENSE is powered-up and powered-down by enabling and disabling
less than Vth (typically 1.10 V). Low battery warning is the band gap reference via the receiver enable pin RE.
available at BLI.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Ground pins GND1, GND2 and GND3 connected together.
SYMBOL PARAMETER MIN. MAX. UNIT
VP supply voltage −0.3 +8.0 V
Tstg storage temperature −55 +125 °C
Tamb operating ambient temperature −10 +70 °C
Ves electrostatic handling; note 1
pins VI1RF and VI2RF −1500 +2000 V
pin RRFA −500 +2000 V
pins VO1RF and VO2RF −2000 +250 V
pins VP and OSB −500 +500 V
pins OSC and OSE −2000 +500 V
other pins −2000 +2000 V
Note
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor.
1996 Jan 15 19
DC CHARACTERISTICS
VP = 2.05 V; Tamb = −10 to +70 °C (typical values at Tamb = 25 °C); measurements taken in test circuit Figs 1, 2, 3 or 4
with crystal at pin OSB disconnected; unless otherwise specified.
Supply
VP supply voltage 1.9 2.05 3.5 V
IP supply current VRE = HIGH; 2.3 2.7 3.2 mA
fi(RF) = 173 and 470 MHz
VRE = HIGH; fi(RF) = 930 MHz 2.9 3.4 3.9 mA
IP(off) stand-by current VRE = LOW − − 3 µA
Vbias(osc) oscillator bias voltage 1.20 1.22 1.24 V
Receiver enable input (pin RE)
VIH HIGH level input voltage 1.4 − VP V
VIL LOW level input voltage 0 − 0.3 V
IIH HIGH level input current VIH = VP = 3.5 V − − 20 µA
VIL LOW level input current VIL = 0 V 0 − −1.0 µA
Battery LOW indicator output (pin BLI)
VOH HIGH level output voltage VSENSE < Vth; IBLI = −10 µA VP − 0.5 − − V
VOL LOW level output voltage VSENSE > Vth; IBLI = +10 µA − − 0.5 V
Vth voltage threshold for battery VP = 2.05 V; Tamb = 25 °C 1.05 1.10 1.15 V
LOW indicator VP = 2.05 to 3.5 V; 1.03 1.10 1.17 V
Tamb = −10 to +70 °C
Demodulator output (pin DO)
VOH HIGH level output voltage IDO = −10 µA VP − 0.5 − − V
VOL LOW level output voltage IDO = +10 µA − − 0.5 V
1996 Jan 15 20
AC CHARACTERISTICS (173 MHz)

VP = 2.05 V; Tamb = 25 °C; test circuit Figs 1 or 2; fi(RF) = 172.941 MHz with ±4.0 kHz deviation; 1200 baud pseudo
random bit sequence modulation (tr = 250 ±25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
channel spacing; unless otherwise specified.
Radio frequency input
Pi(ref) input sensitivity (Pi(ref) is the BER ≤ 3⁄100; note 1 − −126.5 −123.5 dBm
maximum available power at Tamb = −10 to +70 °C; note 2 − − −120.5 dBm
the RF input of the test board)
VP = 1.9 V − − −117.5 dBm
Mixers to demodulator
αacs adjacent channel selectivity Tamb = 25 °C 69 72 − dB
Tamb = −10 to +70 °C 67 − − dB
αci IF filter channel imbalance − − 2 dB
αc co-channel rejection − 4 7 dB
αsp spurious immunity 50 60 − dB
αim intermodulation immunity 55 60 − dB
αbl blocking immunity ∆f > ±1 MHz; note 3 78 85 − dB
foffset frequency offset range deviation f = ±4.0 kHz ±2.0 − − kHz
(3 dB degradation in sensitivity) deviation f = ±4.5 kHz ±2.5 − − kHz
∆fdev deviation range 2.5 − 7.0 kHz
(3 dB degradation in sensitivity)
ton receiver turn-on time data valid after setting RE input − − 5 ms
HIGH; note 4
Notes
1. The bit error rate BER is measured using the test facility shown in Fig.12. Note that the BER test facility contains a
digital input filter equivalent to the one used in the PCA5000A, PCF5001 and PCD5003 POCSAG decoders.
2. Capacitor C16 requires re-adjustment to compensate temperature drift.
3. ∆f is the frequency offset between the required signal and the interfering signal.
4. Turn-on time is defined as the time from pin RE going HIGH to the reception of valid data on output pin DO. Turn-on
time is measured using an external oscillator (turn-on time using the internal oscillator is dependent upon the
oscillator circuitry).
1996 Jan 15 21

VP = 2.05 V; Tamb = 25 °C; test circuit Figs 3 or 4; fi(RF) = 469.950 MHz with ±4.0 kHz deviation; 1200 baud pseudo
random bit sequence modulation (tr = 250 ± 25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
maximum available power at Tamb = −10 to +70 °C; note 2 − − −118.5 dBm
VP = 1.9 V − − −115.5 dBm
Mixer input
Pi(mix) input sensitivity BER ≤ 3⁄100; note 3 − −115.0 −110.0 dBm
Tamb = −10 to +70 °C 65 − − dB
αci IF filter channel imbalance − − 2 dB
HIGH; note 5
Notes
2. Capacitor C16 requires re-adjustment to compensate temperature drift.
3. Test circuit Fig.5. Pi(mix) is the maximum available power at the input of the test board. The bit error rate BER is
measured using the test facility shown in Fig.12.
1996 Jan 15 22

VP = 2.05 V; Tamb = 25 °C; test circuit Fig.6; note 1; fi(RF) = 930.500 MHz with ±4.0 kHz deviation; 1200 baud pseudo
random bit sequence modulation (tr = 250 ± 25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
maximum available power at VP = 1.9 V − − −108.0 dBm
HIGH; note 4
Notes
1. The external oscillator signal Vi(OSC) has a frequency of fOSC = 310.1667 MHz and a level of −15 dBm.
1996 Jan 15 23
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator: fgen = fi(RF) + 4 kHz, no modulation, Vi(RF) = 1 mV (RMS).
2. Measure the IF with a counter connected to test pin TPI. Tune C16 to set the crystal oscillator to achieve fIF = 4 kHz
Change the generator frequency to fgen = fi(RF) − 4 kHz and check that fIF is also 4 kHz. For a received input
frequency fi(RF) = 172.941 MHz the crystal frequency is fXTAL = 57.647 MHz, while for fi(RF) = 469.950 MHz the
crystal frequency is fXTAL = 78.325 MHz. For a received input frequency fi(RF) = 930.500 MHz an external oscillator
signal must be used with fi(OSC) = 310.1667 MHz and a level of −15 dBm (for definition of crystal frequency, see
Table 1).
3. Set the signal generator to nominal frequency (fi(RF)) and turn on the modulation deviation ±4.0 kHz, 600 Hz square
wave modulation, Vi(RF) = 1 mV (RMS). Note that the RF signal should be reduced in the following tests, as the
receiver is tuned, to ensure Vo(IF) = 10 to 50 mV (p-p) on test pins TPI or TPQ.
4. Tune C15 (oscillator output circuit) and C12 (frequency multiplier output) to obtain a peak audio voltage on pin TPI.
5. Tune C3 and C6 (RF input and mixer input) to obtain a peak audio voltage on pin TPI. When testing the mixer input
sensitivity tune C23 instead of C3 and C6 (test circuit Fig.5).
6. Check that the output signal on pin TPQ is within 3 dB in amplitude and at 90° (±20°) relative phase of the signal on
pin TPI.
7. Check that data signal appears on output pin DO and proceed with the AC test.
AC test conditions
Table 5 Definitions for AC test conditions (see Table 6)
SIGNAL DESCRIPTION
Modulated test signal 1
Frequency 172.941, 469.950 or 930.500 MHz
Deviation ±4.0 kHz
Modulation 1200 baud pseudo random bit sequence
Rise time 250 ±25 µs (between 10% and 90% of final value)
Modulated test signal 2
Deviation ±2.4 kHz
Modulation 400 Hz sine wave
Other definitions
f1 frequency of signal generator 1
∆fcs channel spacing (20 kHz)
P1 maximum available power from signal generator 1 at the test board input
Pi(ref) maximum available power at the test board input to give a Bit Error Rate (BER) ≤ 3⁄100 for the modulated
test signal 1, in the absence of interfering signals and under the conditions as specified in Chapters
“AC characteristics (173 MHz)”, “AC characteristics (470 MHz)” and “AC characteristics (930 MHz)”
1996 Jan 15 24
Table 6 AC test conditions; notes 1 and 2

SYMBOL PARAMETER CONDITIONS TEST SIGNALS
αa adjacent channel selectivity; f2 = f1 ± ∆fCS
Fig.11(b) generator 1: modulated test signal 1 P1 = Pi(ref) + 3 dB
generator 2: modulated test signal 2 P2 = P1 + αa(min)
αc co-channel rejection; Fig.11(b) f2 = f1 ± up to 3 kHz
generator 1: modulated test signal 1 P1 = Pi(ref) + 3 dB
generator 2: modulated test signal 2 P2 = P1 − αc(max)
αsp spurious immunity; Fig.11(b) f2 = 100 kHz to 2 GHz
generator 2: modulated test signal 2 P2 = P1 + αsp( min)
αim intermodulation immunity; f2 = f1 ± ∆fcs; f3 = f1 ± 2∆fcs
Fig.11(c) generator 1: modulated test signal 1 P1 = Pi(ref) + 3 dB
generator 2: unmodulated P2 = P1 + αim(min)
generator 3: modulated test signal 2 P3 = P2
αbl blocking immunity; Fig.11(b) f2 = f1 ± 1 MHz
generator 2: modulated test signal 2 P2 = P1 + αbl(min)
foffset frequency offset range; deviation = ±4.0 kHz, f1 = fi(RF) ± 2 kHz (foffset(min))
Fig.11(a) generator 1: modulated test signal 1 P1 = Pi(ref) + 3 dB
∆fdev deviation range; Fig.11(a) deviation = ±2.5 to ±7 kHz; (∆fdev(min) to ∆fdev(max))
ton receiver turn-on time; Fig.11(a) note 3
Notes
1. The tests are executed without load on pins TPI and TPQ.
2. All minimum and maximum values correspond to a bit error rate (BER) ≤ 3⁄100 in the wanted signal (P1).
3. The BER measurement is started 5 ms (ton(max)) after VRE goes HIGH; BER is then measured for 100 bits
(BER ≤ 3⁄100).
1996 Jan 15 25

GENERATOR 1 DEVICE BER TEST(1)
(a)
R s = 50 Ω UNDER TEST FACILITY
50 Ω 2-SIGNAL
(b) POWER
R s = 50 Ω COMBINER
UNDER TEST FACILITY
GENERATOR 2
R s = 50 Ω
GENERATOR 1
R s = 50 Ω
50 Ω 3-SIGNAL
(c) POWER
R s = 50 Ω COMBINER
UNDER TEST FACILITY
MLC232
GENERATOR 3
R s = 50 Ω
(a) One generator.

(b) Two generators.
(c) Three generators.
(1) See Fig.12.
Fig.11 Test configurations.

recovered clock
GENERATOR DEVICE DIGITAL CLOCK
R s = 50 Ω UNDER TEST FILTER RECOVERY retimed
Rx data
PRESET DATA to error

DELAY COMPARATOR counter
PSEUDO
250 µs RANDOM MASTER
RISE TIME SEQUENCE CLOCK
GENERATOR
MLC233
Fig.12 BER test facility.
1996 Jan 15 26
PRINTED-CIRCUIT BOARDS
MBD562
Fig.13 PCB top view for LQFP32; test circuit Figs 1 and 3.
1996 Jan 15 27
MBD561
Fig.14 PCB bottom view for LQFP32; test circuit Figs 1 and 3.
1996 Jan 15 28
C19
R3
L7 L6
L5
V bosc R2
C14 L4 C9
C12 C7
C11
C20 C15 C8
VP UAA2082H C10
L8
R6 L3
Vsense
C13 C6
C4
C16 C17
L2
GND XTAL
L9 R1
R5
C18
TS
BLI
VIRF
DO DO TPI TPQ
RE
MLC234
VEE = GND; VC = VP.
Fig.15 PCB top view with components for LQFP32; test circuit Fig.3.
1996 Jan 15 29
C5
R4
C3
L1
C2 C1
MLC235
Fig.16 PCB bottom view with components for LQFP32; test circuit Fig.3.
1996 Jan 15 30
C19
R3
C23
L7 L6
L5
L10
V bosc R2
C14 L4
C10
C12
C15 C11 C21 C22
C20
VP UAA2082H
L8
R6 Vsense
C13
C16 V i RF
C17
GND XTAL
L9
R5
C18
TS
BLI
DO DO TPI TPQ
RE
MLC236
1996 Jan 15 31
C5
R4
MLC237
1996 Jan 15 32
book, full pagewidth
GND C13
VP
L5 L4 C9
L11
R2
R3 C12
L10
L6
UAA2082H
C7
C19 L7 L3 C4
C8
L8
L2
C14
C6
Vi(OSC) R1
C15
TS
L1
BLI
DO C3
RE
TPI C1 C2
TPQ
MLC238
V i(RF)
1996 Jan 15 33
C5
R4
MLC239
1996 Jan 15 34
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1
c
y
X
24 17 A
25 16 ZE
e
Q
E HE
A A2 A (A 3)
1
wM
θ
bp Lp
pin 1 index L
32 9
detail X
1 8
e ZD v M A
wM
bp
D B
HD v M B
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y Z D (1) Z E (1) θ
o
0.20 1.45 0.4 0.18 7.1 7.1 9.15 9.15 0.75 0.69 0.9 0.9 7
mm 1.60 0.25 0.8 1.0 0.2 0.25 0.1
0.05 1.35 0.3 0.12 6.9 6.9 8.85 8.85 0.45 0.59 0.5 0.5 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
93-06-29
SOT358 -1
95-12-19
1996 Jan 15 35
SOLDERING If wave soldering cannot be avoided, the following

conditions must be observed:
Introduction
• A double-wave (a turbulent wave with high upward
There is no soldering method that is ideal for all IC pressure followed by a smooth laminar wave)
packages. Wave soldering is often preferred when soldering technique should be used.
through-hole and surface mounted components are mixed
• The footprint must be at an angle of 45° to the board
on one printed-circuit board. However, wave soldering is
direction and must incorporate solder thieves
not always suitable for surface mounted ICs, or for
downstream and at the side corners.
printed-circuits with high population densities. In these
situations reflow soldering is often used. Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
This text gives a very brief insight to a complex technology.
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
Reflow soldering applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
Reflow soldering techniques are suitable for all LQFP
adhesive is cured.
packages.
Maximum permissible solder temperature is 260 °C, and
Reflow soldering requires solder paste (a suspension of
maximum duration of package immersion in solder is
fine solder particles, flux and binding agent) to be applied
10 seconds, if cooled to less than 150 °C within
to the printed-circuit board by screen printing, stencilling or
6 seconds. Typical dwell time is 4 seconds at 250 °C.
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
Several techniques exist for reflowing; for example,
of corrosive residues in most applications.
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
Repairing soldered joints
method. Typical reflow temperatures range from
215 to 250 °C. Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
Preheating is necessary to dry the paste and evaporate
(less than 24 V) applied to the flat part of the lead. Contact
the binding agent. Preheating duration: 45 minutes at
time must be limited to 10 seconds at up to 300 °C. When
45 °C.
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
Wave soldering
270 and 320 °C.
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Jan 15 36
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jan 15 37
NOTES
1996 Jan 15 38
NOTES
1996 Jan 15 39
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474
Tel. (02)805 4455, Fax. (02)805 4466 Portugal: PHILIPS PORTUGUESA, S.A.,
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Tel. (01)60 101-1236, Fax. (01)60 101-1211 Apartado 300, 2795 LINDA-A-VELHA,
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366
Tel. (31)40-2783749, Fax. (31)40-2788399 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Brazil: Rua do Rocio 220 - 5th floor, Suite 51, Tel. (65)350 2000, Fax. (65)251 6500
CEP: 04552-903-SÃO PAULO-SP, Brazil, South Africa: S.A. PHILIPS Pty Ltd.,
P.O. Box 7383 (01064-970), 195-215 Main Road Martindale, 2092 JOHANNESBURG,
Tel. (011)821-2333, Fax. (011)829-1849 P.O. Box 7430, Johannesburg 2000,
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (011)470-5911, Fax. (011)470-5494
Tel. (800) 234-7381, Fax. (708) 296-8556 Spain: Balmes 22, 08007 BARCELONA,
Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (03)301 6312, Fax. (03)301 42 43
Tel. (02)773 816, Fax. (02)777 6730 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
China/Hong Kong: 501 Hong Kong Industrial Technology Centre, Tel. (0)8-632 2000, Fax. (0)8-632 2745
72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (852)2319 7888, Fax. (852)2319 7700 Tel. (01)488 2211, Fax. (01)481 77 30
Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
Fax. (571)217 4549 TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444
Denmark: Prags Boulevard 80, PB 1919, DK-2300 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 209/2 Sanpavuth-Bangna Road Prakanong,
Finland: Sinikalliontie 3, FIN-02630 ESPOO, Bangkok 10260, THAILAND,
Tel. (358)0-615 800, Fax. (358)0-61580 920 Tel. (66) 2 745-4090, Fax. (66) 2 398-0793
France: 4 Rue du Port-aux-Vins, BP317, Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
92156 SURESNES Cedex, Tel. (0 212)279 27 70, Fax. (0212)282 67 07
Tel. (01)4099 6161, Fax. (01)4099 6427 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165,
Germany: P.O. Box 10 51 40, 20035 HAMBURG, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991
Tel. (040)23 53 60, Fax. (040)23 53 63 00 United Kingdom: Philips Semiconductors LTD.,
Greece: No. 15, 25th March Street, GR 17778 TAVROS, 276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Tel. (0181)730-5000, Fax. (0181)754-8421
India: Philips INDIA Ltd, Shivsagar Estate, A Block, United States: 811 East Arques Avenue, SUNNYVALE,
Dr. Annie Besant Rd. Worli, Bombay 400 018 CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556
Tel. (022)4938 541, Fax. (022)4938 722 Uruguay: Coronel Mora 433, MONTEVIDEO,
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, Tel. (02)70-4044, Fax. (02)92 0601
P.O. Box 4252, JAKARTA 12950,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)7640 000, Fax. (01)7640 200
Italy: PHILIPS SEMICONDUCTORS S.r.l., Internet: http://www.semiconductors.philips.com/ps/
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 For all other countries apply to: Philips Semiconductors,
Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, International Marketing and Sales, Building BE-p,
Tel. (03)3740 5130, Fax. (03)3740 5077 P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825
Korea: Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 SCDS47 © Philips Electronics N.V. 1996
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
All rights are reserved. Reproduction in whole or in part is prohibited without the
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 prior written consent of the copyright owner.
Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,
Tel. 9-5(800)234-7381, Fax. (708)296-8556 The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, notice. No liability will be accepted by the publisher for any consequence of its
Tel. (040)2783749, Fax. (040)2788399 use. Publication thereof does not convey nor imply any license under patent- or
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, other industrial or intellectual property rights.
Tel. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546 Printed in The Netherlands

Data Sheet: Advanced Pager Receiver

Uploaded by

Copyright:

Available Formats

Data Sheet: Advanced Pager Receiver

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Data Sheet: Advanced Pager Receiver

Uploaded by

Copyright:

Available Formats

INTEGRATED CIRCUITS

Advanced pager receiver UAA2082

FEATURES GENERAL DESCRIPTION

APPLICATIONS The UAA2082 was designed to operate together with the

Advanced pager receiver UAA2082

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

data rate 1200 bits/s; Tamb = 25 °C

BAND GAP CRYSTAL FREQUENCY

REFERENCE OSCILLATOR MULTIPLIER

TPI TPQ C3 10 pF 10 pF L4 GND2

handbook, full pagewidth

Advanced pager receiver UAA2082

Table 1 Tolerances of components shown in Figs 1 and 2 (notes 1 and 2)

INDICATOR low noise 47

BAND GAP CRYSTAL FREQUENCY

TPI TPQ C3 22 pF 22 pF L4 GND2

Fig.5 Mixer input sensitivity test circuit; fi(RF) = 469.95 MHz.

Advanced pager receiver UAA2082

Table 2 Tolerances of components shown in Figs 3, 4 and 5 (notes 1 and 2)

Pins 9, 17, 23 and 29 are not connected.

Fig.6 Test circuit; fi(RF) = 930.50 MHz.

Advanced pager receiver UAA2082

Table 3 Tolerances of components shown in Fig.6 (note 1)

Advanced pager receiver UAA2082

SYMBOL PIN DESCRIPTION

GND1 11 ground 1 (0 V) VI1RF 7 18 VI1MQ

VO2RF 12 pre-amplifier RF output 2 VI2RF 8 17 n.c.

VO1RF 13 pre-amplifier RF output 1

VP 14 supply voltage MLC228

Advanced pager receiver UAA2082

CHIP DIMENSIONS AND BONDING PAD LOCATIONS

Chip area: 18.15 mm2

Fig.8 Bonding pad locations.

Advanced pager receiver UAA2082

Table 4 Bonding pad centre locations (dimensions in µm)

Advanced pager receiver UAA2082

handbook, full pagewidth 32 31 30 29 28 27 26 25

Fig.9 Internal circuits drawn for LQFP32.

handbook, full pagewidth

Fig.10 Internal circuits drawn for naked die.

Advanced pager receiver UAA2082

Advanced pager receiver UAA2082

Battery LOW indicator Band gap reference

Advanced pager receiver UAA2082

Advanced pager receiver UAA2082

AC CHARACTERISTICS (173 MHz)

Advanced pager receiver UAA2082

AC CHARACTERISTICS (470 MHz)

Advanced pager receiver UAA2082

AC CHARACTERISTICS (930 MHz)

Advanced pager receiver UAA2082

Advanced pager receiver UAA2082

Table 6 AC test conditions; notes 1 and 2

Advanced pager receiver UAA2082

handbook, full pagewidth

(a) One generator.

Fig.11 Test configurations.

handbook, full pagewidth