TESTABILITY FOR VLSI – ASSIGNMENT 2

Name: DWARAKANATH MADIHALLI NARASIMHAN

Submission Date: 17th November 2018.

Topic: Memory Repair

Introduction: Memory Technology:

With the advancements in the VLSI IC fabrication technology, the increase in the number of transistors on
a chip has been exponential since more than four to five decades. This exponential trend seems to keep
its pace due to ever more increasing efforts to keep up with technological exploration and innovation. It
has been noted that the memory density (bits/chip) quadruples roughly every 3.1 years (from Bushnell
and Agrawal, pp255.). With this rate of increase, consequently the cost of memory is also reducing at a
rapid pace. This in general helps the vast number of memory-intensive operations/algorithms that can be
developed for various applications – like in the field of high-speed graphics, big-data analytics, weather
forecasting and so on. In large part, most of this is due to the advancements in the Dynamic-Random
Access Memory technology (DRAM) – due to the highly dense memory that can be realized in contrast to
the Static RAM technology.

Fig1: Schematic Representation of 1-transistor DRAM Bit Cell

Fig2: Schematic Representation of 3-transistor DRAM Bit Cell (with read/write controls)
The above figures show the schematic representation of the single bit cell used in dynamic memories. As
can be seen, the memory element is based on the charge stored on the capacitor. Due to non-ideal (leaky)
MOS structures, such dynamic elements retain their charge for a finite duration of time. Frequent
measuring and re-charging is carried out – called memory refresh – to retain the data for longer periods.

We look at the simple extension of multi-bit memories with bit cells arranged as rows and columns as
depicted below in fig3.

Fig3: Schematic representation of DRAM memory bank with row/column addressing

In contrast, a static-RAM cell needs at least 6-transistors for storing a single-bit. Thus we see that dynamic
RAM’s have very huge densities.

Defects in Memory Circuits:

As the trends keep going with requirement for larger memories, it is common to see the importance of
faster testability of memories. For the exponential increase in the memory density, if the testing
methodology too takes up more time for modelling and detection of faults – then it is highly undesirable.
Various faults include the individual bit-cell faults, the cell coupling fault and the linked cell coupling fault.
The individual bit-cell fault is due to the exponentially reduced charge on the storage capacitor. The
coupling fault is between adjacent cells that interact unintentionally. The linked cell coupling fault is where
a fault at a particular cell influences many other cells that are linked. We can also classify the faults as : 1.
Stuck-at-Fault (SAF), 2. Transition Fault (TF), 3. Coupling Fault (CF), 4. Neighbourhood pattern sensitive
fault (NPSF).
We can also observe that there can be defects in the addressing lines – called the addressing faults (AF) –
which leads to defects in the memory usage. The causes of defects are the usually the various
shortcomings in the fabrication process.

Need for MBIST:

We do not elaborate further the details of the above faults and their detection procedures. It is sufficient
to note that given the very high dense nature of the memories, and the non-idealities of any fabrication
process technology – it is imminent that there would certainly be some manufacturing defect in the
memory IC. This means, nearly any memory fabricated does have some defects – leading to 0% yield.
Hence, in order to overcome these defects the only way is to introduce reasonable amount of redundancy
(with extra rows and columns of bit cells, addressing lines and associated mux logic) and effective ways of
applying the memory-defect detection and memory-repair. Due to very huge density of memory bit cells,
we employ a separate unit, which identifies the defects automatically. This unit is called the Memory Built-
In Self-Test (MBIST). All required logic for initiation of test pattern generation, application of the test
vectors, comparing the response to the expected patterns (signature) and then identifying the defects is
what constitutes the MBIST. Sufficient care is taken in optimization such that the cost incurred in
introducing the MBIST remains well within the cost of the memory/overall system.

Fig4: Block representation of an MBIST unit

Need for Memory Repair:

As we discussed above, it is a certainty that any memory fabrication does have some defects. The only
way to ensure the working of the memory is to introduce sufficient memory redundancy. Once the MBIST
detects the defective memory cells, we need an effective mechanism to isolate the defective cells and re-
route the memory-cells from redundant bank via the programmable “fuse” registers. This procedure is
called the Memory Repair. Since the complexity if the memory is too large, new methodologies have been
evolved wherein after self-test, the self-repair is also carried out by what is called the Memory Built-In
Self-Repair (MBISR). It is sufficient to ensure that the MBISR unit is programmed appropriately to know
the complete memory elements, the test patterns, the outputs to be observed, the redundant memory
provisioned, and the fuse-registers for making the corrective next steps. The MBISR will automatically
perform the required memory repair to finally yield in working reliable memories.

We elaborate upon a few key concepts and also explore the supporting mechanisms as provided by the
tool Tessent by Mentor-Graphics ®.

The Fuse cell:

A simple electrically controlled switch is initially open during fabrication. By the application of the fuse-
voltage (usually slightly higher than the operating voltage) one can cause the fuse to be permanently short
or open. A bank of fuse-switches is used so as to create redundant routing resources. The MBISR is made
aware of the details of the availability of these fuses so as to enable the appropriate corrective measures
to be initiated.

Built-In Self-Repair for memory:

The Tessent tools support both serial as well as parallel interfaces for BISR. Appropriate constructs are
provided for realization at the top level. Below is a block representation of the possible BISR interfaces.

Fig5: Serial and Parallel BISR interfaces

Redundant Column, Redundant IO and Redundant Rows:

The amount of redundancy to be made available is determined based on the maturity of the fabrication
process, the yield improvement that the memory designers want to target, and the overall cost overhead
due to the extra resources (routing, fuses, control logic, redundant memory cells). The simplest
implementation is the insertion of a redundant memory column as shown below in Fig6. The extra column
is in blue. If a particular column has any defect then the fuses are used to disconnect the defective column
and make use of the redundant column for memory repair.

Fig6: Memory with Redundant Column

The next possible implementation is the insertion of redundant IO – which is a collection of columns. This
calls for more redundancy and at the same time provides for addressing greater amount of defects. The
block representation is as shown below in Fig7.

Fig7: Memory with Redundant IO

Also, one can make the implementation of inserting redundant rows (also called spares) so as to overcome
defects, as shown in the below Fig8.

Fig8: Memory bank with Redundant rows

Incremental Memory Repair:

With any of the architectures of redundant memory available, the target of the self-repair logic would be
to remove all possible defects from the memory by effectively replacing them with the working cells. The
below Fig9 shows the working flow of the incremental repair algorithm. According to the Tessent tool, the
TP1, TP2 and TP3 – form the Pre-repair test patterns, Repair test patterns and the Post-repair test
patterns. The goal of this procedure would be to end with a “good device” and a working memory. In an
inevitable case where even the incremental repair ends up in a bad device, it leads to reduced memory
yields.

Fig9: Steps followed by Tessent for Incremental Memory-Repair

Conclusion:

We explored the growth of memory usage and the related defects during fabrication. We understood the
need of effective ways of automated testing for the exponentially growing memory density. It is inevitable
that any memory fabricated will have certain amount of defects due to challenges in advanced-node
fabrication process – effectively leading us to 0% memory yield. The way out for this problem lies in
reserving some area on the chip for redundant memory to replace the defective cells in the main memory.
Given the challenges in detection and repair, due to high density, we explored ways of automatically
testing (MBIST) and repairing (MBISR) methods commonly employed in the industry.

References:

[1] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,

Memory & Mixed-Signal VLSI Circuits. Boston: Kluwer Academic Publishers,
2000.
[2] Tessent MemoryBIST User's Manual, For Use with Tessent® Shell, Software Version 2018.3, August
2018