Lecture-13

Internal Architecture of Intel 8085A

The functional block diagram of 8085A is shown in fig.4.1.

RST7.5 RST5.5
INTA
INTR RST6.5 TRAP
SOD SID

INTERRUPT
SERIAL I/O
(Internal Bus) 8 8

8 8
8 8 8
8 8
B(8) C(8)
FR(S) IR(8)
D(8) E(8)
A(S) TR(S)

8 H(8) L(8)
INTERRUPTION
8
8 DECODER&
M/C ENCODER PC(16)

ALU
SP(16)
8
8
W(8) Z(8)
OUTPUT SIGNALS

INR/DCR ADDR LATCH(16)

CONTROL SIGNALS

16 (AB)

8
8
D7-D0
A15-A8 A7-A0
8 8
Timing and control 8

Unit
ADDER BUFFER ADDERR/DATA BUFFER
X1
CLK STATUS CONTROL
CKT
X2 SIGNALS
8
8
A15-A8 AD7-AD0
HLDA RESET IN
CLK (OUT) S1 ALE WR

S0 RD READY HOLD RESET (OUT)

IO/M

Fig.4.1 Internal Architecture of 8085A Microprocessor

It consists of five essential blocks.

(1) Arithmetic Logic Section
(2) Register Section
(3) The Interrupt Control Section
(4) Serial I/O Section
(5) The Timing And Control Unit
There is an internal bi-directional data bus of 8-bit wide. This bus is
used to transfer data and instructions among various internal
registers. All the internal registers which transfer data to the internal
bus are tri-state registers. Higher order address bus (A15-A8) and
time-multiplexed lower order address data bus (AD7-AD0) are the
external buses and used to interface peripherals and memory chips
to CPU. Address buffer and address/data buffers isolate the internal
data bus from the external address bus and address/data bus and
drive the external address bus and address/data bus. The CPU can
send the address of desired memory locations and I/O chip through
these buffers. The 8-bit internal data bus is also connected to the
address/data buffers. The bi-directional arrows indicate a tri-state
connection that allows the address/data buffer to send or receive data
from the 8-bit internal data bus. In the output mode the information on
the data bus is loaded into the 8-bit data latch that drives the
address/data bus output buffer. The output buffers are floated during
input or non transfer operations. During the input mode, data from the
external bus is transferred over the internal data bus to internal
register.

The figure shown does not include the control signals driving
internal registers.

Arithmetic & Logic Section: This section consists of:

(a) Accumulator (A)
(b) Temporary Register (TR)
(c) Flag Register (FR)
(d) Arithmetic Logic Unit (ALU)
Accumulator:
Arithmetic and/or logic operations on one or two operations
are the basic data transformations implemented in a µρ one of these
two operands is always in the accumulator. Accumulator is an 8-bit
register accessible to the user is connected to the 8-bit internal data
bus. The bi-directional arrow between the accumulator and the bus
indicates a tri-state connection that allows the accumulator to send or
receive data. In addition, it has a two state 8-bit output. The content
of the accumulator is always available at this two state output as one
of the operands for the ALU. The contents of the accumulator can be
manipulated through instructions. Its content can be incremented and
decremented. The content of the memory location can be transferred
to the accumulator and vice-versa. The result of arithmetic/ logical
operations carried out by ALU is also stored back in the accumulator.
In other words, it accumulates the result of the operation, hence, the
name accumulator.

Temporary registrar (TR):

This is an 8-bit register not accessible to the user. It is used by
the processor for internal operations. The second operand as and
when necessary is loaded in to this register by the microprocessor
before the desisted operation takes placed in the ALU. The temporary
register has 8-btis two state output. The second operand is always
available at this output.
Arithmetic Logical Unit (ALU):
ALU is a combination logic block which performs the desired
operation on the two operands. The contents of the accumulator and
the temporary register are the inputs to the ALU. This is governed by
the control signals generated by the timing and control unit. The
various arithmetic and logical operations that can be performed by
ALU are:
 Binary addition, subtraction, increment and decrement,
 Logical AND, OR and EX-OR,
 Complement,
 Rotate left of right.

The result of the operation is, in general, stored back in accumulator.

In subtraction operation, the content of the temporary register is
subtracted from the content of the accumulator and is stored back in
the accumulator.
In many applications it is appropriate to represent data in binary
coded decimal (BCD) form. The result on any operation on BCD
should also be in BCD form. The ALU contains additional logic to
adjust result of addition operations where the operands are
interpreted as BCD data.

Flags register:
The ALU influences a number of flip flops called flags which
store information related to the results of arithmetic and logical
operations. Taken together this flags constitute a flag register.
 Flag register is an 8-bit register accessible to the user through
instruction. Each bit in the flag register has a specific function. Only 5
bits out of 8 bits are used as shown below:
D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

The three crossed bit are redundant bits and not used. They
can be either ‘0’ or ‘1’ but normally they are forced to be zero. The
other five bits are affected as a result of execution of an instruction.
All instructions do not affect these flags e.g. data transfer operation
do not affect these flags. The meaning and the effect of these flags
are as follows.

CY (Carry) Flag bit:

This particular bit is SET (=1) if there is a carry from the MSB
position during an addition operation or if there is a borrow during the
subtraction operation otherwise the flag is reset (=0). The processor,
by design, does the subtraction operation also by taking 2’s
complement of one operand and adding it to another operand.

P (Parity) Flag bit:

The parity flag test for the number of ‘1’s in the accumulator. If
the accumulator holds on an even number of 1’s, it is said that even
parity exists and the parity flag is set to ‘1’. However, if the
accumulator holds an odd number of ‘1’ it is called odd parity and the
parity flag is reset to ‘0’. In other words, if the module-2 sum of the bit
is ‘0’, this flag is set otherwise the flag is reset.
AC (Auxiliary Carry) Flag bit:
This bit is set if there is a carry from b3 bit to b4 bit of
accumulator during addition operation otherwise it is reset. The AC
flag is useful for BCD arithmetic and is used in a particular instruction
known as DAA (Decimal Adjust Accumulator).

Z (Zero) Flag bit:

Zero flag bit is SET if the result of an operation is zero,
otherwise it is RESET.

Sign Flag bit:

The sign flag is set to the condition of the most significant bit of
the accumulator following the execution of arithmetic or logical
operation. These instructions use the MSB of the data (result) to
represent the sign of the number contained in the accumulator. A set
sign flag represents a negative number, where as a reset flag means
a positive number.

Example 1:
Let us consider the execution of the instruction ADD B.
ADD is the mnemonic for addition. The first operand is known to exist
in the accumulator (Reg. A). Register B contains the second operand.
The meaning of the instruction is add the contents of the B register to
the contents of A register and store the result back in the accumulator
(A). Symbolically we can write,
(A) (A) + (B)
 Let as suppose the register contents are (A) = 9BH, (B) = A5H
before the execution of the instruction. It means,
(A) = 9BH → (1001 1011)2
(B) = A5H → (1010 0101)2
ADD B = (A+B) → (0100 0000)2
As a result of addition, there is a carry from b3 to b4 position and
therefore AC is set. Also there is a carry from the MSB out and,
therefore, CY flag is also set. Soon after the execution of ADD B
instruction the accumulator contains (A) = (0100 0000)2 = 40H and is
non-zero. Therefore Z flag is reset to zero. Also, result contains only
one ‘1’, an odd number. Therefore, parity bit is also be reset to zero.
Since the MSB of the result is zero, therefore the sign (S) bit is also
reset. Thus the flag register, soon after the execution of the
instruction, contains (0001 0001)2 = 11H.

Example 2:
Let us consider the execution of another instruction SUB B.
SUB is the mnemonic for subtraction. Accumulator consists of first
operand. Register B contains the second operand. The meaning of
the instruction is subtract the contents of the B register from the
contents of A register and store the result back in the accumulator
(A). Symbolically we can write,
(A) (A) - (B)
Let as suppose the register contents are (A) = A5H, (B) = 9BH
before the execution of the instruction. It means,
Before execution A = A5H and B = 9BH
(A) = 1010 0101 → (1010 0101)2
(B) = 1001 1011 2’s complement → (0110 0101)2
Carry 1 (0000 1010)2
Since result is non zero, therefore, Z bit is ‘0’. Sign bit is also ‘0’
because MSB of the result is ‘0’. AC is also ‘0’ because in addition
(2’s complement), there is no carry from b3 to b4. Parity bit is ‘1’ (2
ones). CY bit seems to be ‘1’. But it is complemented and then
stored. Therefore, CY bit is stored as ‘0’. It also indicates that (A) is
having larger number than register (B), otherwise smaller one. Thus
the flag register, after the execution of the instruction, contains (0000
0100)2 = 04H.
Let us consider (A) is having 9B H and (B) is A5 H before execution.
(A) = 1001 1011 → (1001 1011)2
(B) = 1010 0101 2’s complement → (0101 1011)2
Carry 0 (1110 0110)2
Therefore, in this case, the flag bits will be S=1, Z=0, AC=1, P=1,
CY=1 (complement of ‘1’ obtained in addition). Thus the flag register,
after the execution of the instruction, contains (1001 0101)2 = 95H.

Let use consider execution of another instruction DCR C. DCR is the

mnemonic for decrement register. C register is the operand. This
instruction means decrement the content of the C register by ‘1’ and
store it back in the C register. The MACRO RTL implemented is
C)← C - 1
Let us suppose (C) contains D2H before the execution of the
instruction. After the execution of instruction, (C) shall contains D1H
and, therefore, is not zero. Therefore the flag register will contain
(1000 0100)2 or 84H. On the other hand, if (C) contains 01H just
before the execution of the instruction DCR C. Just after the
execution of the instruction, (C) shall contain 00H. Since the result of
the operation is ‘0’ the zero flag shall now be SET to ‘1’. Other flag
will be affected in the normal way.

These flag bit are utilized in many instructions for branching

operations. During the execution of a program normally one of these
bits are tested for TRUE & FALSE condition. Depending upon the
condition the program branches to different paths. This is shown in
fig.4.2

Fig.4.2 Branching Operation Depending on Condition