Advanced Microprocessors

By,
Dr. Vimal Shrivastava
Assistant Professor
School of Electronics Engg.
KIIT Bhubaneswar
 Books for 8086
• Microprocessors & Interfacing: Programming & Hardware
– By Douglas V. Hall.

• Microprocessors: Theory and Applications

– By Rafiquzzaman.

• Advanced Microprocessors and Peripherals

– by K. M. Bhurchandi and A. K. Ray.
 Introduction
• 8086 Microprocessor is an enhanced version of 8085 Microprocessor that
was designed by Intel in 1978.

Features of 8086:
• It is a first 16 bit µp.

• It has 16-bit ALU.

• It has 16-bit registers.

• It has 16 data lines.

• 8086 has a 20 address lines and can access up to 𝟐𝟐𝟎 memory locations (1
MB).

• It can support up to 64K I/O ports.

• Provides segmented memory addressing capability.

 Features of 8086 (cont..)
• It has an instruction queue which is capable of storing six
instruction bytes from the memory resulting in faster processing.

• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves the performance.

• It has 256 vectored interrupts.

• It consists of powerful instruction set, which provides operations

like multiplication and division easily.

• It supports two modes of operation, i.e. Maximum mode and

Minimum mode. Maximum mode is suitable for system having
multiple processors and Minimum mode is suitable for system
having a single processor.

• It consists of 29,000 transistors.

 Comparison between 8085 & 8086 Microprocessor
• Size: 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

• Address Bus: 8085 has 16-bit address bus while 8086 has 20-bit address
bus.

• Memory: 8085 can access up to 64Kb, whereas 8086 can access up to 1

Mb of memory.

• Instruction Queue: 8085 doesn’t have an instruction queue, whereas 8086

has an instruction queue.

• Pipelining: 8085 doesn’t support a pipelined architecture while 8086

supports a pipelined architecture.

• I/O: 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 =
65,536 I/O's.
Architecture of 8086
 Architecture of 8086 (cont..)
• 8086 Microprocessor is internally divided into two functional
units:
– BIU (Bus Interface Unit)
– EU (Execution Unit)

BIU (Bus Interface Unit):

• The BIU performs all bus operations such as:
– Physical address calculation of memory,
– Fetching instructions,
– Reading data from memory and I/O ports,
– Writing data to memory and I/ O ports.
– It interfaces the 8086 to the outside world.
BIU (cont..):
• The BIU provides all external bus operations.
• It contains segment registers, instruction queue and address
generation unit.

Instruction Queue:
– It is First-In First-Out (FIFO) group of registers.
– BIU gets up to 6 bytes of next instructions and stores them in
the instruction queue.
– When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this
instruction queue resulting in increased execution speed.
– Fetching the next instruction while the current instruction
executes is called pipelining.
– If the instructions such as Jump or subroutine call is
encountered, BIU will reset the queue and begin refilling after
passing the new instruction to the EU.
 BIU (cont..)
• Segment registers:
• BIU has four 16-bit segment registers, i.e. CS, DS, SS & ES.
• The 8086 1 MB memory is divided into segments of up to 64KB
each.
• The 8086 can directly address four segments (256KB within the 1
MB memory) at a particular time.

• CS: It stands for Code Segment. It is used for addressing a memory

location in the code segment of the memory, where the executable
program is stored.

• DS: It stands for Data Segment. It consists of data used by the

program and is accessed in the data segment by an offset address or
the content of other register that holds the offset address.
• SS: It stands for Stack Segment. It handles memory to store data
and addresses during execution.

• ES: It stands for Extra Segment. ES is additional data segment,

which is used by the string to hold the extra destination data.

• IP (Instruction pointer): It is a 16-bit register used to hold the

address of the next instruction to be executed.

Adder:
• The BIU contains a dedicated adder which is used to produce 20-bit
address.
• The BIU computes 20-bit physical address internally using the
programmer-provided logical addresses (16-bit contents of CS and
IP) by logically shifting the contents of CS four bits to left and then
adding 16-bit contents of IP.
• Note: Go through the example on Page-172 of Rafiquzzaman.
 EU (Execution Unit)
• The EU decodes and executes instructions that have already been fetched
by the BIU.

• EU has no direct connection with system buses, it performs operations over

data through BIU.

• The EU has a 16-bit ALU.

• It handles all arithmetic operations like addition, subtraction,

multiplication, division and logical operations like OR, AND, NOT
operations.

• It has eight 16-bit registers. These are AX, BX, CX, DX, SP, BP, SI and DI.

• The 16-bit registers AX, BX, CX and DX can be used as two 8-bit registers
(AH, AL; BH, BL; CH, CL; DH, DL).

• The general-purpose registers AX, BX, CX and DX are named after special
functions carried out by each one of them.
Ex:
1. AX
– The AX is called the 16-bit accumulator while the AL is the 8-bit
accumulator.
– The use of accumulator register is assumed by some instructions.
– The IN/OUT instructions always use AX or AL.
– Multiplication and division instructions also use AX or AL.
– The AL register is same as 8085 ‘A’ register.

2. BX
– BX register is called base register.
– This is the only general-purpose register , the contents of which can be
used for addressing 8086 memory.
– All memory references utilizing these register contents for addressing
use DS as the default segment register.
– It is similar to 8085 HL registers.
3. CX
– CX register is known as the counter register.
– Some instructions such as shift, rotate and loop instructions use the
contents of CX as a counter.

4. DX
– DX is called data register.
– It is used to hold the results of multiplication and division.

Stack Pointer (SP) and Base Pointer (BP):

• SP and BP are used to access data in the stack segment.

• SP is used as an offset from the current SS during execution of instructions that

involve the stack segment in the external memory.

• SP contents are automatically updated (incremented/decremented) due to

execution of a POP or PUSH instruction.

• BP contains an offset address in the current SS, which is used by instructions

utilizing the based addressing mode.
Source Index (SI) and Destination Index (DI):
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI registers

together with DS and ES respectively in order to distinguish
between the source and destination addresses.

• Flag Register:
– It is a 16-bit register.
– It has 9 active flags and they are divided into 2 groups:

• Six Conditional Flags (CF, AF, PF, ZF, SF, OF): It changes its
status according to the result stored in the accumulator.

• Three Control Flags (TF, IF, DF): It can be set or reset by

programmer.
 Flag Register (cont..):
Auxiliary Carry Flag
It is used by BCD operation. Carry Flag
AF=1, if there is a carry from lower nibble into
higher nibble or borrow from higher nibble into This flag is set, when there is a carry
lower nibble of the low order 8-bit of 16-bit out of MSB in case of addition or a
number. borrow in case of subtraction.

Sign Flag Zero Flag

Parity Flag
This flag is set, when the result of This flag is set, if the result of the
any computation is negative (MSB computation or comparison performed This flag is set, if the result has even parity.
of result is 1) by an instruction is zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
If this flag is set, the processor enters
Overflow Flag the single step execution mode by
This flag is set, if there is an arithmetic overflow occurs, i.e., if the size of the result generating internal interrupts after the
exceeds the capacity of destination location. execution of each instruction.
Used for debugging the program.

Interrupt Flag
Direction Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the string
is processed beginning from the lowest address to the highest address, i.e., Causes the 8086 to recognize external mask
auto incrementing mode. Otherwise, the string is processed from the highest interrupts; clearing IF disables these
address towards the lowest address, i.e., auto decrementing mode. interrupts.
15
 Summary of 8086 Registers
Sl.No. Type Register Name of register
width
1 General purpose 16 bit AX, BX, CX, DX
register
8 bit AL, AH, BL, BH, CL, CH,
DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
 Summary of 8086 Registers (cont..)
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic
operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic
operations
BX Base register Used to hold base value in base addressing mode
to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE
and LOOP instructions
DX Data Register Used to hold data for multiplication and division
operations
SP Stack Pointer Used to hold the offset address of top stack
memory
BP Base Pointer Used to hold the base value in base addressing
using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)
for string instructions
DI Data Index Used to hold the index value of destination
operand (data) for string operations
8086 Pin Diagram
• The 8086 comes in a 40 pin
package where some pins
are multiplexed.

• 8086 pins can be

categorized in three
groups:

1. Common functions in min

as well as max mode.

2. Special functions for min

mode.

3. Special functions for max

mode.
 Common Pins
• AD0-AD15 (Address/Data bus)
– These are 16 time multiplexed address/data bus.
– AD0-AD7 carries low order byte and AD8-AD15 carries higher order
byte.
– During the first clock cycle, it carries 16-bit address and after that it
carries 16-bit data.

• A16/S3, A17/S4, A18/S5, A19/S6 (Address/Status bus)

– These are the 4 time multiplexed address/status bus. S3 S4 Oper
– During the first clock cycle, it carries 4-bit address ation
and later it carries status signals. 0 0 ES
• S5 contains the value of Interrupt Flag (IF). 0 1 SS
• S6 is reserved for future purpose. Always S6=0. 1 0 CS/
Idle
1 1 DS
• BHE/S7 (Bus High Enable/Status)
– It is used to indicate the transfer of data over the higher order data bus
(D8-D15). S7 is reserved for future purpose. Always S7=0.
 Common Pins (cont..)
• RD (Read)
– The signal is used to indicate read operation (memory or I/O).

• Ready
– It is an acknowledgement signal from I/O devices that data is
transferred.
– When it is high, it indicates that the device is ready to transfer
data.
– When it is low, it indicates wait state.

• RESET
– It causes the processor to immediately terminate its current
activity.
– Restart the execution from FFFF0H.
– This signal must be active high for the first 4 clock cycles to
RESET the microprocessor.
 Common Pins (cont..)
• INTR (Interrupt Request)
– This is a level triggered input.
– It is sampled during the last clock cycle of each instruction to
determine the availability of interrupt request.

• NMI (Non-Maskable Interrupt)

– It is an edge triggered input.
– It causes an interrupt request to the microprocessor.
– It is not maskable internally by software.

• TEST
– This input is examined by a ‘WAIT’ instruction.
– If it goes low, execution will continue, else the processor
remains in an idle state.
– This is used to synchronize an external activity to the processor
internal operation.
 Common Pins (cont..)
• MN/MX (Minimum/Maximum Mode)
– It indicates what mode the processor is to operate in.
– When it is high, it works in the minimum mode (single
processor) and when it is low, it works in the maximum mode
(multiprocessor).

• CLK (Clock Input)

– It provides timing to the processor for operations and bus control
activity.
– Its frequency is different for different versions of 8086, i.e.
5MHz, 8MHz and 10MHz.

• VCC & GND (Power supply)

– It uses +5V power supply at VCC pin and uses ground at VSS
(GND) pin for its operation.
 Pins used in Minimum Mode
• M/IO (Memory/IO)
– This signal is used to distinguish between memory and I/O
operations.
– When it is high, it indicates I/O operation and when it is low
indicates the memory operation.

• INTA (Interrupt Acknowledge)

– When this signal goes low, it means that processor has accepted
the interrupt.

• ALE (Address Latch Enable)

– This output signal indicates the availability of the valid address on the
address/data lines.

• WR (Write)
– The signal is used to indicate write operation (memory or I/O).
 Pins used in Minimum Mode (cont..)
• DEN (Data Enable)
– This signal indicates the availability of valid data over the
address/data lines.
– It is used to enable transceivers (bidirectional buffers) to separate
the data from the multiplexed address/data bus.

• DT/R (Data Transmit/Receive)

– This output signal is used to decide the direction of data flow
through the transceivers (bidirectional buffers).
– When it is high, data is transmitted out from processor and a low
on this pin indicates the processor is receiving data.

• HOLD and HLDA (HOLD/HOLD Acknowledge)

– This signal indicates to the processor that external devices are
requesting to access the address/data buses.
– HLDA acknowledges the HOLD signal.
 Pins used in Maximum Mode
• S2, S1, S0 (Status Lines)
– These are the status signals that indicate the type of operation being
carried out by the processor.

• LOCK
– This output pin indicates that other processors (system) will be
prevented from gaining the access of system bus, while LOCK signal is
low.
 Pins used in Maximum Mode (cont..)
• QS1, QS0 (Queue Status)
• These signals provide the status of instruction queue.
• Their conditions are shown in the following table:

• RQ/GT0 and RQ/GT1 (Request/Grant)

• These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus.
• When the signal is received by CPU, then it sends acknowledgment.
• RQ/GT0 has a higher priority than RQ/GT1.
Summary:
 Minimum Mode Configuration of 8086
(Refer: Bhurchandi Book)
• MN/MX = 1

• There is a single microprocessor in the minimum mode system.

• All the control signals are given out by the microprocessor itself.

• The remaining components in the system are:

– Latches
– Transreceivers
– Clock generator
– Memory and
– I/O devices.
Minimum Mode of 8086 System
Latch:
• The latches are generally buffered output D-FFs like 74LS373 or
8282.

• They are used for separating the valid address from multiplexed
address/data signals (AD0-AD15) and address/status signals
(A16/S3-A19/S6).

• It is controlled by ALE signal.

• Commercially available latches contain 8 input lines.

• Thus, for demultiplexing twenty address lines, three chips are

required.
• Transreceivers:
• These are bidirectional buffers.

• It is controlled by two signals: DEN and DT/R.

• DEN indicates valid data is available on the data bus.

• DT/R indicates direction of data i.e. from/to the processor.

• 8086 has multiplexed 16-bit data bus in the form of AD0-AD15,

hence data can be separated from the address and buffered using two
bidirectional buffers (transreceivers).
• Control Signals:
• For deriving control bus from the available control signals RD, WR
and M/IO, any combinational circuit may be used as shown below:
• Clock Generator:
• The clock generator (8284) generates the clock from the
crystal oscillator.

• It is used as an accurate timing reference for the system.

• It also synchronizes some external signals with the system

clock.

• Memory:
• The system contains memory: RAM and ROM.

• A system may contain I/O devices for communication with the

processor.