Mentor Graphics Corporation, Using DesignChecker With SystemVerilog-VHDL Assistant, Release v2018.2

Using DesignChecker with
SystemVerilog-VHDL Assistant
Release v2018.2
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Table of Contents
Chapter 1
Introduction to DesignChecker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DesignChecker Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2
Invoking DesignChecker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Managing Policies and RuleSets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Running an Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3
DesignChecker Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuring Check Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Selecting Design Units and Running the Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Investigate Results in the Results Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Cross-Referencing Results With Source Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Investigate the Results Summary Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 4
DesignChecker Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Set Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Add Code/Rule Exclusions Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
dc_exclude API. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Setting Code/Rule Exclusions Visually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Setting Code/Rule Exclusions Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Enabling Pragma Exclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DesignChecker Predefined Exclusion Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting Black Box Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reviewing and Editing Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reviewing and Editing Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Code/Rule Exclusions Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reviewing and Editing Example Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reviewing Black Box Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reviewing Exclusion Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reviewing Pragma Code Excluded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Reviewing Unbound Component/Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Changing the Behavior of Exclusion Synthesis Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Exclusions Summary Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reporting Exclusions in the Results Summary Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Showing/Hiding Excluded Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 3

Table of Contents
Appendix A
DesignChecker Features Available in SystemVerilog-VHDL Assistant . . . . . . . . . . . . . . 53
DesignChecker-Related Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
End-User License Agreement
4 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

List of Figures
Figure 4-1. Add Code/Rule Exclusions Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 4-2. DesignChecker Results Tab — Excluded Violations . . . . . . . . . . . . . . . . . . . . . 50
Figure 4-3. DesignChecker Results Tab — Excluded Column . . . . . . . . . . . . . . . . . . . . . . . 51

List of Figures

List of Tables
Table 4-1. Exclusion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4-2. Add Code/Rule Exclusion Dialog Box Controls . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4-3. Supported Exclusion Pragma Pairs (Synthesis-Specific) . . . . . . . . . . . . . . . . . . 34
Table 4-4. Supported Exclusion Pragma Pairs (DesignChecker-Specific) . . . . . . . . . . . . . . 34
Table 4-5. Code/Rule Exclusions Pane Font Meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 4-6. Code/Rule Exclusion Pane Options - Exclusion Selected . . . . . . . . . . . . . . . . . . 42
Table 4-7. Code/Rule Exclusion Pane Options - No Exclusion Selected . . . . . . . . . . . . . . . 43

List of Tables

Chapter 1
Introduction to DesignChecker
SystemVerilog-VHDL Assistant integrates with DesignChecker, which is a design checking

tool that ensures interoperability and consistency across design styles and coding practices, for
developers and development teams creating complex designs. It is a powerful solution for
individual engineers.
DesignChecker can operate with a full featured Graphical User Interface (GUI). The user
interface supports quick and easy rule configuration, with powerful results cross-referencing
between DesignChecker and SystemVerilog-VHDL Assistant editor.
This chapter explains the following topics:
DesignChecker Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DesignChecker Flow
The basic flow of DesignChecker involves configuring and running checks on your design
code. The flow starts by configuring your settings and ensuring that you have access to the
appropriate ruleset(s) and policies which have been previously configured by the project
manager to match your coding standards.
To run an analysis, you have to specify the policy you intend to use, and then select the design
units to be analyzed. After running the analysis and viewing the results, you can cross-reference
your results to the source view to identify where the violations occur. Note that before running
an analysis, you have the option to set exclusions on the analyzed code if needed.
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Introduction to DesignChecker
DesignChecker Flow
In the following sections, it is assumed that you are familiar with the basic operation of
DesignChecker and SystemVerilog-VHDL Assistant. For information, refer to DesignChecker
User Guide and SystemVerilog-VHDL Assistant Reference Manual.
Chapter 2
Invoking DesignChecker
DesignChecker can be invoked in several ways from SystemVerilog-VHDL Assistant.

DesignChecker can be invoked for two reasons:
1. To Manage Policies and RuleSets: DesignChecker enables the user to create the
desired rulesets and policies that are to be applied to design units before running an
analysis. It is possible to manage polices and rules by invoking DesignChecker directly
from SystemVerilog-VHDL Assistant.
2. To Run an Analysis: DesignChecker integrates with SystemVerilog-VHDL Assistant,
such that it is possible to run an analysis using DesignChecker directly through
SystemVerilog-VHDL Assistant.
This chapter explains the following topics:
Managing Policies and RuleSets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Running an Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Managing Policies and RuleSets

You can invoke DesignChecker through SystemVerilog-VHDL Assistant for the purpose of
configuring rulesets and policies.
Procedure
1. To manage policies and rulesets, do one of the following from SystemVerilog-VHDL
Assistant:
• From the Projects browser, select the project’s node then select Tools> Checks.
Then choose Manage TB Policies/Rulesets or Manage RTL Policies/Rulesets.
Managing Policies and RuleSets
Note that this option is only available if a project is selected.
• From the Projects browser, right click the project’s node then select Project
Settings from the popup menu. The Project Settings dialog box will be displayed.
Select the Check Settings node then, depending on your need, press the Manage
button for TB Policy or RTL Policy.
Running an Analysis
2. DesignChecker will be invoked with the Setup tab opened.
Running an Analysis
To run an analysis through SystemVerilog-VHDL Assistant, you must first set the policy and
select the desired design unit for analysis.
For more information on how to run the analysis directly through SystemVerilog-VHDL
Assistant, refer to “Selecting Design Units and Running the Analysis” on page 17.
Running an Analysis
Chapter 3
DesignChecker Flow
This chapter describes how you can validate the correctness of the designs available in
SystemVerilog-VHDL Assistant by using DesignChecker.
The basic DesignChecker flow is as follows:
Before using DesignChecker to validate your code, make sure you have a design in
SystemVerilog-VHDL Assistant, whether an already existing design that you have imported or
a new design that you have created. You should also make sure the design is compiled before
running a DesignChecker analysis.
Refer to SystemVerilog-VHDL Assistant Reference Manual for more information.
Note
Before selecting design units and running an analysis, you have the ability to set exclusions.
The exclusions feature allows you to exclude specific code blocks from analysis, and to
exclude certain rules/rulesets from being applied to the analysis. For more information on
exclusions, refer to “DesignChecker Exclusions” on page 23.
Configuring Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Selecting Design Units and Running the Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Investigate Results in the Results Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Cross-Referencing Results With Source Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Investigate the Results Summary Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Configuring Check Settings

To run an analysis using DesignChecker, you must first set some options that will affect your
DesignChecker analysis.
Procedure
1. Select the project’s node then do one of the following:
• Choose Project Settings option from the popup menu.
• Choose Tools> Project Settings.
The Project Settings dialog box displays.
DesignChecker Flow
Configuring Check Settings
2. From the left pane, select the Check Settings page. The Check Settings page displays.
3. In the Check Settings pane on the right hand side, you can set the following options:
• Policy Location: Use this field to type the path to your policies directory or you can
use the Browse button to select a path.
• TB Policy: Use the dropdown box to select the policy you want to apply to your
DesignChecker analysis. Refer to the DesignChecker User Guide for more
information on setting a policy through DesignChecker.
• RTL Policy: Use the dropdown box to select the policy you want to apply to your
DesignChecker analysis. Refer to the DesignChecker User Guide for more
information on setting a policy through DesignChecker.
• RuleSet Location: Use this field to type the path to your rulesets directory or you
can use the Browse button to select a path.
• Exclusion File Location: Use this field to type the path to your exclusion file
directory or you can use the Browse button to select a path.
• Enable pragma exclusions: Select this option if you want to apply exclusions via
pragmas to your analysis. This enables you to skip RTL code blocks while running a
DesignChecker analysis. You can use the pragma checking_off/on to enclose the
blocks of code you want to exclude when running an analysis. For information, refer
to “Enabling Pragma Exclusion” on page 32.
DesignChecker Flow
Selecting Design Units and Running the Analysis
• Manage Policies/ RuleSets: Clicking this button invokes the DesignChecker tool in
order to set up rules and policies.
4. Click OK.
Selecting Design Units and Running the

Analysis
Before running an analysis, you need to select the project/file’s node you need to verify from
one of the SystemVerilog-VHDL Assistant’s browsers.
Procedure
Do one of the following:
a. From the Projects browser, select the project/file’s node then choose Tools>
Checks> Using TB [Verification_UVM_Policy] or Using RTL
[My_Essentials_Policy].
b. From the Projects browser, right click the project/file’s node then select Checks >
Using TB [Verification_UVM_Policy] or Using RTL [My_Essentials_Policy].
Note
For projects, you should mark the desired units to run on as “top”. SystemVerilog-
VHDL Assistant runs checks on the selected project through hierarchy of detected/
identified top design units, in addition to other selected top design units. Also note that:
• Any design unit not in the hierarchy of SystemVerilog-VHDL Assistant top design
units, is not checked.
• Any project that doesn’t have top design units, is not checked.
Note
For files, SystemVerilog-VHDL Assistant runs checks on the selected file through
hierarchy of detected/identified compilation units included in this file.
Also note that, any design unit not included in the hierarchy of selected file compilation
units, is not checked.
Caution
After running your analysis on a certain project, changing the policy location for that
project will not be reflected on DC instance.
DesignChecker Flow
Investigate Results in the Results Tab

Once you run an analysis through SystemVerilog-VHDL Assistant, DesignChecker is invoked
with the Results tab opened and all the detected violations are displayed.
The Results tab is divided into a central results pane in which all the violations are listed, and a
summary pane in which you will find high level information about the analysis.
By default, the Results tab shows the results grouped by severity, and then within each severity,
the results are grouped by the violated rule (you can control the display of results by changing
viewpoints; refer to the DesignChecker User Guide for more information).
DesignChecker Flow
You can use the plus sign to keep traversing down from the severity group until you reach the
violation message and the code snippet highlighting the exact line of code having that violation.
As shown in the figure, each violation is given a certain severity level depending on the prior
configurations of the ruleset. For example, if the ruleset is using the severity set titled Default
SeveritySet, the violations will have the severity levels Error, Note or Warning, and if the
ruleset is using the severity set titled RMM_SeveritySet, the violations will have the severity
levels Rule or Guideline. Refer to “Configuring Rule SeveritySets” in the DesignChecker User
Guide for further information.
In addition to the current severity set used in your analysis, you may find some violations
having different titles such as Syntax Error, Synthesis Error or Elaboration Error. These types
DesignChecker Flow
Cross-Referencing Results With Source Views
of violations can occur when running certain rules on a design that is not complete or
synthesizable. For more information, refer to “Supporting Synthesizable Designs” and “Further
Understanding Design Checking Rule Behavior” in the DesignChecker User Guide.
Cross-Referencing Results With Source Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Investigate the Results Summary Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Cross-Referencing Results With Source Views

You can cross reference from a violation message in the Results tab of DesignChecker to the
source view in SystemVerilog-VHDL Assistant.
Procedure
1. Open the Results tab in DesignChecker.
2. Expand the results till you reach the violation message you need to trace.
3. Double-click on the violation message. You can also right-click on the violation
message and select Open HDL from the popup menu. Consequently, SystemVerilog-
VHDL Assistant editor opens and the violation line is highlighted.
DesignChecker Flow
Investigate the Results Summary Pane
4. Move around the code by clicking on the different violations highlighted in the Report
pane. The code editing pane in SystemVerilog-VHDL Assistant automatically changes
to display the appropriate line of code.
Note
A tooltip is displayed when you right-click on the line number in SystemVerilog-
VHDL Assistant text editor’s context bar.
5. Investigate the other DesignChecker menu options.

The Results Summary pane provides high level information on the results of the analysis.
For more information on the results summary pane, refer to DesignChecker User Guide.
DesignChecker Flow
Chapter 4
DesignChecker Exclusions
Before running an analysis, you can set the exclusions feature which enables you to exclude
certain areas of your code from being analyzed or more specifically exclude certain rules or
rulesets from being run on your code.
Excluding certain areas of your code from being generally checked, or excluding certain rules
from running on your code, saves you the hassle of having to go through the violations that may
be generated by this code, which could be in fact behaving as designed or could be third-party
code which does not comply with your coding standards.
On running an analysis, an Exclusions tab displays showing all the exclusion settings applied in
the analysis.
Set Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setting Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
dc_exclude API. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DesignChecker Predefined Exclusion Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting Black Box Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reviewing and Editing Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Reviewing and Editing Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reviewing Black Box Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reviewing Unbound Component/Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Changing the Behavior of Exclusion Synthesis Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Exclusions Summary Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reporting Exclusions in the Results Summary Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Showing/Hiding Excluded Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Set Exclusions
Set Exclusions
DesignChecker has the following types of exclusions that can be used with SystemVerilog-
VHDL Assistant:
Table 4-1. Exclusion Types

Exclusion Type Description
Code/Rule Exclusion Excludes specific checks from being performed on specific
parts of the design.
Pragma Exclusion Allows you to skip specific RTL code blocks.
Black Box Exclusion Ensures that DesignChecker recognizes that a component is
present, but does not apply any checks to it.
Setting Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DC Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
dc_exclude API. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DesignChecker Predefined Exclusion Pragmas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Setting Black Box Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Setting Code/Rule Exclusions

Exclusion via Code/Rule exclusions enables you to force DesignChecker to skip selected design
units or files when running a specific rule or ruleset.
You can set your Code/Rule exclusions visually through the DesignChecker Add Code/Rule
Exclusions dialog box (Figure 4-1) or you can set them manually by editing the dc_constraints
file. Note that the dc_constraints file location is set from the Check Settings page in the Project
Settings dialog box.
Caution
It is strongly recommended not to edit the dc_constraints file when running DesignChecker.
Also, attempting to edit the dc_constraints file while in the process of adding code/rule
exclusions visually may lead to the loss of your manual edits.
Add Code/Rule Exclusions Dialog Box

To access: From DesignChecker tool, do one of the following:
• From the DesignChecker menu, choose Exclusions > Add Code/Rule Exclusion.
• In the Code/Rule Exclusions pane of the Exclusions tab, right-click and choose Add
Code/Rule Exclusion.
• Select Exclusions in the shortcut bar on the left and click Add Code/Rule Exclusion.
The Add Code/Rule Exclusions dialog box enables you to define code/rule exclusions for
libraries on which an analysis was previously run. That is, you can exclude specific checks from
being performed on specific parts of the design on the next DesignChecker run.
Figure 4-1. Add Code/Rule Exclusions Dialog Box
Objects
Table 4-2. Add Code/Rule Exclusion Dialog Box Controls
Control Description
Justification field Allows you to enter a justification for your defined exclusion.
DC Constraints File
Table 4-2. Add Code/Rule Exclusion Dialog Box Controls (cont.)

Control Description
Object group box Allows you to define whether you want to exclude a file or a design
unit.
Exclude Source File
Object Library field Allows you to specify the library you want to exclude a file from.
The list displays the libraries on which you had run your last
analysis.
File Path field Lets you enter or browse for the file you want to exclude from
checking. Note that this field accepts relative paths as well as full
paths.
Exclude Design Unit
Object Library field Allows you to specify the library you want to exclude a design unit
from. The list displays the libraries on which you had run your last
analysis.
Unit Name field Allows you to select a design unit from the specified library to
exclude from checking.
Line Range Group Box Allows you to define line-level exclusions. You can enter a specific
range of code lines to be excluded from the analysis of the source
file or design unit which is specified in the Object Group Box.
Enter the Start Line number and the End Line number.
If you wish to exclude a single line, then enter the same line
number as the Start Line and End Line.
Rule box Allows you to browse for rules or rulesets you want to disable for
the objects defined in the Object group box.
Location field Displays the path to the chosen rules/rulesets
DC Constraints File
The DC constraints file is a Tcl file in which code/rule exclusions set for a given library are
saved. The file is given the name ‘dc_constraints.tcl’ and its location is set from the Check
Settings page in the Project Settings dialog box.
The content of the file is derived from the code/rule exclusions set visually through
DesignChecker or set manually by directly editing the file using the dc_exclude command.
Refer to “dc_exclude API” on page 28.
Note
Do not attempt to edit the dc_constraints file when running DesignChecker to avoid losing
your manual edits.
dc_exclude API
dc_exclude API
Exclude selected library design unit or file from being checked by the specified rule or ruleset.
Exclusion settings are associated to the library under which the dc_constraints file holding the
dc_exclude command resides.
Usage
dc_exclude -library <library name | * | all > -design_unit <design unit name | * | all> | -
source_file <file path | * | all > -start_line <line number> -end_line <line number> -check
<hierarchical check path> [comment<comment text>]
Arguments
• -library <library name>
Specifies the library to which exclusions will be applied.
• -design_unit <design unit name>
Specifies the design unit name to be excluded from the check. You must specify either -
design_unit or -source_file. Check examples below.
• -source_file <file path | * | all >
Specifies the path to the file to be excluded from the check. Note that this argument accepts
both relative and full file paths. For relative paths, the path is relative to your current
directory, or to the TCL script where it is written in. Also, you must specify either -
design_unit or -source_file. Check examples below.
• -start_line <line number>
Specifies the start line of the excluded range. Note that it only accepts integers. (Optional)
• -end_line <line number>
Specifies the end line of the excluded range. Note that it only accepts a positive integer
greater than or equal the start_line. (Optional)
• -check < check path>
Specifies the path to the rule or ruleset name to be disabled for a specific design unit or file.
• -comment <comment text>
Specifies comment text that you can associate with the defined exclusion. (Optional)
Examples
• Exclude the file coverage.svh from being checked by the Verification_UVM ruleset
dc_exclude -source_file {R:\SVA\examples\projects\UVM\multadd_uvm\
multadd_uvm_hds_lib\svassistant\multadd_uvm\Design_Src\environment\
coverage.svh}
-check {RuleSets\Verification_UVM}
Setting Code/Rule Exclusions Visually
• Exclude the design unit Printer from being checked by UVM Components:
build_phase() method required
configured rule
dc_exclude -design_unit {printer}
-check {RuleSets\Verification_UVM\UVM Components: build_phase()
method required}
• Exclude the file scoreboard.svh from being checked by the OVM Allowed Classes base
rule and all its configured rules
dc_exclude -source_file {R:\SVA\examples\projects\UVM\multadd_uvm\
multadd_uvm_hds_lib\svassistant\multadd_uvm\Design_Src\environment\
scoreboard.svh}
-check {Base Rules\Verification\OVM Allowed Classes} -comment
{exclusions}

Code/Rule Exclusions can be set visually through the Add Code/Rule Exclusions dialog box or
through working directly with the analysis results in the Results tab.
Procedure
1. Through the Add Code/Rule Exclusions dialog box:
a. Open the Add Code/Rule Exclusions dialog box. Refer to “Add Code/Rule
Exclusions Dialog Box” on page 25.
b. In the Object group box, define the design object to be excluded by selecting one of
the following:
o Exclude Source File: This excludes a design file from being checked.
• From the Object library drop-down list specify the source file library.
• Enter or browse to the design file path.
o Exclude Design Unit: This excludes a design unit from being checked.
• Specify the design unit library from the Object library drop-down list.
• Specify the design unit name from the Design unit drop-down list.
c. In the Line Range Group Box, enter a specific range of code lines to be excluded
from the analysis of the source file or design unit which is specified in the Object
Group Box. Enter the Start Line number and the End Line number. If you wish to
exclude a single line, then enter the same line number as the Start Line and End Line
d. In the Rule box, select the rulesets or rules you want to disable for the design objects
specified in step two. The path to the selected rule/ruleset is displayed in the
Location field.
e. Click OK to close the Add Code/Rule Exclusions dialog and run your analysis.
2. Through the Results tab:
a. Expand the Warning or Error tree then select a violation for a rule/ruleset and design
unit/file you want to disable. For example, you can select the violation for “UVM
Components: Do not construct Components directly” rule and scoreboard class.
b. Right-click and choose Disable Rule For to display a cascade menu from which you
can select one of the following:
o Policy <policy used in last run>
o Design Unit <violating design unit name>
o Source File <violating source file name>
o Source File <violating source file name> <code line number>
Note
If the option “Prompt for justification” is selected in the Edit Justification dialog
box, then the Edit Justification dialog box pops up automatically for you to enter
a justification for the exclusion. Refer to “Adding Justification for Disabled Rules”
in the DesignChecker User Guide for information on this option.
c. Select the required design unit or file and run your analysis.
Note
You can turn on or off certain checks through the Results tab. You can right-click on
a violation message in the Results tab and select Disable Rule/RuleSet For from
the popup menu and from the cascade menu you can choose whether to disable the rule/
ruleset on the level of the policy, design unit, source file, or the code line number in the
source file. You can re-enable checks in the same way by right-clicking on the violation
message and selecting EnableRule/RuleSet For from the popup menu and from the
cascade menu you can choose whether to enable the rule/ruleset on the level of the
policy, design unit, source file, or the code line number in the source file.
Any rules/rulesets you disable for design units or source files are displayed in the
Exclusions tab; refer to “Reviewing and Editing Exclusions” on page 39.
Related Topics
DC Constraints File
Reviewing and Editing Exclusions
Setting Code/Rule Exclusions Manually
Setting Code/Rule Exclusions Manually

You can set you code/rule exclusions manually through the .dc_constraints.tcl file. This file can
be edited in SystemVerilog-VHDL Assistant’s editor.
Procedure
1. From SystemVerilog-VHDL Assistant tool, choose File > Open File. The Open File
window displays.
2. Navigate to the location you set before in the Check Settings page.
3. Select the .dc_constraints.tcl file then press the Open button. The file displays in
SystemVerilog-VHDL Assistant’s editor.
4. Add your exclusions using the dc_exclude command, save your file and then run your
analysis. Refer to “DC Constraints File” on page 27.
Related Topics
DC Constraints File
Enabling Pragma Exclusion

Exclusion via Pragma Pairs enables you to force DesignChecker to skip specific RTL code
blocks while running an analysis.
For example, parts of your code may be used only for debugging purposes, and hence, it may
not be necessary to have these parts checked. In this case, you can enable the Exclusion via
Pragma Pairs feature, and then apply the pragmas to your code. This feature relies basically on
embedding the pragmas in your HDL code in such a way to enclose the sections that shall be
excluded by DesignChecker.
Procedure
1. Select the project’s node then do one of the following:
• Choose Project Settings from the popup menu.
• Choose Tools > Project Settings.
The Project Settings dialog box displays.
2. Select the Check Settings page.
3. Check the Enable pragma exclusions option.
By doing this step, the pragma checking_off/on is enabled.
Note
Synthesis pragmas are always enabled (translate_off/on, synthesis_off/on,
dc_script_begin/end). You can only enable or disable the DesignChecker-specific
pragma checking_off/on by checking/ unchecking the Enable pragma exclusion option
in the Check Settings page. The pragma checking_off/on cannot exclude syntax errors.
4. Within your source code, use the exclusion pragma pair checking_off/on to encase the
excluded code.
The pragma pair constitutes of a start pragma and an end pragma. The start pragma is
placed as a comment before the beginning of the code block as an indication for
DesignChecker to stop analysis at this point; similarly, the end pragma is placed as a
comment after the end of the code block as an indication to resume analysis.
For example, you can exclude RTL code sections or you can exclude a whole design
unit.
DesignChecker Predefined Exclusion Pragmas
// pragma checking_off
ma_agent_req_item expected_txn;
ma_agent_rsp_item actual_txn;
ma_agent_rsp_item predicted_txn;
// pragma checking_on
Caution
Double commenting a pragma disables the pragma.
It is recommended to write the pragma in a separate line to ensure it works properly.
5. Run the analysis. For details on running an analysis, refer to “Selecting Design Units
and Running the Analysis” on page 17.
The Results tab opens displaying the outcome of the analysis; the details of the
exclusion settings are displayed in the Summary pane. For more details on how
exclusion affects your results, refer to “Reporting Exclusions in the Results Summary
Pane” on page 48.
Related Topics
Selecting Design Units and Running the Analysis
Reporting Exclusions in the Results Summary Pane

In addition to the DesignChecker-specific pragma checking_off/on, DesignChecker provides a
predefined set of synthesis-specific pragmas you can use for code exclusion. Each pragma pair
is defined by a start pragma name and an end pragma name.
Optionally, the DesignChecker checking_off/on pragma can be enabled or disabled through the
Projects Settings dialog box - Check Settings page.
All the synthesis pragmas (listed in Table 4-3) are always enabled by default. The supported
pragma pairs are as follows:
Table 4-3. Supported Exclusion Pragma Pairs (Synthesis-Specific)
Short Name Start Pragma End Pragma
dc_script_begin/end dc_script_begin dc_script_end
synthesis_off/on synthesis_off synthesis_on
translate_off/on translate_off translate_on
Table 4-4. Supported Exclusion Pragma Pairs (DesignChecker-Specific)

Short Name Start Pragma End Pragma
checking_off/on checking_off checking_on
Setting Black Box Exclusions
You insert the start pragma before the excluded code, and then insert the end pragma after.
Thus, this pragma-enclosed section is skipped during the DesignChecker analysis.

Marking a design component as a “Black Box” ensures that DesignChecker recognizes that
component is present, but does not apply any checks to it. For example, you may want to mark
third party components used in your designs as black boxes as they may not comply with your
coding standards.
Procedure
1. To set black box exclusions, do one of the following:
• You can set the source view corresponding to the selected result row as a black box
for DesignChecker by choosing Set Black Box File from the popup menu of the
message in the Results tab.
• Alternatively, select a folder/file and choose Checks> Exclude From Check from
the popup menu in the SystemVerilog-VHDL Assistant Projects browser.
You can add a justification to the excluded file to explain why this file is excluded
by selecting the file and choose Check> Edit Justification from the popup menu.
Tip
When a file has been set as a black box for DesignChecker, the file is parsed but
no checks are performed. Files that have been excluded can be identified in the
Projects browser by the presence of the icon in the Excluded column.
2. To unset black box exclusions, do one of the following:

• From the Exclusions tab in DesignChecker, select a file from the Black Box Files
pane then choose Remove Exclusion from the popup menu.
• From the Projects browser in SystemVerilog-VHDL Assistant, select a folder/file

and choose Checks> Include In Check from the popup menu in the
SystemVerilog-VHDL Assistant Projects browser.

Once you have run DesignChecker, the Exclusions tab is available from which you can review
the exclusions related to the last run. The tab contains facilities to add/edit code/rule exclusions,
remove exclusions or link to excluded files or rules. The Exclusions tab is divided into an
exclusions viewpoint and a summary pane, as shown in the picture below.
The summary pane (shown on the right) contains high-level information about the policy
disabled rules, code/rule exclusions, black boxed files, exclusion pragmas and unbound
component/instances.
The viewpoint (shown on the left) displays code/rule exclusions, black-boxed files, exclusion
pragmas, pragma excluded code and unbound component/instances each in a separate pane.
Reviewing and Editing Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Reviewing Black Box Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reviewing Unbound Component/Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Changing the Behavior of Exclusion Synthesis Pragmas. . . . . . . . . . . . . . . . . . . . . . . . . 45
Reviewing and Editing Code/Rule Exclusions

If you have set code/rule exclusions, whether in the Add/CodeRule Exclusions dialog box, in
the DesignChecker Results tab or in the constraints file, these exclusions are shown in the
Code/Rule Exclusions pane of the Exclusions tab after running analysis. You can use the Code/
Rule Exclusions pane to examine and edit your exclusions.
Code/Rule Exclusions Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reviewing and Editing Example Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . 43
Code/Rule Exclusions Pane

The Code/Rule Exclusions pane displays a list of all the library code/rule exclusions set for the
libraries on which DesignChecker was last run.
Refer to “Reviewing and Editing Example Code/Rule Exclusions” on page 43.
Columns Available in Code/Rule Exclusions Pane

The Code/Rule Exclusions pane contains columns showing information on each exclusion in
the Code/Rule Exclusions pane. There are some columns that are available by default. If you
want to add columns, right-click on the header row and choose Select Columns > “column
name”.
• Object Name — The design unit or source file that is being excluded in conjunction
with a rule.
• Start Line — If you have excluded a Line Range, this column shows the number of the
start line.
• Library — The library to which the excluded object belongs.
• Rule Name — The check that is not applied to the object.
• Object Type — Specifies whether the object is a Design Unit or Source File.
• Justification — Shows the justification you previously defined for the exclusion in the
Add Code/Rule Exclusions Dialog Box.
• Affects Results — The value of this column is “Yes” or “No” depending on whether the
exclusion affected the last analysis in the current session or not.
• End Line — If you have excluded a Line Range, this column shows the number of the
end line.
• Object Full — The full name of the excluded object if it is a design unit or the physical
path if it is a source file.
• Rule Path — The path of the rule within the RuleSet. For example: RuleSets\
Verification_UVM\UVM Sequence_item: Do not construct directly
Exclusion Font Meaning
DesignChecker shows exclusions in the Code/Rule Exclusions pane in different font weight and
color depending on whether the exclusion affects results or not.
Table 4-5. Code/Rule Exclusions Pane Font Meaning
Font Meaning
Bold Black The exclusion affects the results of the last analysis run by DesignChecker.
Also, the Affects Results column shows the value “Yes”.
Regular Black The exclusion does not affect the results of the last analysis run by
DesignChecker. Also, the Affects Results column shows the value “No”.
Regular Red The exclusion is invalid due to a problem in one of the following: rule
name, file name or design unit name. A tooltip provides more information
on reason the exclusion is invalid. Also, the Affects Results column shows
the value “No”.
Operations Available in Popup Menu

You can perform several operations directly in the Code/Rule Exclusions pane from the popup
menu.
If you select one of the listed exclusions and right-click, a popup menu displays with the
following options:
Table 4-6. Code/Rule Exclusion Pane Options - Exclusion Selected
Menu Item Description
Edit Code/Rule Exclusions Displays the Edit Code/Rule Exclusions dialog box to
enable you to change the information related to the
selected exclusion. Refer to “DC Constraints File” on
page 27.
Show Disabled Rule Displays the Setup tab with the disabled rule highlighted.
Open Source File(s) Opens DesignPad showing the excluded file. Notice that
this option is disabled if a rule was disabled for a design
unit.
Remove Exclusion Deletes the selected exclusion.
If you right click in the Code/Rule Exclusions pane without selecting an exclusion a popup
menu with the following options is displayed.
Table 4-7. Code/Rule Exclusion Pane Options - No Exclusion Selected

Menu Item Description
Add Code/Rule Exclusion Displays the Add Code/Rule Exclusions dialog box to
enable you to add a new exclusion.
Remove all Exclusions Deletes all the exclusions listed in the Code/Rule
Exclusions pane.
Reviewing and Editing Example Code/Rule Exclusions

The code/rule exclusions pane displays the code/rule exclusions related to files that are part of
the library on which DesignChecker was last run.
(See “Code/Rule Exclusions Pane” on page 41.)
This is an example to demonstrate how exclusions related to the last DesignChecker analysis
results are highlighted.
Prerequisites
• multadd_uvm project should be opened.
• DesignChecker should be configured to use Verification_UVM_Policy.
Procedure
1. In the Projects browser of SystemVerilog-VHDL Assistant, right-click the multadd_uvm
project and choose Checks > Using TB Policy [Verification_UVM_Policy].
DesignChecker opens the Results tab showing the violations found through analysis.
2. In the DesignChecker Results tab, select a violation for “UVM Components:
build_phase() method required” rule and printer file. Choose Disable Rule
For > Design Unit ‘printer’ from the popup menu.
Note
If the option “Prompt for justification” is selected in the Edit Justification dialog
box, then the Edit Justification dialog box pops up automatically for you to enter a
justification for the exclusion. Refer to “Adding Justification for Disabled Rules” in the
DesignChecker User Guide for information on this option.
DesignChecker re-runs the analysis.

3. Open the Exclusions tab and examine the content of the Code/Rule Exclusions pane.
A row is added in the Code/Rule Exclusions pane showing the new exclusion in bold
font. The bold font indicates that the new exclusion affects the results of the last analysis
Reviewing Black Box Exclusions
run by DesignChecker. Also, the Affects Results column shows the value “Yes” further
indicating that this exclusion setting affects the analysis results.
Note
If the Affects Results column is not shown, right-click on the header row and choose
Select Columns > Affects Results.
4. In the DesignChecker Results tab, select a violation for “UVM Sequence_item: Do not
construct directly” rule and minmax_seq.svh file. Choose Disable Rule For > Source
File ‘minmax_seq.svh’ from the popup menu.
DesignChecker re-runs the analysis.
5. Open the Exclusions tab and examine the content of the Code/Rule Exclusions pane. A
new “minmax_seq/ UVM Sequence_item: Do not construct directly” exclusion is added
in bold and the Affects Results column indicates “Yes”. Note that the “scoreboard/UVM
Components: build_phase() method required” exclusion is now displayed in normal font
as it does not affect the results of the last analysis.
Related Topics
Code/Rule Exclusions Pane
Reviewing Black Box Exclusions

The Black Boxed Files pane displays the black box exclusions set for the code on which
DesignChecker was last run.
Refer to “Setting Black Box Exclusions” on page 35.
You will be able to view the name of the black boxed file, the library to which it belongs, the
dialect of the file, the location of the file on the hard disk, whether or not the file affects results,
and the justification for being marked as a black box.
You can right-click on any black box exclusion and select Open Source File(s) from the popup
menu to open the source file in SystemVerilog-VHDL Assistant’s text editor. You can also
select Edit Justification which opens the Black-Box Justification dialog box in which you can
edit or add an explanation for reference.
You can cancel the black box by right-clicking on the required black box exclusion and
selecting Remove Exclusion from the popup menu.
Reviewing Exclusion Pragmas
Reviewing Exclusion Pragmas

The Exclusion Pragmas pane displays the pragmas set for the project that includes the files on
which DesignChecker was last run. Exclusions related to design files that were part of the last
analysis are shown in bold while those related to files that were not are listed in normal font.
Reviewing Pragma Code Excluded

The Pragma Code Excluded pane shows all the code blocks that have been excluded from the
latest DesignChecker analysis due to using exclusion pragmas.
The pane shows the Start Pragma and End Pragma used in the exclusion, the name of the file in
which the pragma pair was used, the number of the Start Line and End Line of the excluded
code block, and the location of the file on the hard disk.
Note that double-clicking on an entry in this pane opens the corresponding file in
SystemVerilog-VHDL Assistant’s editor.
Reviewing Unbound Component/Instances

The Unbound Component/Instances pane displays a list of the instances which are not bound to
masters as found in the latest DesignChecker analysis.
You will be able to view the name of the unbound instance, the name of its missing master, the
name of the relevant file, the line number of the instance, and location of the file on the hard
disk.
Changing the Behavior of Exclusion Synthesis

Pragmas
DesignChecker enables you to control the behavior of synthesis pragmas to operate at synthesis
level or at parsing level.
The exclusion pragmas supported by DesignChecker allow you to exclude blocks of code from
analysis. In addition to the DesignChecker-specific pragma checking_off/on, DesignChecker
provides a predefined set of synthesis-specific pragmas that you can also make use of in
DesignChecker analysis exclusion.
Synthesis pragmas are primarily used to communicate with synthesis tools to switch off/on
synthesis for the enclosed code. The synthesis-specific pragmas supported by DesignChecker
are: dc_script_begin/end, synthesis_off/on and translate_off/on. By default, these pragmas
operate at synthesis level, that is, code enclosed between synthesis pragmas is ignored by the
synthesis engine. You have the ability to switch synthesis pragmas to operate at parsing level,
that is, code enclosed between synthesis pragmas is ignored by the parsing engine. This ability
Changing the Behavior of Exclusion Synthesis Pragmas
to change the behavior of synthesis pragmas applies only to synthesis_off/on and translate_off/
on.
Prerequisites
• Set up your DesignChecker-specific pragma exclusions (refer to “Enabling Pragma
Exclusion” on page 32), use synthesis-specific pragmas (synthesis_off/on or
translate_off/on) and DesignChecker-specific pragmas (checking_off/on) to enclose
code blocks as needed, and then run DesignChecker analysis on your design.
Procedure
1. In DesignChecker, open the Exclusions tab, and then go to the Exclusion Pragmas pane.
2. Check the Level column.
This column displays the current level of the exclusion pragma. The level of the
checking_off/on pragma is “checking”, and that of the synthesis_off/on and
translate_off/on pragmas is “synthesis” by default.
3. Right-click on the synthesis_off/on or translate_off/on pragmas and choose Switch
Level to Parsing.
The value in the Level column for synthesis_off/on and translate_off/on pragmas
changes from “synthesis” to “parsing”. Hence, in any future operations that involve
parsing, any code block enclosed in these synthesis pragmas is excluded from parsing.
4. (Optional) Right-click on the synthesis_off/on or translate_off/on pragmas and choose
Switch Level to Synthesis to toggle back to synthesis level.
Exclusions Summary Pane
Related Topics
Exclusions Summary Pane

The Exclusions summary pane displays an overview of the set exclusions in tabular form under
the following headings:
• Policy Disabled Rules: This displays information about the rules that have been
disabled from a specific policy. For example:
• Code/Rule Exclusions: This displays the names of the libraries that were part of the last
DesignChecker analysis, the number of the set code/rule exclusions, and the number of
exclusions that were actually used in the last run.
• Black Boxed Files: This displays the number of black box exclusions. For example:
• Exclusion Pragmas: This shows the number of excluded code blocks and the number of
exclusion pragmas. Refer to “Enabling Pragma Exclusion” on page 32 for information.
Note that the number of exclusion pragmas reflects the actual number of pragma types
encountered during the analysis (for example: checking_off/on, dc_script_begin/end,
and so on).
• Unbound Component/Instances: This displays the number of unbound component/
instances and the number of missing masters in the latest run.
Reporting Exclusions in the Results Summary

Pane
The Summary pane of the Results tab contains a section titled Exclusions, in which data on the
exclusion settings is displayed.
Refer to “Set Exclusions” on page 24 for more information on how to set exclusions.
It is important to note that the data shown in the Exclusions section includes data on the
exclusion settings that affected the last performed analysis only. For example, you may have set
four files as black boxed files, whereas only two are reported in the Exclusions pane of the
Results Summary pane; this means that only two black boxed files of the four were involved in
the scope of analysis.
The following data is displayed in the Exclusions summary section:
• Policy Disabled Rules — shows the number of rules that have been disabled in the
policy and hence were not applied to the analyzed code. If you right-click on this entry
and select Show Exclusions from popup menu, the Rule Details tab is opened
displaying the policy. Refer to “The Rule Details Tab” in the DesignChecker User
Guide for information on the tab’s content.
• Code/Rule Exclusions — shows the number of code/rule exclusions that have affected
the analysis results. If you right-click on this entry and select Show Exclusions from the
popup menu, the Exclusions tab is opened displaying the Code/Rule Exclusions pane.
• Black Boxed Files — shows the number of black boxed files that have been excluded
from the analyzed code. If you right-click on this entry and select Show Exclusions
from the popup menu, the Exclusions tab is opened displaying the Black Boxed Files
pane.
• Exclusion Pragmas — shows the number of exclusion pragma types that have affected
the analyzed code. On running a DesignChecker analysis while having enabled
exclusion pragmas, DesignChecker will skip the HDL blocks wrapped by the pragma
pairs. If you right-click on this entry and select Show Exclusions from popup menu, the
Exclusions tab is opened displaying the Exclusion Pragmas pane.
Enabling exclusion pragmas is reflected on your results as follows:
o If an entire design unit is excluded, it will not be counted in the total number of
analyzed design units which is shown in the Design Units section of the Results
Summary pane.
• Pragma Code Excluded — shows the number of code blocks that have been discarded
from analysis using exclusion pragmas. If you right-click on this entry and select Show
Exclusions from the popup menu, the Exclusions tab is opened displaying the Pragma
Code Excluded pane.
• Missing Masters — shows the number of missing masters in the analyzed design. If
you right-click on this entry and select Show Exclusions from the popup menu, the
Exclusions tab is opened displaying the Unbound Component/Instances pane.
• Unbound Instances — shows the number of instances that are not bound to masters. If
you right-click on this entry and select Show Exclusions from the popup menu, the
Exclusions tab is opened displaying the Unbound Component/Instances pane.
Showing/Hiding Excluded Violations

DesignChecker provides a waivers feature which allows you to control whether to show or hide
excluded violations in the Results tab. This feature enables you to adjust the degree of visibility
over analysis violations according to your needs.
Procedure
1. Specify the policy which you want to use for DesignChecker analysis. Refer to
“Managing Policies and RuleSets” on page 11.
2. Specify the code/rule exclusions you need to apply to your DesignChecker analysis.
Refer to “Set Exclusions” on page 24.
3. Select the project and then run the DesignChecker analysis. Refer to “Selecting Design
Units and Running the Analysis” on page 17.
4. After the analysis is run, open the Results tab to examine the violations.
Note how the violations related to the set exclusions are highlighted in the Results tab.
Figure 4-2. DesignChecker Results Tab — Excluded Violations
You can show the “Excluded” column, which helps you identify whether the violation is
excluded or not. You can group results by the “Excluded” column for better visibility by
right-clicking on the column name and selecting Group by this column from the popup
menu.
Figure 4-3. DesignChecker Results Tab — Excluded Column
5. Hide excluded violations by doing one of the following:

• From the DesignChecker menu bar, select Results > Show/Hide Excluded
Violations.
• Click Exclude Highlighted Violations on the Results shortcuts bar on the left hand
side.
You can show excluded violations again using the same method. Note the name of the
button in the Results shortcut bar changes to Show Highlighted Violations.
Note how the excluded violations are reported in the Violations section of the Summary
pane.
Note
On exporting results reports, you have the option to display excluded violations in
the report. Refer to “Exporting Results” in the DesignChecker User Guide.
Appendix A
DesignChecker Features Available in
SystemVerilog-VHDL Assistant
This appendix provides DesignChecker-related features you can use through SystemVerilog-
VHDL Assistant.
DesignChecker-Related Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DesignChecker-Related Features
The following list of DesignChecker-related features can be performed directly through
SystemVerilog-VHDL Assistant.
• Invoking DesignChecker
• Setting the Default Policy
• Running DesignChecker
• Accessing the DC_constraints file and changing its location
• Setting Pragma Exclusions
• Setting Black Box Exclusions
• Sharing RuleSets and Policies
DesignChecker Features Available in SystemVerilog-VHDL Assistant
DesignChecker-Related Features
End-User License Agreement
The latest version of the End-User License Agreement is available on-line at:
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Rev. 170330, Part No. 270941

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Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 3

4 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Figure 4-1. Add Code/Rule Exclusions Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 5

6 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Table 4-1. Exclusion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 7

8 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

SystemVerilog-VHDL Assistant integrates with DesignChecker, which is a design checking

This chapter explains the following topics:

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 9

10 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

DesignChecker can be invoked in several ways from SystemVerilog-VHDL Assistant.

Managing Policies and RuleSets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Managing Policies and RuleSets

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 11

Note that this option is only available if a project is selected.

12 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

2. DesignChecker will be invoked with the Setup tab opened.

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 13

14 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Refer to SystemVerilog-VHDL Assistant Reference Manual for more information.

Configuring Check Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Configuring Check Settings

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 15

16 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Selecting Design Units and Running the

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 17

Investigate Results in the Results Tab

18 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 19

Cross-Referencing Results With Source Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Cross-Referencing Results With Source Views

20 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

5. Investigate the other DesignChecker menu options.

Investigate the Results Summary Pane

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 21

22 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 23

Table 4-1. Exclusion Types

Setting Code/Rule Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Setting Code/Rule Exclusions

24 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Add Code/Rule Exclusions Dialog Box

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 25

Figure 4-1. Add Code/Rule Exclusions Dialog Box

26 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Table 4-2. Add Code/Rule Exclusion Dialog Box Controls (cont.)

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 27

28 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Setting Code/Rule Exclusions Visually

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 29

30 Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2

Using DesignChecker with SystemVerilog-VHDL Assistant, v2018.2 31

Setting Code/Rule Exclusions Manually