A Dynamic-Adjusting Threshold-Voltage Scheme for

FinFETs Low Power Designs

XiaoXin Cui, KaiSheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, and DunShan Yu
Institute of Microelectronics, Peking University
Beijing 100871, People’s Republic of China
Email: [email protected]

Abstract—In this paper, a novel device/circuit co-design scheme, introduced a technique namely self-adjusting threshold-
namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) voltage scheme (SATS) [4], that reduces VTH fluctuation in an
for independent-gate mode FinFET circuits has been proposed. active mode by adjusting substrate bias with a feedback
The main idea of this scheme is that a pair of back-gate bias of control circuit. Seta, K. et al. proposed a standby power
FinFETs is adjusted dynamically to change threshold voltage reduction (SPR) scheme [5] that raises VTH in a standby mode
according to the system operating frequency and operating by switching substrate bias between the power supply and an
mode, which could optimize circuit power, especially leakage external additional supply higher than VDD or lower than
power. The experimental and simulation result shows that the GND. Combine the advantages of SATS and SPR, Kuroda, T.
leakage power dissipation reduced greatly when circuits operate
et al. introduced a variable threshold voltage scheme (VT
at the lower frequency, and the energy-delay product of FinFET
circuits is reduced by 30% approximately.
scheme) [6] to reduce active power dissipation with
negligible overhead in speed, standby power dissipation and
chip area. These schemes are implemented through detecting
I. INTRODUCTION leakage current and converting leakage current to substrate
With the sharp increasing use of portable electronic bias voltage to adjust VTH.
applications, power has become the most important design In this paper, a novel device/circuit co-design scheme,
consideration in deep sub-micron VLSI designs. namely Dynamic-Adjusting Threshold Voltage Scheme
Conventional bulk-MOSFET structure suffers from (DATS) will be introduced, whose main idea is that through
scalability in sub-90nm nodes because of deteriorating device detecting system operating clock and converting different
electrostatics resulting in increased short-channel effects clock frequency to bias voltage, thus adjusting threshold
(SCE). Therefore leakage power has become the major voltage effectively. At the same time, considering FinFETs
contributor to total power especially in the circuits with the have better device characteristic and more design flexibility,
long standby time. especially IG-mode FinFETs, whose front-gate threshold
To reduce leakage power, several innovative low-power voltage could be affected by back-gate bias voltage
techniques are proposed from circuit level to device level. accurately, we innovatively applied DATS to IG-mode
From the viewpoint of the devices, new transistor FinFETs low-power design firstly, and achieved the best
architectures, such as dynamic threshold MOSFET (DTMOS) trade-offs between leakage power and circuit performance. In
[1] and multiple-gate FinFET [2] have been introduced. new scheme, FinFETs’ back-gate voltage is adjusted by bias
FinFETs, for a given channel length, can achieve a better voltage generated by DATS effectively. Thus the threshold
subthreshold slope and drain induced barrier lowering (DIBL) voltage would be scaled down for high performance active
with respect to conventional bulk-MOSFETs, thus reducing switching and would be maintained high in low performance
the leakage power dissipation more effectively. Moreover, or idle mode. DATS can be implemented on-chip or off-chip.
FinFET technology can fabricate transistors with either single In this paper, the system verification method is illustrated and
gate surrounding the silicon fin, that is short-gate (SG) hardware-software co-simulation result shows that the
FinFETs, or two gates which can be independently biased and leakage power dissipation reduced greatly when circuits
controlled, that is independent-gate (IG) FinFETs [3]. The operate at the lower frequency, and the reduction of energy-
IG-mode FinFETs offer more flexibility for low power delay product of FinFET circuits is about 30%.
design. Now, FinFET circuit design has become one of the In section 2, the parameter and the electrical
research focuses on low-power design. characteristics of the FinFETs used in this study is described.
From a circuit perspective, in order to reduce leakage In section 3, FinFETs circuit working mode and test circuit is
power, several circuit-level and system-level technologies shown. Then a principle of the proposed DATS scheme is
including using stacked transistors and by dynamically explained followed by an explanation of the system design
changing the threshold voltage VTH through the body biasing, details in section 4. Section 5 presents the simulation and
have been proposed. Based on this idea, Kobayashi T. et al. experimental results.

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 129

 5.4 250
Gate Propagation Delay Time
Drain
Leakage Power

Propagation Delay Time (10-11 S)

Oxide 5.2
Fin Gate 200

Leakage Power (10-19 W)

Source Fin Drain
5.0 Vbgn=-0.3V;
Gate
Source Vbgp= 1.3V; 150
Oxide
4.8 and
Vth =0.3V
(a) (b) 100
4.6
VD VD VD VD
50
4.4
VG VG VFG VBG VFG VBG

4.2 0
VS VS VS VS
Vbgn=0;Vbgp=1; Vbgn=-0.2;Vbgp=1.2; Vbgn=-0.4;Vbgp=1.4;
SG-mode IG-mode Back-gate Voltage of N-FinFETs (Vbgn) and P-FinFETs (Vbgp) (V)

(c)
Figure 2. Back-gate bias voltage vs. delay and leakage power
Figure 1. FinFET model and schematic (a) three-dimensional diagram (b)
cross sectional top view (c) electrical model schematic The standard expression for leakage current dissipation
due to sub-threshold conduction is shown in (3). Where K is a
II. DEVICE CHARACTERISTICS technology related factor, VT is the thermal voltage which is
temperature dependent and VTH is the threshold voltage.
FinFET is a sort of multi-gate transistor on SOI substrate. Hence, the total power dissipation is the sum of dynamic and
Fig. 1 illustrates the three-dimensional diagram and cross leakage power, shown in (4).
sectional top view of a FinFET transistor respectively.
According to front-gate and back-gate tie up or not, FinFET VGS −VTH VDS
−
nVT VT
circuits can be divided into two basic operating modes, I leakage = K ⋅ e ⋅ (1 − e ) (3)
namely, Shorted-Gate mode (SG) and Independent-Gate
mode (IG). Different circuit operating mode has different
characteristics, which increases the design flexibility.
Ptotal = Pdynamic + Pleakage
The experiment is based on Predictive Technology Model (4)
1 2 n
(PTM) for 32nm FinFET [7], which consist of two SOI = ⋅ V dd ⋅ ∑ C i + V dd ⋅ I leakage
MOSFETs and capacitor coupling between the gates of two 2 i =1
MOSFETs. Considering the capacitor coupling of the front
and back gate, threshold voltage of the front-gate varies in FinFET circuit behavior will be studied by SPICE model
response to the back-gate bias voltage. Formula (1) and circuit-level simulation. An invertor which the ratio of
demonstrates the affect the back-gate bias voltage VBG of device width to device length of N-FinFET is 64nm/32nm
FinFET on the front-gate threshold voltage VTHFG [8], where and P-FinFET is 180nm/32nm as testbench is simulated as
Csi, Coxf, Coxb are body capacitance, front-gate capacitance shown in Fig. 2. When the back-gate voltage increases the
and back-gate capacitance respectively, tsi and tox are the body negative bias gradually, the front-gate threshold voltage will
thickness and gate oxide thickness respectively. Given a increase, which results in an exponential decrease of leakage
reverse increasing δVBG on the bias voltage of back-gate power, while the propagation delay increases as
(decrease the back-gate voltage for N-FinFETs and increase approximately given in (5), where α is typically 1.3 and k is a
the back-gate voltage for P-FinFETs), the front-gate threshold constant. If the back-gate bias voltage is out of the range of
voltage will increase by δVTH. Hereinto equation is effective VTHBG, the influence to leakage power and propagation delay
in range of VBG<VTHBG, VTHBG is the threshold voltage of becomes weak.
back-gate.
k ⋅ C L ⋅ Vdd
δVTH C oxb C si t t pd = (5)
=− ∝ ox (1) (Vdd − VTH )α
δVBG C oxf (Coxb + C si ) t si
III. CIRCUIT DESCRIPTION
A circuit typically dissipates a certain amount of power in
the absence of switching activity. The total power dissipation A schematic diagram of the FinFET experimental circuit
is the sum of the static (leakage) and dynamic power is shown in Fig. 3, where have 3 step pipelines and
contributions. Dynamic power is shown in (2), associating combination logic consist of 100 invertors cascaded. The IG-
with charging and discharging the output capacitive load. mode FinFET circuit is used, the front-gate of N-FinFETs
Where Vdd is power supply, Ci is load capacitance of node i. and P-FinFETs are connected to the regular input signal, the
back-gates of all N-FinFETs are connected together to Port
Vbgn, and the back-gates of all P-FinFETs are connected to
1 n Port Vbgp respectively. Fig. 4 compares the layouts of invertor
Pdynamic = .Vdd2 .∑ Ci (2) and DFF based on SG-mode FinFET standard cell and IG-
2 i =1 mode FinFET standard cells.

130
 Combinational Logic Combinational Logic
VDD
Vbgp

Din D Q D Q D Q Dout

clk
Vbgn
GND
I II III IIII
Figure 3. Schematic diagram of FinFET experimental circuit (a) (b)

VDD
IV. DYNAMIC-ADJUSTING THRESHOLD-VOLTAGE SCHEME
Fig. 5 shows a block diagram of proposed Dynamic-
Adjusting Threshold Voltage Scheme (DATS) to adjust clk
D Q
leakage power according to circuit performance. The DATS clk

circuit consists of Phase Locked Loop (PLL) and Bias

Voltage Generator (BVG). According to different circuit
frequency, the different bias voltage is generated dynamically GND
through the PLL circuit with feed-back loop. Thereinto, the (c)
output voltage of Change Pump (CP) varies directly as input
operating frequency, the different bias voltage of FinFET VDD
circuit is generated dynamically through the BVG circuit.
When circuits work in higher frequency, the back-gate bias
voltage of FinFETs is no bias or forward bias, assuring high- clk
D
Q

clk
speed operation. While in low-speed mode or standby mode,
a reverse back-gate bias is applied to increase the threshold
voltage and to lower the sub-threshold leakage current. GND
One of simple and efficient implementation of BVG (d)
circuit is illustrated in Fig. 6. Block A is a simple follower to
isolate the BVG from previous CP circuit. Block B is a linear Inverter Pass-gate
amplifier to enhance the signal. Block C is a slicer circuit
based on comparator and analog multiplexer. Block D Figure 4. Layouts of invertor and DFF (a) SG-mode invertor (b) IG-mode
reverses the direction of change of the signal. Block E invertor (c) SG-mode DFF (d) IG-mode DFF
reverses and shifts the bias voltage of N-FinFET to get the
Signal Input
bias voltage of P-FinFET. error[n] = Fclock [n] − FVCO [ n] H

++
Amplifier
Counter

V CP V BBN
V. SIMULATION AND RESULTS clk
Bias Voltage Generator

Change
Pump
Threshold
The software-hardware co-verification platform has been DIV — Controlled IG-
built as shown in Fig. 7. DATS circuit consists of PLL and CLK1
mode FinFET
Circuit
BVG. PLL function is implementation based on system-level V BBP
Counter

algorithm simulation tool-MATLAB Simulink, and BVG ÷N VCO

function is designed based on circuit-level simulation tool-

Signal Output
PSPICE. DATS function is validated by MATLAB and
PSPICE co-simulation. Figure 5. Block diagram of DATS

C Analog MUX
A 00

A B A 01
A 10
Y f(u) ref U
U
Fcn Continuous-Time
Port R1 A 11 contrl
Vcp S1 S0 VCO
100kO
R2 var D
D
242kO
DC Continuous-Time VCO
-0.3V Lookup Table PFD
Charge Pump
R6 R7
Port DC Loop Filter
100kO 10kO VBBN -K- Gain
R3 1V
9kO R13
R16 10kO 10kO
R12
R4 Clock
2kO 10kO Port VBBN
R10 10kO
VBBP
R11 R14 R15
R5
10kO
Bad Link
9kO 10kO 10kO
R8 R9
100kO 10kO E VBBP
DC
BVG
0.3V
D
Figure 6. Bias Voltage Generator (BVG) circuit Figure 7. DATS verification platform

131
 The voltages of Ports VBBN and VBBP in verification
platform in Fig. 7 are back-gate bias voltage of FinFET 1.8
Energy Delay Product
circuits, used to adjust threshold voltage of FinFETs and to
control the leakage current according to detecting the system

Energy Delay Product (10 J*s)

1.6
clock. Fig. 8 shows the relationship of propagation delay and

-24
power. The first curve is the output voltage of CP, the second
1.4
and third curves are back-gate bias voltages of P-FinFETs
and N-FinFETs. The fourth and fifth curves are total power
and leakage power of FinFET circuits. As seen from the Fig. 1.2
8, when system frequency increases firstly, then decreases,
and increases again, the output voltage of CP follows with 1.0
system clock frequency, back-gate biases, between 0V to |±
0.3|V, generated from BVG vary inversely as CP output 0.8
voltage, thus the threshold voltage of FinFETs is modulated 0.00 0.05 0.10 0.15 0.20 0.25 0.30
based on (6) [9]. Simulation result shows that circuit operates Bias Voltage (V)
at high frequency, the leakage and total power increase,
assuring high-speed operation, and circuit operates at low Figure 9. Simulated energy-delay product vs. bias voltage
frequency, leakage and total power decrease, assuring low-
power operation. VI. CONCLUSIONS
⎧⎪Vthgf
0
− δ (V gbs − Vthgb ), if V gbs < Vthgb A novel Dynamic-Adjusting Threshold-Voltage Scheme
Vthgf ≈⎨ 0 (6) (DATS) for IG-mode FinFET circuits has been proposed in
⎪⎩Vthgf , other this paper. This scheme can adjust threshold voltage through
detecting system clock, thus optimize circuit power. The
Minimizing the energy-delay (ED) product is a good experimental and simulation result shows that leakage power
approach for optimizing circuit and system. The ED product dissipation decreases greatly when circuits operate at the
is plotted as a function of inversely bias voltage in Fig. 9. The lower frequency, and the reduction of the energy-delay
test data used are the same with Fig. 8. When inverse bias product of FinFET circuits is about 30%.
voltage increase, the threshold voltage become large, power
consumption reduced significantly, and ED product is REFERENCES
reduced by 30% approximately. Therefore, the DATS is an
[1] Assaderaghi, F.; Sinitsky, D.; Parke, S.A.; Bokor, J.; Ko, P.K.;
effective scheme in VLSI low-power design, especially Chenming Hu; “Dynamic threshold-voltage MOSFET (DTMOS) for
FinFET circuit low-power design. ultra-low voltage VLSI”; IEEE Transactions on Electron Devices;
Page(s): 414 – 422, 1997.
0.117 PLL [2] D. Hisamoto; W.-C. Lee; J. Kedzierski; H. Takeuchi; K. Asano; C.
VF to V
VF to V

0.078 Kuo; E. Anderson; T.-J. King, J. Bokor; and C. Hu; “FinFET—A self-
PLL

0.039 aligned double gate MOSFET scalable to 20 nm”; IEEE Trans.

0.000
1661920 1661920 1599520 Electron Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000.
1.3 [3] Prate ek Mishra; Anish Mutt reja; Niraj K. Jha; “FinFET Circuit
1.2 Design”; Nanoelectronic Circuit Design, (Eds.)N.K. Jha and D. Chen,
Vpback
(V)

1.1
DOI 10.1007/978-1-4419-7609-3_2, ○ C Springer Science+Business
Back-gate Vol Media, LLC 2011.
1.0 for P-FinFETs
[4] Kobayashi, T.; Sakurai, T.; “Self-adjusting threshold-voltage scheme
0.0 Back-gate Vol (SATS) for low-voltage high-speed operation”; in Proc. CICC94,
for N-FinFETs
Vnback

-0.1
(V)

Page(s): 271 – 274, 1994.

-0.2
[5] Seta, K.; Hara, H.; Kuroda, T.; Kakumu, M.; Sakurai, T.; “50% active-
-0.3 power saving without speed degradation using standby power reduction
(SPR) circuit”; IEEE International Solid-State Circuits
FinFET Circuit FinFET Circuit

2.64
Leakage Power Total Power
( X10-15 W )

Total Power Conference(ISSCC), Papers. Page(s): 318 - 319, 1995.

2.31
[6] Kuroda, T.; Fujita, T.; Mita, S.; Nagamatu, T.; Yoshioka, S.; Sano, F.;
1.98
Norishima, M.; Murota, M.; Kako, M.; Kinugawa, M.; Kakumu, M.;
1.65
Sakurai, T., “A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine
330
transform core processor with variable-threshold-voltage scheme”;
( X10-17 W )

220 Leakage Power ISSCC, Page(s): 166 - 167, 437, 1996.

110
[7] Nanoscale Integration and Modeling (NIMO) Group at ASU, PTM:
0 http://ptm.asu.edu/.2005.
[8] Jin Ouyang; Yuanxie; “Power Optimization for FinFET-based Circuits
40

0
40

04

40
0

Using Genetic Algorithms”; IEEE International Conference on SOC,

87

74

87

74
15

16

15

16

page(s): 211 – 214, Sept. 2008.

Input Frequency ( kHz )
The frequency rises firstly, then falls, and rises finally. [9] Vishal P. Trivedi; Jerry G. Fossum; Weimin Zhang; “Threshold voltage
and bulk inversion effects in nonclassical CMOS devices with undoped
ultra-thin bodies”; Solid-State Electronics 2007.51:pp.170–178, 2007.
Figure 8. Simulation result of DATS

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